Patent Application
20120292670
1. Field of the Invention
The present invention relates to semiconductor devices and their manufacture, and more particularly relates to a method and structure of making a field effect transistor having silicided regions, particularly field effect transistors having stressed liners.
2. Description of the Related Art
Field effect transistors (“FETs”) in advanced technologies are semiconductor devices each of which contains a semiconductor region which incorporates a source region, a drain region, and a channel region between the source and drain regions. FETs typically have silicide regions contacting their source and drain regions. The silicide regions, which are more conductive than the source and drain regions, help increase the flow of current through the FET. To increase the performance of the FET, such as the speed at which the FET may switch between on and off states, a stressed dielectric liner may be formed on the silicide regions which applies a stress to the source, drain and the channel regions of such FET.
Silicide regions in FETs typically are formed by depositing a metal onto the source and drain regions and sometimes also the gates of the FETs, and then heating the FET to a temperature such as 400 to 450 degrees Celsius (hereinafter “° C.”) at which the metal reacts with the semiconductor material to form the silicide. Then, the stressed dielectric liner is formed on the silicide regions and other portions of the FETs at a temperature such as 400 to 480° C. The stressed dielectric liner may apply a stress to the semiconductor region of the transistor, i.e., the source, drain and channel regions, which has a magnitude exceeding one gigapascal (hereinafter “GPa”).
In subsequent processing, a relatively thick dielectric layer can be formed covering the FET, and electrically conductive contacts are formed which extend through the thick dielectric layer and contact the silicide regions to electrically connect with the source and drain regions and the gate of the FET.
Further improvements can be provided in the fabrication of FETs having silicide regions and stressed liners.
According to an aspect of the invention, a method is provided of fabricating a semiconductor device. Such method includes implanting a species into a silicide region contacting a semiconductor region of a substrate. A stressed liner may then be formed overlying the silicide region having the implanted species therein. According to a particular aspect of the invention, a conductive via can be formed which extends through the stressed liner and is electrically connected with the semiconductor region.
According to a particular aspect, prior to forming the stressed liner, within an interval less than one second, a step of annealing can be performed to elevate at least a portion of the silicide region to a peak temperature ranging from 800 to 950° C. Examples of annealing processes are laser spike annealing and flash annealing, either or both of which may be used. In one example, the interval can be limited to less than 10 milliseconds. In a particular example, the peak temperature can be at least 900° C. and the interval can be less than 10 milliseconds.
In a particular example, the annealing may include at least one of laser spike annealing or flash annealing, the peak temperature may be approximately 950° C. and the annealing can maintain at least a portion of the silicide region at the peak temperature ranging from 0.1 millisecond to 10 milliseconds.
In one example, the implanting step can produce a distribution of the implanted species centered at a depth within the silicide region which is less than a depth at which the silicide regions contact the semiconductor region. In a particular example, the centered depth may be less than or equal to a depth at a midpoint of the thickness of the silicide region above the semiconductor region.
The implanted species can include at least one of carbon, nitrogen, boron, boron fluoride or arsenic. The implanting step can be performed at an energy between about 0.2 keV and 10 keV. A typical dose of the implanted species can be between 5×1014cm−2 and 5×1015cm−2.
The stressed liner typically has a stress greater than one gigapascal (GPa) in magnitude, and the silicide region typically consists essentially of a silicide of at least one of nickel, platinum, or palladium.
A method of fabricating a semiconductor device according to a particular aspect of the invention may include: implanting a species of at least one of carbon, nitrogen, boron, boron fluoride or arsenic at a dose between about 5×1014cm−2 and about 5×1015cm−2 into a silicide region, the silicide region contacting a semiconductor region of a substrate, to produce a distribution of the implanted species centered at a depth within the silicide region which is less than a depth at which the silicide region contacts the semiconductor region. The silicide region may consist essentially of a silicide of at least one of nickel, platinum, or palladium Annealing may be performed within an interval of less than one second to elevate at least a portion of the silicide region to a peak temperature between 800 and 950° C. After the annealing, a stressed liner can be formed which has a stress of at least one gigapascal in magnitude overlying the at least a portion of the silicide region having the implanted species therein.
In a particular aspect of the invention, a conductive via can be formed which extends through the stressed liner and is electrically connected with the semiconductor region.
A semiconductor device according to an aspect of the invention can include: a semiconductor region of a substrate having a first portion having a first conductivity type and second portions extending from edges of the first portion and having a second conductivity type opposite the first conductivity type, the first and second portions having major surfaces. A gate may overlie the major surface of the first portion of the semiconductor region. A silicide region may overlie and contact the major surfaces of the second portions of the semiconductor region. The silicide region may contain at least one implanted species selected from the group consisting of carbon, nitrogen, boron, boron fluoride and arsenic having a distribution centered at a depth within the silicide region which is less than depths of the major surfaces of the second portions of the semiconductor region. The silicide region may consist essentially of a silicide of at least one of nickel, platinum, or palladium. Dielectric spacers may separate the gate from the silicide region, and a stressed liner may overlie the silicide region having the implanted species therein. The dielectric spacers may have the at least one implanted species therein, the implanted species having a distribution centered at a particular depth internally within the dielectric material of the dielectric spacers.
In a particular aspect of the invention, a plurality of conductive vias may extend through the stressed liner and be electrically connected with the semiconductor region. A silicide region may overlie and be electrically connected with the gate, and a conductive via may extend through the stressed liner and be electrically connected with of the silicide region overlying the gate.
Advanced semiconductor chips typically incorporate very large numbers, e.g., billions, of semiconductor devices such as FETs. To fabricate semiconductor chips which operate reliably throughout their intended lifetimes, the incidence of failure in each chip must be reduced to an extent in which no more than a few isolated device failures is likely to occur during the entire lifetime of the chip.
In FETs that have silicide regions and stressed dielectric liners, the inventors recognize that the process of forming the stressed liner can negatively affect the silicide regions. The formation of a stressed liner at temperatures, e.g., 500° C. or above, which is above a temperature, e.g., 400 to 450° C. at which the silicide regions are formed, can cause the silicide region to develop voids in which the silicide region has insufficient coverage or insufficient thickness in certain areas on the surface of the source region and the drain region. Voids in the silicide regions can increase electrical resistance of the silicide regions, and may in some cases cause the later formed conductive contacts to fail, or may cause electrical circuits which incorporate FETs to fail.
The inventors recognize that voids in the silicide regions may pose even greater risks to FET performance as the size of FETs shrinks further in future generations and the voids may occupy a proportionally greater area of the silicide regions. The techniques and structures described herein may help to reduce the risk that voids may form in silicide regions of FETs having stressed dielectric liners, or may help to reduce the size of voids which can form.
Accordingly,
In one example, a silicided FET can be a FET such as made according to an advanced semiconductor technology in which the length of the channel region of the transistor is less than 50 nanometers, and may be quite smaller. At such dimension, the widths, i.e., the smallest dimensions of the source region and the drain region in a direction along their surfaces in contact with the silicide regions may in one example range from a few tens of nanometers to a few hundred nanometers. At these dimensions, silicide regions which have voids greater than a few nanometers in width could significantly impact the performance of at least some FETs on an integrated circuit, and can cause the incidence of device failures on the semiconductor chip to increase beyond the established tolerable limit. Processing as further described below may reduce the width of or number of voids in the silicide regions of silicided devices such as FETs which have stressed liners thereon.
According to the embodiment shown in
Examples of species that can be implanted include carbon, nitrogen, boron, boron fluoride, and arsenic. Carbon or nitrogen species do not alter the conductivity type (p-type or n-type) of the semiconductor region that the species reaches during the implanting step. Either carbon, nitrogen, or both carbon and nitrogen can be implanted into silicide regions contacting underlying semiconductor regions which have either p-type or n-type conductivity. However, other species such as boron, boron fluoride and arsenic are commonly used as dopants in creating p-type semiconductor regions in the case of boron, and in creating n-type semiconductor regions in the case of arsenic. Therefore, boron, or boron fluoride are each a species which can be selectively implanted into silicide regions which contact underlying p-type conductivity regions, and arsenic is a species which can be selectively implanted into silicide regions which contact underlying n-type conductivity regions. In a particular embodiment, a mask such as a photoresist mask can be used during the implanting process to limit the implanting of a dopant material such as boron or boron fluoride to semiconductor devices such as PFETs which have silicide regions contacting underlying semiconductor regions of p-type conductivity. Similarly, a mask such as a photoresist mask can be used during the implanting process to limit the implanting of a dopant material such as arsenic to semiconductor devices such as NFETs which have silicide regions contacting underlying semiconductor regions of n-type conductivity.
In an example, the implant can be performed at an energy between 0.2 kilo-electron-volts (“keV”) and 10 keV. In one example, the dose of the implanted species can be between 5×1014cm−2 and 5×1015cm−2. As shown in
In a particular example, the depth at which the implant is centered within the silicide region 210 can be less than or equal to a depth at a midpoint of the thickness 224 of the silicide regions 210 in a direction perpendicular to the major surfaces 236 of the source and drain regions 212, 214 in contact therewith. The same relationship can apply to the depth at which the implant is centered within the silicide region 220, as less than or equal to a depth at a midpoint of the thickness 226 of the silicide region 220 in a direction perpendicular to the surfaces of the source and drain regions 212, 214 in contact therewith. Typical thicknesses of the silicide regions 210 (and the silicide region 220 when present) are from a few nanometers to a few tens of nanometers.
As seen in
As further shown in
Referring again to
Alternatively, when the semiconductor device is an n-type FET or (“NFET”), the source and drain regions 212, 214 thereof can have n-type conductivity, and a stressed liner having tensile stress can be formed atop the source and drain regions. In such case, the tensile stressed liner can apply a tensile stress to the channel region of the NFET which improves the performance of the NFET. The value of the tensile stress typically has a magnitude greater than 1.0 gigapascals (“GPa”). In a particular example, the tensile stress can have a value such as 1.7 GPa.
After the forming (130) of the stressed liner, in further processing can include forming conductive contacts (140) such as conductive vias which electrically connect the source and drain regions and gate of the FET to other circuitry (not shown) of the semiconductor chip. For example, as seen in
Thereafter, columns of conductive material are formed within the openings to form the conductive vias or contacts 340. The conductive material typically includes a metal, a conductive compound of a metal or both. In particular examples, the conductive material can be formed by first depositing an adhesion layer or possibly a conductive barrier layer containing titanium adjacent walls 342 of the openings, after which a second conductive material can be deposited. The second conductive material can include one or more of tungsten, cobalt, phosphorus or a combination thereof, among other possible materials or combinations of materials. With this step, the semiconductor device structure is completed, and subsequent processing can be applied to electrically interconnect the conductive contacts 340 with other conductive structure (not shown) such as horizontally extending metal wiring lines and metal vias which vertically interconnect metal wiring lines at different levels of the chip.
In a particular example, the very short duration anneal can elevate the annealed areas to a peak temperature from 800 to 950° C. within an interval of less than one second. Typically the peak temperature is at least 900° C. and the interval is less than 10 milliseconds. In a particular example, the short duration anneal reaches a peak temperature of approximately 950° C. within at least portions of the silicide regions of the semiconductor devices and maintains the peak temperature therein for an interval ranging from 0.1 to 10 milliseconds.
After the short duration anneal, processing can continue with forming a stressed liner (130) and subsequently forming conductive contacts (140) to the semiconductor devices, as described above relative to
In one example, when the channel region of the FET consists essentially of silicon, the stressed semiconductor regions may include an alloy of silicon with another semiconductor material. Typically, when the semiconductor device is an PFET, the stressed semiconductor regions may include a compressive stressed alloy of silicon such as silicon germanium, which can be formed within the source and drain regions by epitaxial growth of the stressed semiconductor region. In another typical example, when the semiconductor device is an NFET, the stressed semiconductor regions may include a tensile stressed alloy of silicon such as silicon carbon. However, it is possible for tensile stressed semiconductor regions to be provided in device regions of PFETs or for compressive stressed semiconductor regions to be provided in device regions of NFETs, such as, for example, in integrated circuits in which only one type of stressed semiconductor region may be provided.
The stressed semiconductor regions 410 can underlie the silicide regions 210. For example, as particularly shown in
The above description sets forth a variety of materials and process conditions which can be used in carrying out a method of fabricating a semiconductor device according to various embodiments of the invention. In a particular example of a process according to the embodiment of
While the invention has been described in accordance with certain preferred embodiments thereof, those skilled in the art will understand the many modifications and enhancements which can be made thereto without departing from the true scope and spirit of the invention, which is limited only by the claims appended below.
