The present disclosure relates to networking equipment.
Transporting power into the center of an application specific integrated circuit (ASIC) for ASIC core power and ASIC serializer-de-serializer (SERDES) power at levels beyond 1000 amps can be very burdensome on layer count, power plane resistance, and high speed signaling. A substantial portion of the ASIC circuit board layers would be used for power. These additional layers are a significant cost adder to the printed circuit board.
Presented herein are techniques to move high current power distribution layers for integrated circuit core power and serializer-deserializer (SERDES) power into a center area of the integrated circuit footprint. This provides a more reliable and higher current distribution into the center of a large integrated circuit footprint, without causing disruption of high speed signal routing or increased signal integrity burden to the high speed signals.
Briefly, according to one aspect, an apparatus is provided that includes a main printed circuit board and a power block printed circuit board. The main printed circuit board has a first (top) side and a second (bottom) side opposite the first side. The main printed circuit board has an open section over which an integrated circuit is configured to attach to the first side of the main printed circuit. The power block printed circuit board is sized and shaped to fit into the open section of the main printed circuit board. The power block printed circuit board has a first side that is configured to electrically connect to the integrated circuit to provide power to the integrated circuit.
According to another aspect, a method is provided. The method includes providing a main printed circuit board having a top and a bottom, the main printed circuit board having an open section that extends between the top and bottom; mounting an integrated circuit to a top of the main printed circuit board over the open section so that at least a portion of the bottom of the integrated circuit is exposed over the open section; and inserting a power block printed circuit board into the open section of the main printed circuit board from below so that a top of the power block printed circuit board makes electrical contact to the bottom of the integrated circuit.
In a most central area of the IC 120, shown by dotted box designating a core power area 130, is where “core” power needs to be provided for the IC core functionality. For example, the core power area 130 may need 500 amps (A) or more of power. Between the core power area 130 and another area 140 outside of the core area 130, there may be another area that needs a substantially amount of current, such as 1200 A, for example, such as for SERDES functions.
Then, there are other functions of the IC 120 outside the area 140 that need power as well as electrical connections for high-speed data, for example.
In certain applications where the PCB 110 has 50 layers (also called planes), as much as one-third of the layers may be dedicated to routing signal traces for receive signaling, the middle one-third of the layers may be dedicated for transmit signal traces and the remaining/bottom one-third of the layers may be dedicated to signal traces for power. Moreover, power to the areas 130 and 140 of the IC 120 is deployed on the outer areas of the PCB 110 and brought in from the sides of the IC 120 toward the center of the IC 120 through the numerous layers of the PCB 110 that also needs to provide traces for all the associated signal/data handled by the IC. Thus, such a PCB can be very complicated to design and expensive to build.
Presented herein are configurations and techniques to move high current power layers for core power for an integrated circuit and SERDES power into a center area of the integrated IC footprint, bringing the power in from below to as many parts of the IC and surrounding PCB functions. Briefly, presented herein is a PCB apparatus or arrangements that include a main PCB having a first (top) side and a second (bottom) side opposite the first side. The main printed circuit board having an open section that may be created by routing or otherwise removing PCB material in a volume that extends between the first side and the second side. An integrated circuit is provided that is configured to attach to the first side of the main PCB over the open section of the main printed circuit board. A power block PCB is provided that is sized and shaped to fit into the open section of the main PCB. The power block PCB has a first (top) side that is configured to electrically connect to bottom of the integrated circuit to provide power to the integrated circuit. More specifically, the arrangement of electrical connection features (e.g., pin field or ball grid array) on the first side of the power block PCB is in a pattern that is configured to mate with electrical connection features on the bottom of the integrated circuit. No changes need to be made to the design of the integrated circuit to operate in this PCB arrangement. The integrated circuit is completely agnostic to receiving power from the power block PCB rather than from the main PCB.
Reference is now made to
The cross-sectional view of
With the central area removed from the main PCB 210 to create the open section 212, the PCB 210 may be plated. The core power is not provided by the main PCB 210, but the SERDES power vias and BGA pads are still in place. The SERDES power is accessible for connection laterally from inside the central area as shown at 218 in
A power block PCB 230 (also called a power plug PCB or power plug) is provided that is sized and shaped to fit within the open section 212 of the main PCB 210. The power block PCB 230 may be fabricated of the same types of materials, using the same types of technologies as used to fabricate the main PCB 210, to create conductive traces and layers of electrically insulating material.
The power block PCB 230 has a first (top) side 232 that includes a pin field or ball grid array 234 that is in an pattern appropriate and configured to electrically connect to the ball grid array or pin field 226 on the IC 220. In one example, the pin field or ball grid array 234 on the first side 232 of the power block PCB 230 is in a pattern that is configured to mate with the pin field or ball grid array 226 on the IC 220 to supply core power to the IC 220.
As is known in the art, there are specifications set for how flat the entire PCB needs to be, in order for all the pins of the IC 220 to solder on evenly, without breaking, etc. When the power block PCB 230 is inserted into the main PCB 210, mechanisms are employed to ensure that the top of the power block PCB 230 is co-planar with the top of the main PCB 210. Examples of mechanism to adhere/affix the power block PCB 230 to the main PCB 210 include metallization/sintering using a conductive paste, as well as spring-loaded, clips, etc., as described further below. The design of the IC 220 is completely independent of the power block PCB arrangement and needs no design alterations. When the power block PCB 230 is inserted into the main PCB 210, and secured to the main PCB 210 using any of the techniques described herein, the power block PCB 210 replaces the routed out part of the main PCB 210.
The power block PCB 230 may provide power, from beneath the IC 220, to the “heavier” or core power needs of the IC 220 (e.g., 500-800 A). In addition, the power block PCB 230 may provide power laterally into the main PCB 210 for other power needs (e.g., 250-400 A). This can be particularly advantageous to supply power to application specific ICs (ASICs) that perform substantial power heavy signal processing functions, such as for electrical or optical signal transmission and reception, video signal processing, etc.
By moving a large amount of the power delivery functions to the power block PCB 230 that is arranged at a central area of the IC, the number of layers of the main PCB 210 can be reduced/minimized. These techniques fundamentally change how to transport power into an IC.
Reference is now made to
The power block PCB 300 may be made from several layers 320 (e.g., of 3 oz copper) for very high current delivery to the BGA pad 314 with minimal loss. The power block PCB 300 may include vertical conductive stripe traces 322 and 324 on the sides 312 for multiple different/independent pairs of power and ground rails (of different power levels), respectively, that connect laterally into conductive traces in the main PCB.
The power block PCB 300 may include power studs 330 and 332 for receiving input power to be delivered by the power block PCB 300 to the IC and main PCB. Several bus bar or cabling methods may be used to deliver current to the power block PCB 300 for IC core power and SERDES power, as well as other power needs. A bus bar integrated point of load (POL) may be employed. Connection of the bus bars or wires may be made, from beneath the power block PCB 300, by solder attach or by stud mount attach to the power studs 330 and 332. There may be several power studs on the power block PCB 300, and only one pair is shown in
Reference is now made to
The saw-tooth configuration of
Reference is now made to
Reference is now made to
A spring mechanism may be used to bias a pressure plate 540 upwards against the main PCB 510 to ensure sufficient is applied to maintain BGA contact between the power block PCBs and the IC 520. In this regard,
Reference is now made to
As explained above, the power block printed circuit board may be secured to the main printed circuit board using a conductive paste and sintering process, and/or one engaging one or more spring clips.
At step 1120, the method 1100 includes inserting and mounting the power block printed circuit board into the open section of the main printed circuit board and using a sintering process to secure the power block printed circuit board in place, and in some arrangements, additionally using a fixture mechanism (many of which are described above) to maintain a co-planar arrangement between the top of the main printed circuit board and the top of the power block printed circuit board.
At step 1130, the method 1100 includes mounting an integrated circuit to a top of the main printed circuit board over the power block so that at least a portion of the bottom of the integrated circuit is exposed over the power block printed circuit board and a top of the power block printed circuit board makes electrical contact to the bottom of the integrated circuit. The integrated circuit is then secured to the main printed circuit board (and power block printed circuit board) using a reflow process and associated known methods or reflow techniques.
In summary, arrangements and methods are presented herein for routing out the core power area of a printed circuit board under an IC and replacing it with a custom power block/plug printed circuit board that is attached by a metalized paste sintering process or other techniques to the main printed circuit board. As an example, this may be used for power delivery for ASICs or other high-power ASICs or other ICs (e.g., those drawing 1 kW or more) and is advantageous over other power delivery methods heretofore known.
In some aspects, the techniques described herein relate to an apparatus including: a main printed circuit board having a first side and a second side opposite the first side, the main printed circuit board having an open section; an integrated circuit configured to attach to the first side of the main printed circuit board over the open section of the main printed circuit board; and a power block printed circuit board sized and shaped to fit into the open section of the main printed circuit board, the power block printed circuit board having a first side that is configured to electrically connect to the integrated circuit to provide power to the integrated circuit.
In some aspects, the techniques described herein relate to an apparatus, wherein the power block printed circuit board includes multiple layers between the first side and the second side, and side planes around a periphery, the side planes configured to laterally contact and electrically connect with layers in the main printed circuit board to provide power into the main printed circuit board.
In some aspects, the techniques described herein relate to an apparatus, wherein the side planes around the periphery of the power block printed circuit board include a tooth pattern such that each tooth of the tooth pattern has at least two faces that supports power or ground side rails.
In some aspects, the techniques described herein relate to an apparatus, wherein each tooth of the tooth pattern is flattened to create three faces, each of which supports power or ground side rails.
In some aspects, the techniques described herein relate to an apparatus, wherein the open section of the main printed circuit board is sized and shaped to accommodate the tooth pattern on the periphery of the power block printed circuit board.
In some aspects, the techniques described herein relate to an apparatus, wherein the power block printed circuit board is secured to the main printed circuit board by sintering of a metallization paste.
In some aspects, the techniques described herein relate to an apparatus, further including one or more spring clips to secure the power block printed circuit board to the second side of the main printed circuit board.
In some aspects, the techniques described herein relate to an apparatus, further including: a frame that engages a second side of the power block printed circuit board; and a spring mechanism configured to bias the frame to apply pressure between the power block printed circuit board and the integrated circuit.
In some aspects, the techniques described herein relate to an apparatus, wherein the first side of the power block printed circuit board includes a pin field or ball grid array that is configured to electrically connect to a pin field or ball grid array of the integrated circuit.
In some aspects, the techniques described herein relate to an apparatus, wherein the pin field or ball grid array on the first side of the power block printed circuit board is in a pattern that is configured to mate with the pin field or ball grid array on the integrated circuit to supply core power to the integrated circuit.
In some aspects, the techniques described herein relate to an apparatus, wherein the power block printed circuit board has a thickness that is greater than a thickness of the main printed circuit board and is secured to the main printed circuit board in the open section so that the first side of the power block printed circuit board is co-planar with the first side of the main printed circuit board, and the second side of the power block printed circuit board extends beyond the second side of the main printed circuit board.
In some aspects, the techniques described herein relate to an apparatus, further including a cold plate having an open section configured to fit over a portion of the power block printed circuit board that extends beyond the second side of the main printed circuit board, wherein the cold plate is configured to dissipate heat from the power block printed circuit board.
In some aspects, the techniques described herein relate to an apparatus, wherein the cold plate has multiple cooling zones through which a heat exchange fluid is directed.
In some aspects, the techniques described herein relate to an apparatus, further including a plurality of power block printed circuit boards that collectively fit into and fill the open section of the main printed circuit board, each of the plurality of power block printed circuit boards having a first side that is configured to electrically connect to the integrated circuit to provide power to the integrated circuit.
In some aspects, the techniques described herein relate to an apparatus, wherein the integrated circuit includes a die and a substrate, wherein the die is mounted on the substrate, wherein the substrate has an open section that is aligned with at least part of the open section in the main printed circuit board, and the power block printed circuit board extends through the open section of the substrate so that the first side of the power block printed circuit board makes electrical contact with the die.
In some aspects, the techniques described herein relate to an apparatus including: a main printed circuit board having a top and a bottom, the main printed circuit board having an open section over which an integrated circuit is configured to attach; and a power block printed circuit board configured to fit into the open section of the main printed circuit board, the power block printed circuit board having a top that electrically connects to the integrated circuit to provide power to the integrated circuit from below.
In some aspects, the techniques described herein relate to an apparatus, wherein the power block printed circuit board includes multiple layers between the top and bottom, and side planes around a periphery, the side planes configured to laterally contact and electrically connect with layers in the main printed circuit board to provide power into the main printed circuit board.
In some aspects, the techniques described herein relate to an apparatus, wherein the side planes around the periphery of the power block printed circuit board include a tooth pattern such that each tooth of the tooth pattern has at least two faces that supports power or ground side rails, and wherein the open section of the main printed circuit board is sized and shaped to accommodate the tooth pattern on the periphery of the power block printed circuit board.
In some aspects, the techniques described herein relate to an apparatus, wherein the top of the power block printed circuit board includes a pin field or ball grid array that is configured to electrically connect to a pin field or ball grid array of the integrated circuit, wherein the pin field or ball grid array on the top of the power block printed circuit board is in a pattern that is configured to mate with the pin field or ball grid array on the integrated circuit to supply core power to the integrated circuit.
In some aspects, the techniques described herein relate to an apparatus, further including a plurality of power block printed circuit boards that collectively fit into and fill the open section of the main printed circuit board, each of the plurality of power block printed circuit boards having a top that is configured to electrically connect to the integrated circuit to provide power to the integrated circuit.
In some aspects, the techniques described herein relate to a method including: providing a main printed circuit board having a top and a bottom, the main printed circuit board having an open section that extends between the top and bottom; mounting an integrated circuit to a top of the main printed circuit board over the open section so that at least a portion of the bottom of the integrated circuit is exposed over the open section; and inserting a power block printed circuit board into the open section of the main printed circuit board from below so that a top of the power block printed circuit board makes electrical contact to the bottom of the integrated circuit.
In some aspects, the techniques described herein relate to a method, further including securing the power block printed circuit board to the main printed circuit board using a conductive paste and sintering process, and/or one engaging one or more spring clips.
The above description is intended by way of example only. Although the techniques are illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made within the scope and range of equivalents of the claims.
As used herein, unless expressly stated to the contrary, use of the phrase ‘at least one of’, ‘one or more of’, ‘and/or’, variations thereof, or the like are open-ended expressions that are both conjunctive and disjunctive in operation for any and all possible combination of the associated listed items. For example, each of the expressions ‘at least one of X, Y and Z’, ‘at least one of X, Y or Z’, ‘one or more of X, Y and Z’, ‘one or more of X, Y or Z’ and ‘X, Y and/or Z’ can mean any of the following: 1) X, but not Y and not Z; 2) Y, but not X and not Z; 3) Z, but not X and not Y; 4) X and Y, but not Z; 5) X and Z, but not Y; 6) Y and Z, but not X; or 7) X, Y, and Z.
Note that in this Specification, references to various features (e.g., elements, structures, nodes, modules, components, engines, logic, steps, operations, functions, characteristics, etc.) included in ‘one embodiment’, ‘example embodiment’, ‘an embodiment’, ‘another embodiment’, ‘certain embodiments’, ‘some embodiments’, ‘various embodiments’, ‘other embodiments’, ‘alternative embodiment’, and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.
Each example embodiment disclosed herein has been included to present one or more different features. However, all disclosed example embodiments are designed to work together as part of a single larger system or method. This disclosure explicitly envisions compound embodiments that combine multiple previously-discussed features in different example embodiments into a single system or method.
Additionally, unless expressly stated to the contrary, the terms ‘first’, ‘second’, ‘third’, etc., are intended to distinguish the particular nouns they modify (e.g., element, condition, node, module, activity, operation, etc.). Unless expressly stated to the contrary, the use of these terms is not intended to indicate any type of order, rank, importance, temporal sequence, or hierarchy of the modified noun. For example, ‘first X’ and ‘second X’ are intended to designate two ‘X’ elements that are not necessarily limited by any order, rank, importance, temporal sequence, or hierarchy of the two elements. Further as referred to herein, ‘at least one of’ and ‘one or more of’ can be represented using the ‘(s)’ nomenclature (e.g., one or more element(s)).
As used herein, the terms “approximately,” “generally,” “substantially,” and so forth, are intended to convey that the property value being described may be within a relatively small range of the property value, as those of ordinary skill would understand. For example, when a property value is described as being “approximately” equal to (or, for example, “substantially similar” to) a given value, this is intended to convey that the property value may be within +/−5%, within +/−4%, within +/−3%, within +/−2%, within +/−1%, or even closer, of the given value. Similarly, when a given feature is described as being “substantially parallel” to another feature, “generally perpendicular” to another feature, and so forth, this is intended to convey that the given feature is within +/−5%, within +/−4%, within +/−3%, within +/−2%, within +/−1%, or even closer, to having the described nature, such as being parallel to another feature, being perpendicular to another feature, and so forth. Mathematical terms, such as “parallel” and “perpendicular,” should not be rigidly interpreted in a strict mathematical sense, but should instead be interpreted as one of ordinary skill in the art would interpret such terms. For example, one of ordinary skill in the art would understand that two lines that are substantially parallel to each other are parallel to a substantial degree, but may have minor deviation from exactly parallel.
The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible, or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).
One or more advantages described herein are not meant to suggest that any one of the embodiments described herein necessarily provides all of the described advantages or that all the embodiments of the present disclosure necessarily provide any one of the described advantages. Numerous other changes, substitutions, variations, alterations, and/or modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and/or modifications as falling within the scope of the appended claims.
This application claims priority to U.S. Provisional Application No. 63/596,989, filed Nov. 8, 2023, the entirety of which is incorporated herein by reference.
Number | Date | Country | |
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63596989 | Nov 2023 | US |