Patent Application
20240047517
Power MOSFETs (metal-oxide-semiconductor field-effect transistors) are designed to handle significant voltages and are widely used in many types of power electronics applications such as power converters, power supplies, motor controllers, etc. Superjunction techniques, which are based on the idea of charge balancing in the transistor drift region, reduce the resistance of the drift region, which can be the largest resistance contributor in high voltage MOSFETs. Termination designs for superjunction MOSFETs use extra process steps to introduce dedicated termination structures. Such dedicated termination structures may be additional dedicated termination implants or trench isolation structures having the sole purpose of terminating the active circuits with no other active function. The addition of extra process steps to introduce dedicated termination structures adds cost, cycle time, and complexity to the process without adding any performance advantage.
Thus, there is a need for an improved termination design for superjunction MOSFETs.
According to an embodiment of a method of producing a power semiconductor device, the method comprises: forming a plurality of trench gate structures in an active cell region of a semiconductor substrate, the plurality of trench gate structures extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; covering the plurality of trench gate structures with an electrically insulating material; forming, using a common mask, first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region and second contact openings vertically aligned with the trench gate structures in the inactive cell region; and implanting, using a common implantation process, a dopant species into the semiconductor substrate through the first contact openings and the second contact openings to form first counter-doped regions between the adjacent trench gate structures in the active cell region and second counter-doped regions underneath the trench gate structures in the inactive cell region.
According to an embodiment of a power semiconductor device, the power semiconductor device comprises: a plurality of trench gate structures in an active cell region of a semiconductor substrate, the plurality of trench gate structures extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the plurality of trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
The embodiments described herein provide a termination design and process that uses deep charge balancing implants underneath gate bus contacts as an active component of the termination structure. By using a deep charge balance implant under a contact in combination with a contact into a gate trench, the gate oxide is protected from drain potential and drops the drain potential from the backside of the device before reaching the active surface. The embodiments described herein may be used with charge balanced (superjunction) medium voltage power MOSFETS, e.g., in the range of 30V to 60V to reduce the number of process steps, allowing cost of manufacture or wafer cost in silicon foundries to be reduced. In addition, improved yield may be realized by the self-aligned nature of the termination charge balancing structure to the cell structure.
Described next with reference to the figures are embodiments of the termination design and methods of implanting the termination design.
The power semiconductor device 100 includes a semiconductor substrate 102. The semiconductor substrate 102 comprises one or more semiconductor materials that are used to form transistor cells of the power transistor device such as, e.g., Si or SiC power MOSFET cells. For example, the semiconductor substrate 102 may comprise Si, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The semiconductor substrate 102 may be a bulk semiconductor material or may include one or more epitaxial layers grown on a bulk semiconductor material.
Two (2) adjacent transistor cells TC are shown in the partial cross-sectional view of
Each transistor cell TC includes a source region 104 of a first conductivity type and a body region 106 of a second conductivity type opposite the first conductivity type. The source region 104 of each transistor cell TC is separated from a drift zone 108 of the first conductivity type by the corresponding body region 106. In the case of a Si or SiC power MOSFET, a drain region 110 adjoins the drift zone 108 at the back surface 112 of the semiconductor substrate 102.
The first conductivity is n-type and the second conductivity type is p-type for an n-channel device whereas the first conductivity is p-type and the second conductivity type is n-type for a p-channel device. For either n-channel or p-channel devices, the source region 104 and the body region 106 included in the same semiconductor mesa 114 form part of a transistor cell TC and the transistor cells TC are electrically connected in parallel between source (S) and drain (D) terminals of the power semiconductor device 100 to form a power transistor such as a Si or SiC power MOSFET.
The body regions 106 may include a body contact region 116 of the second conductivity type and having a higher doping concentration than the body regions 106, to provide an ohmic connection with a source metallization 118 through a contact structure 120 that extends through an electrically insulating material 122 that separates the source metallization 118 from the underlying semiconductor substrate 102. The source regions 104 are also electrically connected to the source metallization 118 through the contact structure 120.
Stripe-shaped trench gate structures 124 extend from a front surface 126 of the semiconductor substrate 102 and into the substrate 102. The trench gate structures 124 are ‘stripe-shaped’ in that the trench gate structures 124 have a longest linear dimension in a direction which runs in and out of the page in
Each trench gate structures 124 includes an electrically conductive material 128 such as polysilicon or a metal or metal alloy that forms a gate electrode and a gate dielectric insulating material 130 that separates the gate electrode material 128 from the surrounding semiconductor substrate 102. The gate electrode material 128 is electrically connected to a gate terminal ‘G’ of the power semiconductor device 100 through, e.g., metal gate runners 132 and respective contacts/vias 134 that extend through the electrically insulating material 122 that separates the source metallization 118 from the underlying semiconductor substrate 102.
The semiconductor substrate 102 has an active cell region 136 and an inactive cell region 138. The active cell region 136 of the semiconductor substrate 102 is the region of the semiconductor substrate 102 that includes fully functional transistor cells TC of the power semiconductor device 100. A fully functional transistor cell TC contributes to the main current flow of the power semiconductor device 100. The inactive cell region 138 of the semiconductor substrate 102 adjoins the active cell region 136. The inactive cell region 138 of the semiconductor substrate 102 is devoid of fully functional transistor cells TC and reduces electrical field crowding at termination. For example, the source regions 104 and/or body contacts may be omitted from the inactive cell region 138 of the semiconductor substrate 102.
In one embodiment, a breakdown voltage of the power semiconductor device 100 in the active cell region 136 of the semiconductor substrate 102 is in a range of 20V to 60V and the breakdown voltage of the power semiconductor device 100 in the inactive cell region 138 is greater than the breakdown voltage in the active cell region 136 by at least 2V. The maximum voltage across the gate dielectric insulating material 130 of the trench gate structures 124 is less than half the breakdown voltage in the inactive cell region 138, according to this embodiment.
At least some of the trench gate structures 124 extend into the inactive cell region 138 of the semiconductor substrate 102. In the partial cross-sectional view of
Between adjacent trench gate structures 124 in the active cell region 136 of the semiconductor substrate 102, first contact openings 140 are formed in the electrically insulating material 122 that separates the source metallization 118 from the underlying semiconductor substrate 102. Second contact openings 142 are formed in the electrically insulating material and vertically aligned with the trench gate structures 124 in the inactive cell region 138.
First counter-doped regions 144 between the adjacent trench gate structures 124 in the active cell region 136 are vertically aligned with the first contact openings 140. Second counter-doped regions 146 underneath the trench gate structures 124 in the inactive cell region 138 are vertically aligned with the second contact openings 142. The first counter-doped regions 144 and the second counter-doped regions 146 are ‘counter-doped’ in that these regions 144, 146 have the opposite conductivity as the drift zone 108. First contacts 148 are disposed in the first contact openings and second contacts 150 are disposed in the second contact openings 142. The first contacts 148 and the second contacts 150 may comprise tungsten, for example.
A deep charge balance implant through the first contact openings 140 may be used to form the first counter-doped regions 144 and a shallower but wider charge balance implant through the second contact openings 142 may be used to form the second counter-doped regions 146. The contact dimensions may be varied to differentiate the dose of the counter doped implant in the active cell region 136 and the inactive cell region 138.
The first and second counter-doped regions 144, 148 form a superjunction structure with the adjoining regions 152 of the drift zone 108. The superjunction structure protects the gate dielectric insulating material 130 from the drain potential and drops the drain potential from the backside 112 of the power semiconductor device 100 before reaching the active (front) surface 126 of the semiconductor substrate 102.
The second counter-doped regions 146 may have a different average width (W2≠W1) as compared to the first counter-doped regions 144, depending on the relative widths of the first contact openings 140 and the second contact openings 142. For example, the second contact openings 142 may be wider (W2<W1) than the first contact openings 140 if the first counter-doped regions 144 extend deeper into the semiconductor substrate 102 than the second counter-doped regions 146, to ensure charge balancing in the drift zone 108.
As shown in
Also as shown in
In the inactive cell region 138 of the semiconductor substrate 102, at least some of the trench gate structures 124 may intersect a trench gate bus structure 302 that electrically interconnects the gate electrode material 128 of the trench gate structures 124. The trench gate bus structure 302 may have the same or similar configuration as the trench gate structures 124. Accordingly, the trench gate bus structure 302 may be formed concurrently with the trench gate structures 124 using the same trench etching and gate formation processes.
The same common mask 200 used to form the first contact openings 140 and the second contact openings 142 in the electrically insulating material 122 may be used to form an additional contact opening 304 in the electrically insulating material 122 and that is vertically aligned with the trench gate bus structure 302 in the inactive cell region 138. The common mask 200 is overlaid on the electrically insulating material 122 in the cross-sectional view shown in the righthand part of
The common implantation process 202 shown in
The power semiconductor device 100 may include one or more field termination trenches 310 in the inactive cell region 138 of the semiconductor substrate 102. An electrically conductive material 312 such as polysilicon or a metal or metal alloy disposed in the field termination trenches 310 may be electrically floating, i.e., not directly connected to an electric potential.
The same common mask 200 used to form the first contact openings 140 and the second contact openings 142 in the electrically insulating material 122 may be used to form an additional contact opening 502 in the electrically insulating material 122 and that is vertically aligned with the trench shielding structure 500 in the inactive cell region 138. The common mask 200 is overlaid on the electrically insulating material 122 in the cross-sectional view shown in the righthand part of
The common implantation process 202 shown in
Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.
Example 1. A method of producing a power semiconductor device, the method comprising: forming a plurality of trench gate structures in an active cell region of a semiconductor substrate, the plurality of trench gate structures extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; covering the plurality of trench gate structures with an electrically insulating material; forming, using a common mask, first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region and second contact openings vertically aligned with the trench gate structures in the inactive cell region; and implanting, using a common implantation process, a dopant species into the semiconductor substrate through the first contact openings and the second contact openings to form first counter-doped regions between the adjacent trench gate structures in the active cell region and second counter-doped regions underneath the trench gate structures in the inactive cell region.
Example 2. The method of example 1, further comprising: after the common implantation process, forming first contacts in the first contact openings and second contacts in the second contact openings, wherein the first contacts and the second contacts are at different potentials.
Example 3. The method of example 2, further comprising: forming a patterned power metallization layer above the electrically insulating material such that a first part of the patterned power metallization layer contacts the first contacts and a second part of the patterned power metallization layer partly contacts the second contacts; and forming a passivation on any part of the first contacts and the second contacts not covered by the patterned power metallization layer.
Example 4. The method of any of examples 1 through 3, wherein forming the first contact openings and the second contact openings comprises: etching into the semiconductor substrate between the adjacent trench gate structures in the active cell region and into a gate electrode material of the trench gate structures in the inactive cell region.
Example 5. The method of any of examples 1 through 4, wherein in the inactive cell region, the plurality of trench gate structures intersect a trench gate bus structure that electrically interconnects a gate electrode material of the trench gate structures.
Example 6. The method of example 5, further comprising: forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region; and implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region.
Example 7. The method of any of examples 1 through 6, wherein the first counter-doped regions and the second counter-doped regions merge with one another along a border region between the active cell region and the inactive cell region.
Example 8. The method of any of examples 1 through 7, wherein the dopant species is implanted into the semiconductor substrate through the first contact openings and the second contact openings at an angle relative to a first main surface of the semiconductor substrate.
Example 9. The method of any of examples 1 through 8, further comprising: forming a trench shielding structure in the inactive cell region and that laterally surrounds the plurality of trench gate structures, wherein the trench shielding structure is electrically floating; forming, using the common mask, a third contact opening vertically aligned with the trench shielding structure in the inactive cell region; and implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench shielding structure in the inactive cell region.
Example 10. The method of any of examples 1 through 9, further comprising: forming a trench gate bus structure in the inactive cell region; forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region; implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region; and electrically connecting a metal line in the trench gate bus structure to gate electrodes in the plurality of trench gate structures.
Example 11. The method of any of examples 1 through 10, further comprising: forming a trench structure in the inactive cell region; forming, using the common mask, a third contact opening vertically aligned with the trench structure in the inactive cell region; and implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench structure in the inactive cell region, wherein the counter-doped semiconductor substrate underneath the trench structure in the inactive cell region is electrically floating.
Example 12. A power semiconductor device, comprising: a plurality of trench gate structures in an active cell region of a semiconductor substrate, the plurality of trench gate structures extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the plurality of trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings.
Example 13. The power semiconductor device of example 12, wherein the first contacts and the second contacts are aligned with one another in a lengthwise extension of the first contacts and the second contacts.
Example 14. The power semiconductor device of example 12, wherein the first contacts and the second contacts are offset from one another in a lengthwise extension of the first contacts and the second contacts.
Example 15. The power semiconductor device of any of examples 12 through 14, further comprising: a patterned power metallization layer above the electrically insulating material and comprising a first part that contacts the first contacts and a second part that contacts the second contacts; and a passivation covering any part of the first contacts and the second contacts not covered by the patterned power metallization layer.
Example 16. The power semiconductor device of any of examples 12 through 15, wherein the first contact openings are etched into the semiconductor substrate between the adjacent trench gate structures in the active cell region, and wherein the second contact openings are etched into a gate electrode material of the trench gate structures in the inactive cell region.
Example 17. The power semiconductor device of any of examples 12 through 16, wherein in the inactive cell region, the plurality of trench gate structures intersect a trench gate bus structure that electrically interconnects a gate electrode material of the trench gate structures, and wherein the power semiconductor device further comprises: a third contact opening in the electrically insulating material that is vertically aligned with the trench gate bus structure in the inactive cell region; and a third counter-doped region underneath the trench gate bus structure in the inactive cell region and vertically aligned with the third contact opening.
Example 18. The power semiconductor device of any of examples 12 through 17, wherein the first counter-doped regions and the second counter-doped regions merge with one another along a border region between the active cell region and the inactive cell region.
Example 19. The power semiconductor device of any of examples 12 through 18, further comprising: a trench shielding structure in the inactive cell region and that laterally surrounds the plurality of trench gate structures, wherein the trench shielding structure is electrically floating; a third contact opening in the electrically insulating material that is vertically aligned with the trench shielding structure in the inactive cell region; and a third counter-doped region underneath the trench shielding structure in the inactive cell region and vertically aligned with the third contact opening.
Example 20. The power semiconductor device of any of examples 12 through 19, further comprising: a trench gate bus structure in the inactive cell region; a third contact opening in the electrically insulating material that is vertically aligned with the trench gate bus structure in the inactive cell region; and a third counter-doped region underneath the trench gate bus structure in the inactive cell region and vertically aligned with the third contact opening, wherein a metal line in the trench gate bus structure is electrically connected to gate electrodes in the plurality of trench gate structures.
Example 21. The power semiconductor device of any of examples 12 through 20, wherein a breakdown voltage of the power semiconductor device in the active cell region is in a range of 20V to 60V, wherein the breakdown voltage of the power semiconductor device in the inactive cell region is greater than the breakdown voltage in the active cell region by at least 2V, and wherein a maximum voltage across a gate dielectric insulating material of the plurality of trench gate structures is less than half the breakdown voltage in the inactive cell region.
Example 22. The power semiconductor device of any of examples 12 through 21, further comprising: a trench structure in the inactive cell region; a third contact opening vertically aligned with the trench structure in the inactive cell region; and a third counter-doped region underneath the trench structure in the inactive cell region and vertically aligned with the third contact opening, wherein the third counter-doped semiconductor is electrically floating.
Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
