Patent Application
20190164875
This invention relates to a semiconductor substrate and a method of fabricating the semiconductor substrate. In particular, it relates to a semiconductor substrate that is pre-molded for supporting semiconductor dice during semiconductor packaging.
A semiconductor packaging process typically comprises mounting a semiconductor die onto a substrate, and thereafter encapsulating the semiconductor die in a molding compound, thus forming a semiconductor package. The substrate comprises electrical interconnections that functionally and electrically connect electrical contacts of the mounted semiconductor die to external electrical circuitry, and the molding compound protects the substrate and the semiconductor die mounted on it.
Traditionally, lead frames made of copper alloy or stainless steel are used as substrates to support semiconductor dice and to provide electrical interconnections. However, the strong demand for higher performance devices having smaller and thinner package sizes but higher lead counts has resulted in a rapid increase in the use of laminate substrates such as Ball-Grid Array (“BGA”) packages, molded interconnect substrates (“MIS”) and embedded trace substrates (“ETS”).
ETS uses a via to connect a top metallic layer to a bottom BGA layer. The manufacture of ETS comprises laser drilling the via in a dielectric material, followed by forming a seed metallic layer which is patterned for making electrical interconnections. However, laser drilling is an expensive and slow process, thus making ETS a relatively expensive substrate to manufacture and use.
MIS uses copper studs to connect a top metallic layer to a bottom BGA layer. In addition to forming the copper studs, the manufacture of MIS comprises additional processing steps such as grinding a dielectric layer to reveal the copper studs, and thereafter forming a patterned seed layer to form the bottom BGA layer. However, such MIS manufacturing processes are complicated and expensive, thus making the manufacture of MIS complicated and expensive.
It is thus an object of this invention to seek to provide a method of manufacturing a substrate that is less complicated and/or less expensive than the prior art.
According to a first aspect of the invention, there is provided a method of forming a premolded substrate for mounting a semiconductor die, comprising the steps of: providing a carrier; forming conductive circuits on the carrier; forming a plurality of metallic contacts on the conductive circuits; and thereafter, encapsulating the carrier by compressing a top portion of each metallic contact to crush and flatten the top portion of each metallic contact, and introducing a molding compound to surround the plurality of metallic contacts such that the flattened top surfaces of the plurality of metallic contacts are exposed on and flush with a top surface of the molding compound.
According to a second aspect of the invention, there is provided a premolded substrate for mounting a semiconductor die, the premolded substrate comprising: conductive circuits; a plurality of metallic contacts on the conductive circuits; and a molding compound surrounding the plurality of metallic contacts and exposing a top surface of the metallic contacts; wherein the top surfaces of the plurality of metallic contacts have been crushed and flattened to be flush with a top surface of the molding compound.
These and other features, aspects, and advantages will be better understood with regard to the description section, appended claims, and accompanying drawings.
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
In the drawings, like parts are denoted by like reference numerals.
In the Summary section, in the Description section, in the appended claims, and in the accompanying drawings, it will be appreciated that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intermediate layers may also be present. It should also be noted that certain aspects of the figures have been exaggerated for illustration purposes.
At step 110, a metal substrate or carrier 300 is provided. A plan view of a first surface of the carrier 300 is shown in
At step 120, a metallic layer 310 is formed onto the first surface of the carrier 300, as shown in
At optional step 130, electrical contacts 320, such as package level interconnect contacts, may be formed on the metallic layer 310, as shown in
At step 140, a metallic trace layer 330, such as a routing metal trace layer, is formed on the metallic layer 310 and the electrical contacts 320, as shown in
The metallic trace layer 330 is connected to and entirely, or at least partially surrounds, the electrical contacts 320. The advantage of forming the electrical contacts 320 to be at least partially surrounded by the metallic trace layer 330, such as by embedding it within the metallic trace layer 330, is that different materials may be used for the metallic trace layer 330 and the electrical contacts 320, in order to suit the application or requirements of the final electronic device. For instance, the material chosen for the metallic trace layer 330 may be a material which is able to adhere well to a molding compound to be introduced in a subsequent processing step, and the material chosen for the electrical contacts 320 may be a different material which is able to bond well to a semiconductor die in another subsequent processing step.
The metallic trace layer 330 may be formed by applying a plating resist layer, such as a photoresist layer, onto the metallic layer 310, then masking, exposing, developing, and removing portions of the photoresist layer. Thereafter, a metallic trace layer 330 is plated or deposited over exposed areas of the photoresist layer. Subsequently, the remaining photoresist layer is removed, thus forming the metallic trace layer 330 as shown in
As an optional step 150, metallic contact pads or solder contact pads 340 may be formed on the metallic trace layer 330 at the cylindrical portions corresponding to the positions of the BGA pads, as shown in
At step 160, an adhesion promotion treatment may be carried out on the first surface of the carrier 300, as shown in
At step 170, a respective metallic contact, such as a solder contact or a solder ball 360, is formed on each solder contact pad 340 or each cylindrical portion of the metallic trace layer 330, as shown in
At step 180, the first surface of the carrier 300 is encapsulated by a first molding compound or a first encapsulant 370, as shown in
The carrier 300 may be encapsulated in a molding system comprising a molding cavity 500 for holding the carrier 300, and a top mold plate 510 which is movable relative to a bottom mold plate of a molding machine. The carrier 300 may be held in the molding cavity 500 by being clamped between the top mold plate 510 and the bottom mold plate of the molding machine. While a molding compound is being introduced into the molding cavity 500, a surface of the top mold plate 510 may apply a compressive force onto the top surfaces of the solder balls 360 to deform or crush and flatten the top surfaces of the solder balls 360. Alternatively, a surface of the bottom mold plate may be used to apply the compressive force to crush or deform and flatten the top surfaces of the solder balls 360. The top mold plate 510 also shapes the molding compound in the molding cavity 500 into the desired shape and height. The molding compound embeds the routing metallic trace layer 330 and partially embeds the solder balls 360, flattening the top portions of the solder balls 360 and leaving the said top portions exposed on and flush with a top surface of the molding compound. The exposed portions of the solder balls may be used for broad level interconnections during broad level assembly.
At step 190, the carrier 300 is removed along with the metallic layer 310, as shown in
At optional step 200, an adhesion promotion treatment may be carried out on a second surface of the pre-molded substrate, as shown in
At step 210, the pre-molded substrate is formed, as shown in
At step 220, a semiconductor die 390 is attached, for instance by a flip chip bonding process, to the pre-mold substrate via semiconductor die contacts 400, as shown in
At step 230, the attached semiconductor die 390 is encapsulated by a second encapsulant 410 to form the final electronic device or semiconductor package, as shown in
At step 500, a metallic substrate or carrier 600 is provided. A plan view of a first surface of the carrier 300 is shown in
At step 510, a metallic layer 620 is formed onto the first surface of the carrier 600, as shown in
At step 520, a pattern etch is performed to form conductive circuits or metallic trace patterns 630, as shown in
The metallic trace patterns 630 may be formed by applying an etching resist layer, such as a photoresist layer, onto the metallic layer 620, and masking, exposing, developing, and removing portions of the photoresist layer. Thereafter, areas of the metallic layer 620 located at removed portions of the photoresist layer may be removed. Such areas of the metallic layer 620 which are at removed portions of the photoresist layer may be removed by a dry etching method, a wet etching method such as chemical removal, or a combination of dry and wet etching methods. In addition, there are many other well-known etching processes and etchants in the art, and it is not intended that the present invention be limited to any particular etching process.
At step 530, a respective metallic contact, such as solder contact or solder ball 640, is formed on certain areas of each metallic trace pattern 630 or each cylindrical portion of the metallic trace patterns 630, as shown in
At step 540, the carrier 600 is encapsulated by an encapsulant 650, as shown in
At step 550, the carrier 600 and the adhesive 610 are removed to form the pre-molded substrate, as shown in
The pre-molded substrate shown in
A skilled person would appreciate that the pre-molded substrate of the first and second preferred embodiments of the present invention is a one-layer structure which utilizes simple and cost effective processing steps to manufacture. In addition, there is no need to grind any dielectric layer or to use solder resist, both of which may introduce impurities and complications into the manufacturing process. There is also no need to plate copper studs, which would be a clear advantage over conventional manufacturing processes for MIS and ETS.
Furthermore, the skilled person would appreciate that the first preferred embodiment would potentially be able to achieve a finer line width and spacing than the second preferred embodiment.
It should be recognized that the specifics of the various processes recited above are provided for illustrative purposes only, and that other processes and materials which provide equivalent results may be substituted therefor. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
