Patent Application
20160198568
This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2015-0002109, filed on Jan. 7, 2015, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
1. Field
The present disclosure relates to a printed circuit board and an electronic component module.
2. Description of Related Art
Recently, functional capacities provided by smartphones and tablet personal computers, as well as battery consumption and expected battery life have drastically increased. However, battery technology still presents limitations regarding the amount of energy that may be stored. Thus, battery volume has increased in order to increase capacity. In turn, the demand for producing thinner and smaller components for electronic devices has increased.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In one general aspect, a printed circuit board includes a first insulating layer including a first circuit pattern, a second insulating layer including a second circuit pattern, and a dummy pattern disposed in the first insulating layer and the second insulating layer, and the first and second insulating layers are made of different materials.
The second insulating layer may be embedded in the first insulating layer such that an upper surface of the second insulating layer is exposed from the first insulating layer.
The dummy pattern may be disposed at an interface between the first insulating layer and the second insulating layer, the dummy pattern being electrically isolated from the first circuit pattern and the second circuit pattern.
The second insulating layer may be embedded in the first insulating layer such that an upper surface of the second insulating layer is exposed from the first insulating layer, and the dummy pattern may be embedded in the first and second insulating layers such that an upper surface of the dummy pattern is exposed from the first and second insulating layers.
Upper surfaces of the first insulating layer, the second insulating layer, and the dummy pattern may be coplanar.
The second insulating layer may be a photosensitive insulating layer.
The second circuit pattern may include a pattern including a pitch finer than a pitch of the first circuit pattern.
The second circuit pattern may include a plurality of pads and a connection pattern for mounting of components, and the plurality of pads may be electrically connected to each other by the connection pattern.
The second circuit pattern may further include connection vias connecting the plurality of pads and the connection pattern to each other.
The plurality of pads may be embedded in the second insulating layer such that upper ends of the plurality of pads are exposed.
The first circuit pattern may include a plurality of pads embedded in the first insulating layer such that upper ends of the plurality of pads are exposed.
In another general aspect, an electronic component module includes a printed circuit board including a first insulating layer including a first circuit pattern, a second insulating layer embedded in the first insulating layer such that an upper end of the second insulating layer is exposed, the second insulating layer including a micro-circuit structure including a connection pattern for a connection of a pair of components, and a dummy pattern disposed in the first insulating layer and the second insulating layer, the first and second insulating layers being made of different materials; and an electronic component mounted on the printed circuit board, and the electronic component includes a pair of components connected to each other by the connection pattern.
The micro-circuit structure may include a pattern having a pitch finer than a pitch of the first circuit pattern.
The dummy pattern may be embedded in the first and second insulating layers such that an upper surface of the dummy pattern is exposed from the first insulating layer and the second insulating layer.
The micro-circuit structure may further include a pair of pads and a pair of connection vias respectively connecting both ends of the connection pattern and a pair of components to each other.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent to one of ordinary skill in the art. The sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent to one of ordinary skill in the art, with the exception of operations necessarily occurring in a certain order. Also, descriptions of functions and constructions that are well known to one of ordinary skill in the art may be omitted for increased clarity and conciseness.
The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete, and will convey the full scope of the disclosure to one of ordinary skill in the art.
In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.
Printed Circuit Board
Referring to
The first and second insulating layers 150 and 141 may be formed of heterogeneous materials.
In this example, the first insulating layer 150 includes a plurality of insulating layers 151 and 161. The first insulating layer 150 may be formed of any insulating resin generally used as an insulating material in printed circuit boards.
According to the present embodiment, a material of the first insulating layer 150 may be a resin used for a general coreless board, such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, but is not limited thereto. For example, the first insulating layer 150 may be formed of a resin such as Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), or the like.
The first circuit pattern 160 may be formed inside and outside the first insulating layer 150.
As illustrated in
The first circuit pattern 160 may also include a plurality of circuit layers 155 and 165.
Interlayer circuit layers of the first circuit pattern 160 may be electrically connected to each other by a general connection via.
The second insulating layer 141 may be formed of a material different from that of the first insulating layer 150.
The second insulating layer 141 may be a photosensitive dielectric layer in order to facilitate formation of a micro-circuit structure. For example, a photosensitive dielectric layer that does not contain a glass sheet may be used as the second insulating layer 141.
In this example, the second insulating layer 141 is embedded in the first insulating layer 150 so that an upper surface thereof is exposed from the first insulating layer 150.
The second circuit pattern, which is the micro-circuit structure, may be formed inside and outside the second insulating layer 141.
The second circuit pattern may include a pattern having a pitch finer than that of the first circuit pattern 160.
In this example, the second circuit pattern includes a connection pattern 145 that may serve as a signal line that connects a plurality of electronic components to each other.
The second circuit pattern also includes a plurality of pads 125a and 125b for mounting the plurality of electronic components. The plurality of pads 125a and 125b are connected to the connection pattern 145 through a plurality of connection vias 143a and 143b.
The connection vias 143a and 143b, which are fine vias, may have a diameter of, for example, 5 μm to 35 μm.
The plurality of pads 125a and 125b are embedded in the second insulating layer 141 so that upper ends thereof are exposed from the second insulating layer 141.
According to the present embodiment, the micro-circuit structure including a micro-circuit and vias having a small diameter as well as the embedded pattern may be implemented in the outermost layer, thereby enabling connection between the electronic components in the printed circuit board.
Referring the example illustrated in
In this example, upper surfaces of the first insulating layer 150, the second insulating layer 141, and the dummy pattern 130 are coplanar.
The dummy pattern 130 may be formed together with the circuit pattern when the circuit pattern is formed, and may be formed of the same material as that of a general circuit pattern. For example, the dummy pattern 130 may be formed of a metal or a conductive material such as copper (Cu).
In a case of an existing coreless board in which a board technology and a semiconductor technology are combined, adhesion between two different insulating materials is weaker in comparison to the adhesion obtained between insulating materials made of the same material are joined together. In addition, when the two insulating materials are used, a void or the like may occur in the bonded position between the two different insulating materials, or an abrupt step may form on the surface along the interface of the two different insulating materials. This kind of irregularity may contribute to the formation of a weak point that is detected during a reliability test such as a highly accelerated stress test (HAST), high temperature storage (HTS), or the like. Further, the interface area may cause other reliability or yield problem due to moisture absorption and the like.
According to the illustrated example, the dummy pattern is inserted into the bonded portion that is externally exposed at the interface between the two different insulating materials. Thereby, the dummy pattern may prevent the weak bonded portion from being exposed to an outside of the printed circuit board, and eliminate the abrupt step that may form at the bonded portion between the two different insulating materials. In addition, optionally, the surface of the dummy pattern may be provided with roughness to increase adhesion between the dummy pattern and the insulating layers.
Additionally, a general liquid-phase or film-type solder resist layer 171 may be formed as a protective layer exposing the plurality of pads 115, 125a, and 125b, on the outermost insulating circuit layer.
The solder resist layer may be formed in order to protect circuit patterns of the outermost layer and electrically insulate the circuit patterns from each other, and have opening parts formed therein in order to expose pads of the outermost layer connected to an external product.
In addition, a surface treatment layer may be selectively and additionally formed on the pads exposed through the opening parts of the solder resist layer.
The surface treatment layer may be formed by any method known in the art, such as electro gold plating, immersion gold plating, organic solderability preservative (OSP) or immersion tin plating, immersion silver plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like.
The pads formed as described above may be used as pads for wire bonding or pads for bumps, or may be used as pads for solder balling for mounting external connection terminals such as solder balls, depending on a purpose thereof.
Electronic Component Module
Referring to
Electronic components 210a and 210b may include various electronic devices such as a passive device and an active device, and may include any electronic devices that may be generally mounted on or embedded in the printed circuit board.
In this example, the printed circuit board 100 includes a first insulating layer 150 having a first circuit pattern 160, a second insulating layer 141 having a micro-circuit structure including a connection pattern 145 for connecting a pair of electronic components 210a and 210b to each other, and a dummy pattern 130 formed in the first insulating layer 150 and the second insulating layer 141.
The second insulating layer 141 is embedded in the first insulating layer 150 so that an upper surface thereof is exposed from the first insulating layer 150. The upper surfaces of the first insulating layer 150 and the second insulating layer 141 are coplanar.
The first and second insulating layers 150 and 141 may be formed of two different materials.
In this example, the micro-circuit structure includes the connection pattern 145 serving as a signal line connecting the pair of electronic components 210a and 210b to each other. In addition, the micro-circuit structure includes a pair of pads 125a and 125b for mounting the pair of electronic components. The pair of pads 125a and 125b are connected to the connection pattern 145 through a pair of connection vias 143a and 143b. However, the arrangement of the second circuit pattern is not limited to the illustrated example.
The connection vias 143a and 143b, which are fine vias, may have a diameter of, for example, 5 μm to 35 μm.
The pair of pads 125a and 125b may be embedded in the second insulating layer 141 so that upper ends thereof are exposed.
According to the present embodiment, the micro-circuit structure including a micro-circuit and vias having a small diameter as well as the embedded pattern may be implemented in the outermost layer, thereby enabling connection between the electronic components in the printed circuit board.
Referring to
Method of Manufacturing Printed Circuit Board
Referring to
Hereinafter, respective processes will be described with reference to cross-sectional views illustrated in
First, referring to
The carrier member 10 includes a carrier core 11 and first and second metal layers 12 and 13 sequentially formed on one surface of the carrier core 11. However, in another example, the first and second metal layers 12 and 13 may be sequentially formed on both surfaces of the carrier core 11.
The carrier core 11, which supports an insulating layer, a circuit layer, and the like, when the insulating layer, the circuit layer, and the like, are formed, may be formed of an insulating material or a metal.
The first metal layer 12 may be formed of copper. However, a material of the first metal layer 12 is not limited thereto.
The second metal layer 13 may serve as a seed layer and be formed of copper.
However, the above-mentioned carrier member 10 may be only an example, and is not limited in the embodiment as long as it is used as a support board in a circuit board field and may be later detached or removed.
Next, referring to
In detail, after a liquid-phase plating resist is applied onto the carrier member, general exposure and development may be performed on the carrier member onto which the liquid-phase plating resist is applied, thereby forming the predetermined opening parts including opening parts 21 for forming a circuit pattern and opening parts 22 for forming a dummy pattern.
In a case in which the plating resist is applied in a liquid-phase form, uniformity of a thickness may be high, and thus it may be easy to later form a micro-circuit structure.
Next, referring to
The plating may be electroless plating, electroplating, or a combination thereof, and may be copper plating.
Additionally, roughness may be formed on the dummy pattern 130 to make a surface of the dummy pattern rough, thereby later improving bonding characteristics between the dummy pattern 130 and the insulating layer.
Next, referring to
Referring to a plan view illustrated at a lower portion of
Next, referring to
As the second insulating layer 141, a photosensitive insulating layer having surface roughness lower than that of a general resin insulating layer may be used in order to facilitate formation of the micro-circuit structure.
The micro via-holes 142 is formed with a diameter of, for example, about 5 μm to 35 μm through laser beam machining.
Referring to a plan view illustrated at a lower portion of
Next, referring to
The plating may be electroless plating, electroplating, or a combination thereof, and may be copper plating.
Through the process as described above, the pair of pads 125a and 125b for mounting the electronic components and the connection pattern 145 may be electrically connected to each other through the connection vias 143a and 143b.
The connection pattern 145 may serve as a signal line connecting the plurality of electronic components to each other.
Additionally, plasma processing may later be performed on the micro-circuit structure, in order to increase close adhesion between the micro-circuit structure and the insulating layer.
Next, referring to
The insulating layer 151 and the second insulating layer 141 may be formed of two different materials.
The insulating layer 151 may be formed of any insulating resin generally used as an insulating material in a printed circuit board.
According to the present embodiment, a material of the insulating layer 151 may be a resin used for a general coreless board, such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, but is not limited thereto. For example, the insulating layer 151 may be formed of a resin such as ABF, FR-4, BT, or the like.
Next, referring to
The circuit layer 155 may be formed by laser beam machining and a semi-additive process (SAP) depending on a general method of forming a circuit pattern.
Next, referring to
The build-up insulating layer 161 and the second insulating layer 141 may be formed of two different materials.
The build-up insulating layer 161 may be formed of any insulating resin generally used as an insulating material in a printed circuit board.
According to the present embodiment, a material of the build-up insulating layer 161 may be a resin used for a general coreless board, such as a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, but is not limited thereto. For example, the insulating layer 151 may be formed of a resin such as ABF, FR-4, BT, or the like.
Next, referring to
The carrier member may be removed by detaching the carrier core 11 and the first metal layer 12 and then removing the second metal layer 13.
A method of removing the carrier member is not limited. For instance, the carrier member may be removed by various methods depending on a configuration of an actually used carrier member.
Next, referring to
The solder resist layer may be formed in order to protect circuit patterns of the outermost layer and electrically insulate the circuit patterns from each other, and have opening parts formed therein in order to expose pads of the outermost layer connected to an external product.
In addition, a surface treatment layer may be selectively and additionally formed on the pads exposed through the opening parts of the solder resist layer.
The surface treatment layer may be formed by any method known in the art, such as electro gold plating, immersion gold plating, organic solderability preservative (OSP) or immersion tin plating, immersion silver plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like.
Next, referring to
The electronic components 210a and 210b may include various electronic devices such as a passive device and an active device, and may include any electronic devices that may be generally mounted on or embedded in the printed circuit board.
As illustrated in
According to the present embodiment, a circuit pattern including pads of a surface on which the electronic components are mounted may be implemented as an embedded pattern, and the micro-circuit structure may be introduced into the outermost insulating layer, thereby enabling connection between the electronic components in the printed circuit board through the fine pattern.
Further, the dummy pattern may be inserted into the externally exposed bonded portion between two different insulating materials in order to form the micro-circuit structure, thereby preventing as much as possible the weak portion of the printed circuit board from being exposed and alleviating the formation of an abrupt step along the interface between the two insulating materials.
Therefore, electrical characteristics including impedance may be improved.
Provided above is an example of a printed circuit board in which bonding characteristics between heterogeneous insulating materials may be improved, and a method of manufacturing the same.
In the example of the printed circuit board, an abrupt step that may form at an interface between two different insulating materials may be alleviated, thereby improving the reliability of a connection structure between electronic components.
While this disclosure includes specific examples, it will be apparent to one of ordinary skill in the art that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2015-0002109 | Jan 2015 | KR | national |
