Patent Application
20240040691
This application claims benefit of priority to Korean Patent Application No. 10-2022-0093704 filed on Jul. 28, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to a printed circuit board (PCB) and a method for manufacturing the PCB.
According to the high performance and/or super-integration of electronic or electric devices in which PCBs may be used, the size of the components of PCBs has also gradually decreased. As the PCB itself or components of PCBs is highly integrated and/or miniaturized, the difficulty in securing the reliability of PCBs may increase.
In addition, as the performance of semiconductor chips (e.g., processors, memories) has gradually increased, the degree of integration of semiconductor chips has also gradually increased and a spacing between input/output (I/O) terminals of semiconductor chips and the size of each of the I/O terminals has also gradually decreased. As a result, the degree of integration and the difficulty of forming an electrical connection path that PCBs may provide has also gradually increased.
Recently, PCBs have been increasingly widely used in devices requiring a large electrical connection path, such as installed electronic devices (including servers) or electric devices (including vehicles). PCBs used in these devices may have a large horizontal area or a large number of conductive layers, and the difficulty of securing the reliability of an electrical connection path that PCBs may provide has also gradually increased.
An aspect of the present disclosure may provide a printed circuit board (PCB) and a method for manufacturing the same.
According to an aspect of the present disclosure, a printed circuit board (PCB) may include an insulating layer; a first solder resist layer disposed on an upper surface of the insulating layer; a first conductive pattern disposed on the insulating layer and providing a conductive post protruding from an upper surface of the first solder resist layer; and a second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than the upper surface of the insulating layer.
According to another aspect of the present disclosure, a printed circuit board (PCB) may include an insulating layer; a first solder resist layer disposed on an upper surface of the insulating layer; a first conductive pattern buried in the insulating layer; and a conductive post disposed on an upper surface of the first conductive pattern and protruding from an upper surface of the first solder resist layer, wherein an edge of the upper surface of the first conductive pattern is positioned to be lower than the upper surface of the insulating layer.
According to another aspect of the present disclosure, a method for manufacturing a printed circuit board (PCB) may include: forming first and second conductive patterns on a first conductive layer on a base insulating layer; forming an insulating layer on the first and second conductive patterns; separating the base insulating layer from at least a portion of the first conductive layer; etching a partial region of at least a portion of the first conductive layer to form a conductive post; forming a first solder resist layer on a surface of the insulating layer on which the conductive post is formed; and etching a portion of the first solder resist layer to reduce a thickness of the first solder resist layer.
According to another aspect of the present disclosure, a printed circuit board (PCB) may include an insulating layer; a first conductive pattern buried in the insulating layer; and a second conductive pattern buried in the insulating layer and having an upper surface positioned to be lower than an upper surface of the insulating layer; a first solder resist layer disposed on the insulating layer to cover the second conductive pattern; and a conductive post extending from the first conductive pattern to protrude from an upper surface of the first solder resist layer.
The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.
Referring to
For example, a combined structure of the base insulating layer 111 and the first conductive layers 131 and 132 of unfinished PCBs 100a and 100b may be a copper clad laminate (CCL), and thus, at least a portion 132 of the first conductive layers 131 and 132 may include copper (Cu). For example, in the first conductive layers 131 and 132, the portion 131 in contact with the base insulating layer 111 may be replaced with an adhesive layer, and thus, the combined structure of the base insulating layer 111 and the first conductive layers 131 and 132 may be manufactured according to a detachable copper foil (DCF) method.
For example, the first and second conductive patterns 125 and 127 may be a portion of a plating layer formed according to a copper (Cu) plating process, and may be formed by exposure and development in a state in which a protective pattern is formed on the plating layer.
Referring to
For example, the insulating layer 112 of unfinished PCBs 100c, 100d, and 100e may be a copper clad laminate (CCL), ABF, prepreg, FR-4, bismaleimide triazine (BT), a photoimageable dielectric (PID) resin, and may be at least one selected from the group consisting of a thermosetting resin, such as an epoxy resin, a thermoplastic resin, such as polyimide, and polytetrafluoroethylene (PTFE), glass-based, and ceramic-based (e.g., low temperature co-fired (LTCC) resin. In one example, the first conductive pattern 125 and the second conductive pattern 127 may be buried in the insulating layer 112 at substantially a same depth. The meaning of the term “substantially” may include a process error occurring in the manufacturing process, a measurement error, or the like, recognizable by one of ordinary skill in the art. For example, the configuration in which elements have substantially the same depth may include the example in which the elements have exactly the same depth, and also the example in which a minute difference in depth may exist due to a process error occurring in the manufacturing process, a measurement error, or the like, recognizable by one of ordinary skill in the art.
For example, a portion of the insulating layer 112 may be drilled by a laser or drilling, and a conductive via 123 may fill a drilled space of the insulating layer 112. A third conductive pattern 121 may be formed on one surface of the insulating layer 112, and may be formed by exposure and development in a state in which a protective pattern 116 is formed in a manner similar to that in which the first and second conductive patterns 125 and 127 are formed. Thereafter, the protective pattern 116 may be etched.
For example, a material that may be included in the first and second conductive patterns 125 and 127 and the conductive via 123 may be at least one of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt). For example, the third conductive pattern 121 may be implemented using a semi-additive process (SAP), a modified semi-additive process (MSAP), or a subtractive method.
Referring to
For example, upper and lower structures of the base insulating layer 111 in unfinished PCBs 100f and 100g may be used to manufacture a plurality of PCBs. Since the base insulating layer 111 may be a core, each of the plurality of PCBs may have a coreless structure.
Referring to
For example, the method for manufacturing a PCB according to an exemplary embodiment in the present disclosure may further include forming an etch stop pattern 133 in a region of the first conductive layer 132 overlapping the first conductive pattern between the separating of the base insulating layer and the forming of the conductive post 134 and removing the etch stop pattern 133 between the forming of the conductive post 134 and the forming of a first solder resist layer. For example, the etch stop pattern 133 may include at least one of nickel (Ni) and tin (Sn).
For example, in an unfinished PCB 100h, the protective pattern 117 may be formed in a region in which the etch stop pattern 133 is not formed on one surface of the first conductive layer 132, so that the protective pattern 117 may have a temporary opening 135. An unfinished PCB 100i may include the etch stop pattern 133 disposed in the temporary opening 135.
A portion of the protective pattern 117 and the first conductive layer 132 that does not vertically overlap the etch stop pattern 133 may be etched. Accordingly, an unfinished PCB 100j may include a conductive post 134 vertically overlapping the etch stop pattern 133. The forming of the conductive post 134 may include forming the conductive posts 134 on an upper surface of the first conductive pattern 125. In one example, a side surface of the conductive post 134 may have a substantially constant slope with respect to the upper surface of the insulating layer 112. The configuration in which the side surface of the conductive post 134 may have a substantially constant slope with respect to the upper surface of the insulating layer 112 may include the example in which the side surface of the conductive post 134 may have a constant slope with respect to the upper surface of the insulating layer 112, and also the example in which a minute deviation in slope may exist due to a process error occurring in the manufacturing process, a measurement error, or the like, recognizable by one of ordinary skill in the art.
Since the conductive post 134 may be formed from the first conductive layer 132, uniformity of a thickness T1 of the conductive post 134 may be affected by uniformity of a thickness of the first conductive layer 132. Since the first conductive layer 132 may have wide, simple, and smooth upper and lower surfaces, the uniformity of the thickness of the first conductive layer 132 may increase. Accordingly, the uniformity of the thickness T1 of the conductive post 134 may increase. As the uniformity of the thickness T1 increases, when the number of the conductive posts 134 is plural, a thickness difference between the thickest conductive post and the thinnest conductive post, among the plurality of conductive posts 134, may be reduced.
In other words, in the process of forming the conductive post 134, a difference between the design and the reality (process dispersion) may be small, so that the possibility of an occurrence of an electrical short between the conductive post 134 and the adjacent conductive structure (e.g., the second conductive pattern 127) may be reduced.
Since a partial region of the first conductive layer 132 may vertically overlap the second conductive pattern 127, a portion of the second conductive pattern 127 may also be etched according to an etching process method or time adjustment. Accordingly, the upper surface of the second conductive pattern 127 may be positioned to be lower than an upper surface of the insulating layer 112, and a recessed portion 137 may be provided.
Accordingly, the possibility that a metal material corresponding to the first conductive layer 132 remains between the conductive post 134 and the second conductive pattern 127 in a partial region of the first conductive layer 132 may be reduced, and thus, the possibility of an unintentional connection between the conductive post 134 and the second conductive pattern 127 or the possibility of an electrical short may be reduced.
An unfinished PCB 100k may have a structure in which the etch stop pattern is removed. For example, the thickness T1 of the conductive post 134 may be thicker than the thickness T2 of the recessed portion 137.
Referring to
For example, the forming of the first solder resist layer 141pre may include forming the first solder resist layer 141pre to contact the second conductive pattern 127 and further forming a second solder resist layer 142 below the insulating layer 112.
For example, a PCB 1001 may include the first solder resist layer 141pre having a thickness T3 greater than the thickness T1 of the conductive post 134. Between the forming of the first solder resist layer 141pre and the etching of a portion of the first solder resist layer 141pre, an upper surface of the first solder resist layer 141pre may be positioned to be higher than an upper surface of the conductive post 134.
Since the first solder resist layer 141pre may be formed to be relatively thick, adhesion between the first solder resist layer 141pre and the second conductive pattern 127 may increase. Accordingly, the possibility that an electrical short occurs between the second conductive pattern 127 and the conductive post 134 may be reduced.
Accordingly, a distance between the conductive post 134 and the second conductive pattern 127 may be advantageously further reduced and the size of each of the conductive post 134 and the second conductive pattern 127 may be advantageously further reduced, and therefore, the PCB manufactured according to the method for manufacturing a PCB according to an exemplary embodiment in the present disclosure may efficiently increase the degree of integration and/or reliability of an electrical connection path that may be provided and suppress an increase in the incidence of defects due to the increased degree of integration (e.g., an electrical short).
Referring to
For example, the etching of a portion of the first solder resist layer 141 may include etching a portion of the first solder resist layer 141 so that a difference between the thicknesses of the first solder resist layer 141 and the second solder resist layer 142 further increases.
For example, a PCB 100m may include the first solder resist layer 141 having a thickness T4 less than the thickness T1 of the conductive posts 134. After the etching of the portion of the first solder resist layer 141, an upper surface of the first solder resist layer 141 may be positioned to be lower than an upper surface of the conductive post 134.
Referring to
For example, a plurality of input/output (I/O) terminals 225 of the semiconductor chip 200 may be disposed to correspond to the plurality of conductive posts 134, respectively, and may be connected to and fixed to the conductive posts 134 through solder 175.
Referring to
The first solder resist layer 141 may be disposed on an upper surface of the insulating layer 112. For example, the first solder resist layer 141 may include a material different from that of the insulating layer 112. The group of materials that may be included in the first solder resist layer 141 or the second solder resist layer 142 may be selected from the group of materials of the insulating layer 112 that may be used as a known solder resist, but is not limited thereto. For example, the thickness T4 of the first solder resist layer 141 may be thinner than the thickness of the second solder resist layer 142.
The first conductive pattern 125 may be disposed on the insulating layer 112 and may provide a conductive post 134 protruding from the upper surface of the first solder resist layer 141. Accordingly, the semiconductor chip 200 may be efficiently mounted on the conductive post 134, and the PCBs 100m and 100n may efficiently increase the degree of integration and/or reliability of the electrical connection path that the PCBs 100m and 100n may provide.
Depending on the design, a surface treatment structure, such as an electroless nickel electroless palladium immersion gold (ENEPIG) structure or an organic solder passivation (OSP) structure may be formed on the upper surface of the conductive post 134, but is not limited thereto.
The second conductive pattern 127 may be embedded in the insulating layer 112 and may have an upper surface positioned to be lower than the upper surface of the insulating layer 112. Accordingly, a possibility that the metal material remains between the conductive post 134 and the second conductive pattern 127 may be reduced, so that a possibility of unintentional connection between the conductive post 134 and the second conductive pattern 127 or a possibility of an electrical short may be reduced.
Therefore, in the PCBs 100m and 100n according to an exemplary embodiment in the present disclosure, a distance between the conductive post 134 and the second conductive pattern 127 may be further advantageously reduced and the size of each of the conductive post 134 and the second conductive pattern 127 may be further advantageously reduced, and the degree of integration and/or reliability of an electrical connection path that may be provided may be effectively increased.
For example, the insulating layer 112 may include the recessed portion 137, and a portion of the first solder resist layer 141 and the second conductive pattern 127 may contact each other in the recessed portion 137. Accordingly, since a portion of the first solder resist layer 141 may further stabilize the upper surface of the second conductive pattern 127, the possibility of an electrical short between the second conductive pattern 127 and the conductive post 134 may be further reduced.
Referring to
Referring to
Referring to
For example, a protective pattern 117-2 may be formed on an upper surface of the first conductive layer 132, and the protective pattern 117-2 may replace the etch stop pattern. In other words, the protective pattern 117-2 may have a structure in which a material of the etch stop pattern is replaced with a photosensitive insulating material from metal.
Referring to
Referring to
The edge of the upper surface of the first conductive pattern 125 may be positioned to be lower than the upper surface of the insulating layer 112. The conductive post 134-6 may be formed based on a portion of the first conductive layer 132 and a thickness difference or shape difference between the plurality of first conductive patterns 125 may be reduced, so that the occurrence of an electrical short between the conductive post 134-6 and the adjacent conductive structure may be suppressed.
For example, when the first conductive layer 132 of
Accordingly, a width W3 of the lower surface of the conductive post 134-6 may be less than the width (W1 in
For example, a portion of a side surface of the conductive post 134-6 may contact the first solder resist layer 141. Accordingly, a portion of the first solder resist layer 141 may be disposed in close contact with the edge of the upper surface of the first conductive pattern 125, and structural stability of the conductive posts 134-6 may be improved.
For example, the first conductive pattern 125 may be connected to an upper surface of the conductive via 123, and the third conductive pattern 121 may be connected to a lower surface of the conductive via 123. A width of the surface (e.g., the upper surface) of the conductive via 123 connected to the first conductive pattern 125 is less than a width of the surface (e.g., the lower surface) of the conductive via 123 connected to the third conductive pattern 121. For example, a width difference in the conductive via 123 may be formed in the process of drilling a portion of the insulating layer 112 (a portion in which the conductive via is formed). Since the first conductive pattern 125 may receive an electrical connection path through the conductive via 123 and the third conductive pattern 121, the second conductive pattern 127 may be omitted according to design.
Referring to
When the number of the first conductive patterns 125 is plural, the width W1 may be measured as an average of widths W1-1 and W1-2 of the plurality of first conductive patterns 125. When the number of the second conductive patterns 127 is plural, the width W2 may be measured as an average of the widths W2-1 and W2-2 of each of the plurality of second conductive patterns 127. When at least one of the first and second conductive patterns 125 and 127 is plural, the distance D3 may be measured as an average of the plurality of intervals D3-1, D3-2, and D3-3.
For example, the first conductive pattern 125 may be a pad or a land, and the second conductive pattern 127 may be a wiring. The width W2 of the second conductive pattern 127 may be an average of width measurement values in a direction perpendicular to the extension direction at each point of the wiring in the extension direction. The width W1 of the first conductive pattern 125 may be measured in a straight line passing through the center of the first conductive pattern 125, and may be measured in a direction perpendicular to a direction of a long side measured in the straight line. The distance D3 may also be measured in the same direction as that of the widths W1 and W2, and may be measured as an averaged value.
Referring to
The chip-related component 1020 includes a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), and a flash memory; application processor chips, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; logic chips, such as analog-to-digital converters (ADCs) and application-specific integrated chips (ASICs), but is not limited thereto, and may include other types of chip-related electronic components. Also, of course, these chip-related components 1020 may be combined with each other. The chip-related component 1020 may be in the form of a package including the chips or electronic components described above.
The network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated thereafter, and but the present disclosure is not limited thereto and may include any other wireless or wired protocols and certain protocols. Also, the network-related component 1030 may be combined with the chip-related component 1020.
The other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, low temperature co-firing ceramics (LTCC), an electro-magnetic interference (EMI) filter, a multilayer ceramic condenser (MLCC), and the like. However, the present disclosure is not limited thereto and may include a passive element in the form of a chip component used for various other purposes in addition thereto. In addition, the other component 1040 may be combined with the chip-related component 1020 and/or the network-related component 1030.
Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, the present disclosure is not limited thereto, and the other electronic component may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. In addition to this, other electronic components used for various purposes may be included depending on the type of the electronic device 1000.
The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game player, a smart watch, an automotive, and the like. However, the present disclosure is not limited thereto and may be any other electronic device that processes data in addition thereto.
The electronic device may be, for example, a smartphone 1100. A motherboard 1110 is accommodated inside the smartphone 1100, and various components 1120 are physically and/or electrically connected to the motherboard 1110. Also, other components that may or may not be physically and/or electrically connected to the motherboard 1110, such as a camera module 1130 and/or a speaker 1140, may be accommodated therein. A portion of the component 1120 may be the chip-related component described above, for example, a component package 1121, but is not limited thereto. The component package 1121 may be in the form of a PCB on which electronic components including active components and/or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a PCB in which active and/or passive components are embedded. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, and of course, may be other electronic devices as described above.
The PCB and the method for manufacturing a PCB according to an exemplary embodiment in the present disclosure may efficiently increase the degree of integration and/or reliability of an electrical connection path that may be provided, and suppress an increase in the incidence of defects (e.g., an electrical short) due to the increased degree of integration.
While exemplary embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0093704 | Jul 2022 | KR | national |
