Printed circuit board with mixed metallurgy pads and method of fabrication

Abstract

A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to the field of printed circuit boards; more specifically, it relates to electronic devices connection pads and mechanical connectors for printed circuit boards and the method of fabricating the pads and connectors.

BACKGROUND OF THE INVENTION

[0002] Printed circuit boards (PCB's) serve the purpose of an intermediate level of packaging for attachment and electrical inter-connection of discrete devices such as resistors and capacitors and active devices such as logic and memory modules. Printed circuit board may also have edge connectors for physical attachment and electrical connection of the printed circuit board to a higher level of packaging. Devices are attached to printed circuit boards by a variety of methods. One attachment method is soldering to pads of discrete passive surface mount technology (SMT) components or active device ball grid array (BGA) or land grid array (LGA) modules. Another attachment method is pin in hole (PIH) soldering. PIH soldering requires printed circuit having plated through holes (PTH's). The pads and edge connectors are interconnected by wiring traces formed on the top surface of the printed circuit board. Often wiring traces are formed on the bottom surface of the board and within the board itself. Similarly, devices may be mounted on both the top and bottom surfaces of the printed circuit board.

[0003] Pads for SMT, BGA, LGA, and PIH/LGA solder connections require surface finish layers that provide good solderability and corrosion resistance. Edge connectors require surface finish layers for good electrical and mechanical contact, wear resistance, and corrosion resistance. Wiring traces must be protected from solder operations, often by a solder mask. The solder mask must have good adhesion to the wiring trace, requiring a application of a surface finish or surface treatment of the wiring trace.

[0004] Generally it is not possible for one surface finish to satisfy all the requirements thus placed on the printed circuit board so multiple surface finishes and/or surface treatments are required. Often multiple finishes require multiple masking steps. When multiple surface finishes or treatments are applied to a printed circuit board compatibility of the processes employed to produce those finishes is critical. For example, the chemicals used to remove masks should not corrode or contaminate any prior formed surface finishes. Similarly, the processes used to form a given surface finish should not corrode or contaminate other surface finishes or printed circuit board features.

SUMMARY OF THE INVENTION

[0005] A first aspect of the present invention is a method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate. The method includes: forming an oxide layer on the set of second copper conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a lead-tin layer on at least a portion of the third set of conductors.

[0006] A second aspect of the present invention is a method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate. The method includes: forming an oxide layer on the first, second and third sets of second conductors; forming a solder mask over the oxide layer on the second set of conductors; removing the oxide layer from the first and third sets of conductors; forming a first masking layer over the second and third sets of conductors; forming a composite layer on the first set of conductors; removing the first masking layer; forming a second masking layer over the first and second sets of copper conductors; and forming a solder layer on at least a portion of the third set of conductors.

[0007] A third aspect of the present invention is a printed circuit device including an electrically insulating substrate; first, second, and third sets of conductors formed on a top surface of the substrate; an oxide layer on the set of second conductors; a solder mask on the oxide layer; a composite layer on the first set of conductors; and a solder layer on at least a portion of the third set of conductors.

[0008] A fourth aspect of the present invention is a method of improving the adhesion of a protective layer over a conductive circuit feature during fabrication of a printed circuit device comprising: providing a substrate with conductive circuit features thereon; forming an oxide layer over at least a portion of the conductive circuit features, the oxide layer providing enhanced adhesion for a protective layer; applying the protective layer over the oxide layer over at least a portion of the conductive features; selectively removing portions of the protective layer to expose select regions of the oxide layer over the at least a portion of the conductive circuit features; removing the oxide layer in the exposed regions; and electroless plating a first conductive layer in the select regions of exposed the oxide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

[0010] FIGS. 1-6 show a sequence of partial cross section views illustrating initial process steps for fabricating a PCB according to the present invention;

[0011] FIG. 7 shows a partial cross section view illustrating a tri-layer metallurgy for the composite layer formed in FIG. 6 according to the present invention;

[0012] FIG. 8 shows a partial cross section view illustrating a bi-layer metallurgy for the composite layer formed in FIG. 6 according to the present invention;

[0013] FIGS. 9-12 show a sequence of partial cross section views illustrating further process steps for fabricating the PCB according to the present invention; and

[0014] FIG. 13 is a partial top view of the PCB fabricated according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Referring to the drawings, FIGS. 1-6 show a sequence of partial cross section views illustrating initial process steps for fabricating a PCB according to the present invention. The process sequence starts with the structure illustrated in FIG. 1. In FIG. 1! PCB 100 includes a substrate 110 having a top surface 115, a bottom surface 120 and a substrate edge 125. In one example, substrate 110 is an insulating organic laminate board. In a second example, substrate 110 is a multi-layer organic laminate board having one or more internal wiring levels between layers of laminate. In a third example, substrate 110 is a ceramic substrate. In a fourth example, substrate 110 is a multilayer ceramic substrate having one or more internal wiring levels between layers of ceramic material. In a fifth example, substrate 110 is a flexible insulating polymer. Formed from copper on top surface 115 of substrate 110 is a PIH LGA pad 130, a LGA Pad 135, an SMT pad 140, a top wiring trace 145, and an edge connector 150. Also formed in PCB 100 are PTH's 155A, 155B and 155C. PTH 155A is formed within PIH LGA pad 130. LGA pad 135 includes a pad portion 160 connected to PTH 155B by connecting portion 165. Edge connector 150 includes a terminal end 170 located near substrate edge 125, connected to PTH 155C by a connecting portion 175. Optionally, formed from copper on bottom surface 120 of substrate 115 are bottom wiring traces 180 and 185. It is also possible to form LGA pads, SMT pads, and edge connectors on bottom surface 120 of substrate 115.

[0016] In FIG. 2, PCB 100 is treated with an aqueous oxidizing solution to form a copper oxide layer 190 on all exposed copper surfaces including PIH LGA pad 130, LGA Pad 135, SMT pad 140, top wiring trace 145, edge connector 150 and bottom wiring traces 180 and 185. In one example, the oxidizing solution comprises about 10.0 to 14.1 grams of sodium hypochlorite and about 3.5 to 4.3 grams of sodium hydroxide in 100 milliliters of water. Copper oxide layer 190 has a weight per unit area of about 20 to 100 milligram/cm2. In one example, copper oxide layer 190 is cuprous oxide. The purpose of copper oxide layer will be discussed below.

[0017] In FIG. 3, solder mask 195 is applied on copper oxide layer 190 on top wiring trace 145 and bottom wiring traces 180 and 185. In one example, solder mask 195 is applied by a top and bottom screen coating, followed by lithographic expose and develop processes. In one example, solder mask 195 is PSR4000 manufactured by Taiyo America Inc., Carson City NV and is about 200 to 1200 microinches in thickness.

[0018] In FIG. 4, copper oxide layer 190 not protected by solder mask 195 is removed. That is, copper oxide layer 190 is removed from PIH LGA pad 130, LGA Pad 135, SMT pad 140, and edge connector 150. In one example, copper oxide layer 190 is removed using a first solution of sulfamic acid and a second solution of sodium persulfate and sulfuric acid. The first solution comprises about 5 to 15 grams of sulfamic acid in 1000 milliliters of water. The second solution comprises about 35 to 45 grams of sodium persulfate and about 4 to 6 grams of sulfuric acid in 1000 milliliters of water.

[0019] In FIG. 5, upper first resist layer 200 is formed over top wiring trace 145 and edge connector 150. Upper first resist layer is also formed on top surface 115 of substrate 110 between PIH LGA pad 130, LGA PAD 135 and SMT pad 140. Lower first resist layer 205 is formed over bottom wiring traces 180 and 185. Lower first resist layer 205 is also formed between PTH's 155A and 155B and over PTH 155C as well as exposed regions 210 of lower surface 120 of substrate 110. In one example, upper first resist layer 200 and lower first resist layer 205 are formed by a vacuum application coating followed by a lithographic expose, develop and UV harden processes. In one example, upper first resist layer 200 and lower first resist layer 205 are Morton 5000 series manufactured by Morton Thiokol, Tustin, Calif. and are about 1000 to 4000 microinches in thickness.

[0020] In FIG. 6, a composite layer 215 is formed on PIH LGA pad 130, LGA Pad 135, and SMT pad 140 by multiple sequential plating processes using upper first resist layer 200 and lower first resist layer 205 as a selective plating mask. Composite layer 215 is formed on all exposed copper surfaces including sidewalls 220A and 220B of PTH's 155A and 155B respectively. The formation of composite layer 215 is illustrated in FIGS. 7 and 8 and described below.

[0021] FIG. 7 shows a partial cross section view illustrating a tri-layer metallurgy for the composite layer formed in FIG. 6 according to the present invention. Composite layer 215 is illustrated formed on SMT pad 140, but it is understood that the composite layer is also formed on PIH LGA pad 130 and LGA pad 135 as well. In FIG. 7, composite layer 215 includes a nickel layer 225 on SMT pad 140, a palladium layer 230 on top of the nickel layer, and a gold layer 235 on top of the palladium layer. Nickel layer 225 is about 50 to 300 microinches in thickness. Nickel layer 225 is formed by electroless plating. Electrolytic plating may be used whenever electroless plating is indicated. Nickel layer 225 acts as a copper diffusion barrier. Palladium layer 230 is about 4 to 30 microinches in thickness. Palladium layer 230 is formed by electroless plating. Palladium layer 230 acts as a wear resistance layer as well as forming a corrosion resistant surface. Gold layer 235 is about 1 to 10 microinches in thickness. Gold layer 235 is formed by electrolytic or electroless plating. Gold layer 235 enhances solderability and seals palladium layer 230 to prevent the palladium from attracting hydrocarbons that could form a contaminant film. In one example palladium layer 230 is 99.9% pure, fine grained, equiaxed and possesses a hardness of about HK25 200-250 (Knoop hardness scale), while gold layer 235 is soft gold. Soft gold is 99.9% pure gold with limitations on the type and quantity of impurities that are present in the remaining 0.1% of the material.

[0022] Copper oxide layer 190 prevents blister formation between certain conductive circuit features and solder mask 195, as for example, between lower wiring traces 180 and 185 and solder mask 195 as illustrated in FIG. 6 and described above. Copper oxide layer 190 also acts as an adhesion promoter between solder mask 195 and lower wiring traces 180 and 185. For example, solder mask adhesion is of concern in electroless nickel plating baths due to the relativity high temperature reached by the bath and the volume of hydrogen gas evolved during the plating operation. Lifting of the solder mask 195 may cause shorting problems during further card assembly processes. Another concern is blistering (formation of gas bubbles between the solder mask and a conductive circuit feature) of the solder mask away from the conductive circuit features if the conductive circuit features are not treated with a protective layer. Copper oxide layer 190 addresses both these concerns. In contrast to pattern plating precesses, the current invention provides for a conductive circuit feature, in this case, a copper surface treatment before surface finish operations such as lead-tin solder application or palladium plating are performed. To attempt to perform a copper surface treatment after the tin-lead solder has been applied, would be problematic because of the tendency of the copper surface treatment to attack the tin-lead during processes.

[0023] FIG. 8 is shows a partial cross section view illustrating a bi-layer metallurgy for the composite layer formed in FIG. 6 according to the present invention. In FIG. 8, composite layer 215 includes a nickel layer 225 on SMT pad 140 and a gold layer 235 on top of the nickel layer. Nickel layer 225 is about 50 to 300 microinches in thickness. Nickel layer 225 is formed by electroless plating. Nickel layer 225 acts as a copper diffusion barrier. Gold layer 235 is about 20 to 40 microinches in thickness. Gold layer 235 is formed by electrolytic or electroless plating. Gold layer 235 enhances solderability and acts as a wear resistant layer. In one example, gold layer 235 is hard gold. Hard gold is at least 99.9% pure gold alloyed with up to 1000 parts per million of 99.0% cobalt and/or nickel to give the alloy a hardness of about HK25 130-260 (Knoop hardness scale).

[0024] Returning to FIG. 7, alternatively, composite layer 215 includes a nickel layer 225 a hard gold layer 230 on top of the nickel layer, and a soft gold layer 235 on top of the hard gold layer. Nickel layer 225 is about 50 to 300 microinches in thickness. Nickel layer 225 is formed by electrolytic plating. Nickel layer 225 acts as a copper diffusion barrier. Hard gold layer 230 is about 20 to 40 microinches in thickness. Hard gold layer 230 is formed by electroless plating. Hard layer 230 acts as a wear resistant layer. Soft gold layer 235 is about 5 to 30 microinches in thickness. Soft gold layer 235 is formed by electrolytic or electroless plating. The combined thickness of hard gold layer 230 and soft gold layer 235 should not exceed 55 microinches.

[0025] Returning to the process flow, FIGS. 9-12 show a sequence of partial cross section views illustrating further process steps for fabricating the PCB according to the present invention. In FIG. 9 upper first resist layer 200 and lower first resist layer 205 have been removed using benzyl alcohol. Benzyl alcohol is used because it eliminates the possibility of galvanic corrosion between copper and non-copper metallic features (for example, formation of corrosion pits) or Silvering (undercut of precious metal ans/or subsequent flaking causing shorts). Sodium or potassium hydroxide provide the strong electrolytes to promote the galvanic cell reactions. Halogonated organic resist strippers/removers are undesirable because of environmental concerns.

[0026] In FIG. 10, upper second resist layer 240 is formed over the entire top surface 115 of substrate 110 and all structures on the top surface of the substrate except for terminal end 170 of edge connector 150 which is left exposed. Lower second resist layer 245 is formed over the entire bottom surface 120 of substrate 110 and all structures on the bottom surface of the substrate. In one example, upper second resist layer 240 and lower first resist layer 245 are formed by a vacuum coating followed by a lithographic expose, develop bake processes. In one example, upper second resist layer 240 and lower second resist layer 245 are Morton 5000 series manufactured by Morton Thiokol, Tustin, Calif. and are about 1000 to 4000 microinches in thickness.

[0027] In FIG. 11, lead-tin layer 255A has been formed on terminal end 170 of edge connector 150 by electrolytic plating, using upper second resist layer 240 and lower first resist layer 245 as plating masks. Lead-tin layer 255A is about 100 to 1000 microinches in thickness. Lead-tin layer 255A is comprised of about 50 to 70 percent tin. The balance of lead-tin layer 255A is lead. Alternatively, a layer of tin about 3 to 15 microinches in may be formed by electrolytic plating on terminal end 170 first, followed by plating of lead-tin layer 255A second.

[0028] In FIG. 12, upper second resist layer 240 and lower second resist layer 245 have been removed using benzyl alcohol as described above. Lead-tin layer 255A has been reflowed to produce reflowed lead-tin layer 255B.

[0029] FIG. 13 is a partial top view of the PCB fabricated according to the present invention. In FIG. 13, PIH LGA pad 130, LGA Pad 135, SMT pad 140, top wiring trace 145 and edge connector 150 are illustrated. PTH 155A is formed within PIH LGA pad 130. LGA pad 135 includes a pad portion 160 connected to PTH 155B by connecting portion 165. Top wiring trace 145 is coated with solder mask 195. Edge connector 150 includes a terminal end 170 connected to PTH 155C by a connecting portion 175. Terminal end 170 is covered with reflowed lead-tin layer 255B.

[0030] While the discussion has used various materials as examples of how to practice the invention it is understood that other materials can be utilized. For example the circuitized features on the substrate can be copper and its alloys, aluminum and its alloys as well as other metallic conductors. The described oxide layer can be of various oxides of non-noble metals. For example the oxide layer my be oxides of copper, oxides of copper alloys, oxides of aluminum, oxides of aluminum alloys, or oxides of other non-noble metals. The metal component(s) of the oxide layer material can be different from that of the base circuit feature material. Oxides of aluminum could be used over copper for example. While lead-tin solder was used in the description of the invention, it is also understood that any alloy solder can be used. Examples of such solders include eutectic lead-tin solders, high melt lead-tin solders and lead free solders. Various solder mask materials can be used to form the resist layer such as permanent resist, aqueous developed polymeric layers, and non-aqueous developed polymeric layers.

[0031] The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. For example, BGA devices may be substituted for LGA devices. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims

1. A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of said substrate, comprising: forming an oxide layer on said set of second conductors; forming a mask on said oxide layer; forming a composite layer on said first set of conductors; and forming a solder layer on at least a portion of said third set of conductors.

2. The method according to claim 1, wherein said conductors are selected from the group consisting of copper, aluminum, copper alloy, and aluminum alloy.

3. The method according to claim 1, wherein said solder i s selected from the group consisting of eutectic tin lead, high melt tin lead alloys, and lead free alloys.

4. The method according to claim 1, wherein said oxide layer is selected from the group consisting of copper, aluminum, copper alloys, aluminum alloys, and non-noble metals.

5. The method according to claim 1, wherein said composite layer comprises a layer of nickel, a layer of palladium overlaying said layer of nickel and a gold layer overlaying said layer of palladium.

6. The method according to claim 1, wherein said composite layer comprises a layer of nickel and a layer of gold overlaying said layer of nickel.

7. The method according to claim 1, wherein said composite layer comprises a layer of nickel, a first layer of gold overlaying said layer of nickel and a second layer of gold overlaying said first layer of gold.

8. The method according to claim 5, wherein said layer of nickel has a thickness of 50 to 300 microinches, said layer of palladium has a thickness of 4 to 30 microinches and said layer of gold has a thickness of 1 to 10 microinches.

9. The method according to claim 6, wherein said layer of nickel has a thickness of 50 to 300 microinches and said layer of gold has a thickness of 20 to 40 microinches.

10. The method according to claim 7, wherein said layer of nickel has a thickness of 50 to 300 microinches, said first layer of gold has a thickness of 20 to 40 microinches and said second layer of gold has a thickness of 5 to 30 microinches.

11. The method according to claim 5, wherein said layers of nickel and palladium are formed by electroless plating and said layer of gold is soft gold formed by electrolytic or electroless plating.

12. The method according to claim 6, wherein said layer of nickel formed by electroless plating and said layer of gold is hard gold formed by electrolytic plating.

13. The method according to claim 7, wherein said layer of nickel is formed by electroless plating, said first layer of gold is hard gold formed by electrolytic plating and said second layer of gold is soft gold formed by electrolytic or electroless plating.

14. The method according to claim 1, further including forming a layer of tin under said solder layer.

15. The method according to claim 1, wherein said first set of conductors includes PIH/LGA pads, LGA pads and SMT pads, said second set of conductors are wiring traces and said third set of conductors are edge connectors.

16. A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of said substrate, comprising in the order recited: forming an oxide layer on said first, second and third sets of second conductors; forming a solder mask over said oxide layer on said second set of conductors; removing said oxide layer from said first and third sets of conductors; forming a first masking layer over said second and third sets of conductors; forming a composite layer on said first set of conductors; removing said first masking layer; forming a second masking layer over said first and second sets of conductors; and forming a solder layer on at least a portion of said third set of conductors.

17. The method according to claim 16, further including removing said second masking layer.

18. The method according to claim 16, wherein said conductors are selected from the group consisting of copper, aluminum, copper alloy, and aluminum alloy.

19. The method according to claim 16, wherein said solder is selected from the group consisting of eutectic tin lead, high melt tin lead alloys, and lead free alloys.

20. The method according to claim 16, wherein said oxide layer is selected from the group consisting of copper, aluminum, copper alloys, aluminum alloys, and non-noble metals.

21. The method according to claim 16, wherein said composite layer comprises a layer of nickel, a layer of palladium overlaying said layer of nickel and a gold layer overlaying said layer of palladium.

22. The method according to claim 16, wherein said composite layer comprises a layer of nickel and a layer of gold overlaying said layer of nickel.

23. The method according to claim 16, wherein said composite layer comprises a layer of nickel, a first layer of gold overlaying said layer of nickel and a second layer of gold overlaying said first layer of gold.

24. The method according to claim 21, wherein said layer of nickel has a thickness of 50 to 300 microinches, said layer of palladium has a thickness of 4 to 30 microinches and said layer of gold has a thickness of 1 to 10 microinches.

25. The method according to claim 22, wherein said layer of nickel has a thickness of 50 to 300 microinches and said layer of gold has a thickness of 20 to 40 microinches.

26. The method according to claim 23, wherein said layer of nickel has a thickness of 50 to 300 microinches, said first layer of gold has a thickness of 20 to 40 microinches and said second layer of gold has a thickness of 5 to 30 microinches.

27. The method according to claim 21, wherein said layers of nickel and palladium are formed by electroless plating and said layer of gold is soft gold formed by electrolytic or electroless plating.

28. The method according to claim 22, wherein said layer of nickel formed by electroless plating and said layer of gold is hard gold formed by electrolytic plating.

29. The method according to claim 23, wherein said layer of nickel is formed by electroless plating, said first layer of gold is hard gold formed by electrolytic plating and said second layer of gold is soft gold formed by electrolytic plating.

30. The method according to claim 22, further including forming a layer of tin under said solder layer.

31. The method according to claim 22, wherein said first set of conductors includes PIH/LGA pads, LGA pads and SMT pads, said second set of conductors are wiring traces and said third set of conductors are edge connectors.

32. The method according to claim 20, wherein said oxide layer is formed using an aqueous solution comprising sodium hypochlorite and sodium hydroxide.

33 The method according to claim 27, wherein said oxide layer is removed using a first aqueous solutions comprising sulfamic acid and a second aqueous solution comprising sodium persulfate and sulfuric acid.

34. The method according to claim 20, wherein said first and second masking layers are removed using benzyl alcohol.

35. A printed circuit device comprising: an insulating substrate; first, second, and third sets of conductors formed on a top surface of said substrate; an oxide layer on said set of second conductors; a solder mask on said oxide layer; a composite layer on said first set of conductors; and a solder layer on at least a portion of said third set of conductors.

36. The printed circuit device according to claim 35, wherein said conductors are selected from the group consisting of copper, aluminum, copper alloy, and aluminum alloy.

37. The printed circuit device according to claim 35, wherein said solder is selected from the group consisting of eutectic tin lead, high melt tin lead alloys, and lead free alloys.

38. The printed circuit device according to claim 35, wherein said oxide layer is selected from the group consisting of copper, aluminum, copper alloys, aluminum alloys, and non-noble metals.

39. The printed circuit device according to claim 35, wherein said composite layer comprises a layer of nickel, a layer of palladium overlaying said layer of nickel and a gold layer overlaying said layer of palladium.

40. The printed circuit device according to claim 35, wherein said composite layer comprises a layer of nickel and a layer of gold overlaying said layer of nickel.

41. The printed circuit device according to claim 35, wherein said composite layer comprises a layer of nickel, a first layer of gold overlaying said layer of nickel and a second layer of gold overlaying said first layer of gold.

42. The printed circuit device according to claim 39, wherein said layer of nickel has a thickness of 50 to 300 microinches, said layer of palladium has a thickness of 4 to 30 microinches and said layer of gold has a thickness of 1 to 10 microinches.

43. The printed circuit device according to claim 40, wherein said layer of nickel has a thickness of 50 to 300 microinches and said layer of gold has a thickness of 20 to 40 microinches.

44. The printed circuit device according to claim 41, wherein said layer of nickel has a thickness of 50 to 300 microinches, said first layer of gold has a thickness of 20 to 40 microinches and said second layer of gold has a thickness of 5 to 30 microinches.

45. The printed circuit device according to claim 39, wherein said layers of nickel and palladium are formed by electroless plating and said layer of gold is soft gold formed by electrolytic or electroless plating.

46. The printed circuit device according to claim 40, wherein said layer of nickel formed by electroless plating and said layer of gold is hard gold formed by electrolytic plating.

47. The printed circuit device according to claim 41, wherein said layer of nickel is formed by electroless plating, said first layer of gold is hard gold formed by electrolytic plating and said second layer of gold is soft gold formed by electrolytic or electroless plating.

48. The printed circuit device according to claim 35, further including forming a layer of tin under said solder layer.

49. The printed circuit device according to claim 35, wherein said first set of conductors includes PIH/LGA pads, LGA pads and SMT pads, said second set of conductors are wiring traces and said third set of conductors are edge connectors.

50. A method of improving the adhesion of a protective layer over a conductive circuit feature during fabrication of a printed circuit device comprising: providing a substrate with conductive circuit features thereon; forming an oxide layer over at least a portion of said conductive circuit features, said oxide layer providing enhanced adhesion for a protective layer; applying said protective layer over said oxide layer over at least a portion of said conductive features; selectively removing portions of said protective layer to expose select regions of said oxide layer over said at least a portion of said conductive circuit features; removing said oxide layer in said exposed regions; and electroless plating a first conductive layer in said select regions of exposed said oxide layer.

51. The method according to claim 50 wherein said protective layer is selected from the group consisting of solder mask, permanent resist, aqueous developed polymeric layers, and non-aqueous developed polymeric layers.

52. The method according to claim 50 wherein said oxide layer is selected from the group consisting of copper oxide, copper alloy oxide, aluminum oxide, and oxides of non-noble metals.

53. The method according to claim 50 wherein said conductive circuit features are selected from the group consisting of copper, aluminum, copper alloys and aluminum alloys.

54. The method of claim 50 wherein said enhanced adhesion provides additional adhesion of said protective layer to said oxide layer to reduce bubble formation between said protective layer and said conductive features during said electroless plating of said at least a portion of said first conductive layer in said select regions of exposed said oxide layer.