Patent Application
20060261441
This invention relates to the field of semiconductor manufacture and, more particularly, to a method for annealing a metal film which decreases the film's resistance and also may decrease the carbon content of the metal.
Many different types of materials are used in the manufacture of semiconductor memory devices, logic devices, microprocessors, etc. Pure metals are becoming more commonly used in semiconductor manufacture for a wider range of purposes due to the prohibitively high resistance found with nonmetals and metal-containing compounds such as polysilicon, metal silicides, and metal nitrides, particularly with decreasing feature sizes. For example, attempts have been made to manufacture capacitor plates, typically formed from polysilicon, from ruthenium metal. Ruthenium may also be used as a barrier layer to copper migration and as a seed layer for copper plating.
While the formation of a conformal metal layer with good step coverage may be more difficult than the formation of other nonmetals previously used, their use is necessary to produce a reliable semiconductor device. One method for forming a capacitor plate from ruthenium metal is described by U.S. Pat. No. 6,617,248 by Yang, assigned to Micron Technology, Inc., and incorporated herein as if set forth in its entirety. Yang discusses the formation of a container capacitor bottom plate by first forming a layer of ruthenium oxide (RuO2), then reducing the RuO2 to Ru metal by exposing the RuO2 to a hydrogen-rich gas, for example either ammonia (NH3) or hydrogen gas (H2).
As discussed in Yang, RuO2 is not stable at high temperatures and forms an oxidizer. Reducing RuO2 into Ru metal and O2 using NH3 or N2 also results in the formation of ruthenium tetraoxide (RuO4) which strongly oxidizes exposed layers such as titanium nitride or layers comprising silicon and forms a dielectric film over the conductive layer. This dielectric film may lead to unwanted opens and a poorly functional or nonfunctional semiconductor device. Yang forms a barrier to prevent oxidation of the polysilicon pads. Many barriers, however, may not sufficiently protect silicon pads from RuO4, particularly at high temperatures.
Reducing a metal oxide to metal also results in a substantial volumetric decrease of the resulting metal compared with the metal oxide due to the removal of oxygen atoms from the material. Reducing a metal oxide to metal may stress structures formed under the metal oxide, and may damage the structures. Stress may have other undesirable consequences such as causing layers to form at uneven rates and also a change in conductive properties. It is therefore often desirable to avoid stresses resulting from reducing a metal oxide to metal.
In addition to forming metal layers themselves, improving the conductivity and purity of metal layers is a goal of semiconductor process engineers. Increased material conductivity allows the size of a feature, such as the width or cross-sectional area of a metal line, to be decreased while maintaining a resistance within acceptable limits. Forming a metal layer having a higher purity, in addition to improving conductivity, reduces the layer as a source of contamination and improves reliability and longevity of a device.
A method for forming a metal layer with increased conductivity and fewer contaminants would be desirable.
The present invention provides a method for annealing a metal layer which results in the formation of a highly conductive metal layer having reduced contamination and reduced oxidation of exposed layers. In accordance with one embodiment of the invention a pure metal layer, particularly a metal which does not form a metal nitride, is formed in accordance with previous methods such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Metals which do not form metal nitrides include ruthenium, cobalt, platinum, and nickel. The pure metal layer is then annealed in the presence of ammonia (NH3), borane (BH3), diborane (B2H6), hydrogen gas (H2), or carbon monoxide (CO). Annealing the completed metal layer as described densifies the metal, possibly by removing contaminants such as carbon, and improves the conductivity of the completed metal layer. Further, undesirable oxidizing byproducts such as a metal tetraoxide are not produced as these gasses are reducing and not oxidizing.
Advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.
The term “wafer” is to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. Additionally, when reference is made to a “substrate assembly” in the following description, the substrate assembly may include a wafer with layers including dielectrics and conductors, and features such as transistors, formed thereover, depending on the particular stage of processing. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-sapphire, germanium, or gallium arsenide, among others. Further, in the discussion and claims herein, the term “on” used with respect to two layers, one “on” the other, means at least some contact between the layers, while “over” means the layers are in close proximity, but possibly with one or more additional intervening layers such that contact is possible but not required. Neither “on” nor “over” implies any directionality as used herein.
The present invention comprises the formation of a metal layer, particularly a metal which does not form a metal nitride, and its subsequent anneal in an atmosphere having a high concentration of hydrogen. Particularly preferred metals include ruthenium, cobalt, platinum, and nickel. While the description below describes the formation of a ruthenium metal layer deposited using chemical vapor deposition (CVD), it is to be understood that any preferred metal may benefit from the present invention regardless of its method of formation (for example through the use of atomic layer deposition) using the inventive process with similar results.
The present invention comprises forming a semiconductor wafer substrate assembly, then forming a metal layer over the assembly. As used herein, a “metal layer” refers to a layer which is a pure metal layer rather than a metal-containing compound such as a metal oxide, metal nitride, metal silicide, etc. A metal layer which is “substantially free from oxygen” includes a metal layer which may have a low percentage of oxygen atoms, for example resulting from reaction with environmental oxygen, but excludes metal oxides. Further, a “metal layer” as used herein may include a native oxide which forms on the metal by exposure to environmental oxygen, unless it is specified that the “metal layer” is free or substantially free from the native oxide. During the anneal of the metal layer this native oxide will not provide sufficient oxygen to form large amounts of an oxidizer such as metal tetraoxide, for example ruthenium tetraoxide (RuO4), although trace amounts may be present. Thus during this anneal exposed silicon or polysilicon surfaces will not oxidize to such an extend as to interfere with processing, for example resulting in electrical opens, as a result of oxygen which released due to disproportionation of a metal and an oxide. [//this is included to define around Yang if necessary]
One method used to form a ruthenium metal layer begins by placing the wafer assembly into a deposition chamber, or it may remain in a chamber from previous processing. In the chamber, a ruthenium precursor such as tricarbonyl-1,3-cyclohexadiene ruthenium (referred to herein as “CHDR”) is introduced into the chamber at a flow rate of between about 10 sccm to about 2,000 sccm, more preferably at a flow rate of between about 100 sccm and about 1,000 sccm, and most preferably at a flow rate of about 500 sccm. Helium may be used as a carrier gas for the CHDR. The chamber further comprises an environment having a pressure preferably between about 0.1 Torr to about 90 Torr, and more preferably at a pressure of between about 1.0 Torr and about 10.0 Torr. A wafer temperature of between about 100° C. and about 600° C., more preferably between about 150° C. and about 450° C., and most preferably about 210° C. would be sufficient. At the preferred parameters, the ruthenium metal will form at a rate of between about 30 Å/minute and about 120 Å/minute.
After forming the metal layer, it is annealed, preferably in situ. After forming the metal layer the deposition chamber is purged, for example through the introduction of nitrogen (N2) into the chamber. Next, the chamber is heated to an anneal temperature of between about 500° C. and about 900° C., more preferably to between about 625° C. and about 775° C., and most preferably to about 700° C. At temperature, a hydrogen-rich gas is introduced into the chamber. For purposes of this disclosure, the term “hydrogen-rich gas” refers to non-carbon containing hydrides and reducing gasses with the exception of silanes. These gasses comprise hydrogen (H2), ammonia (NH3), diborane (B2H6), and borane (BH3). For example, if B2H6, NH3, and/or BH3 is used, the gas is introduced into the chamber at a flow rate of between about 100 sccm and about 10,000 sccm, and more preferably at a flow rate of between about 1,000 sccm and about 3,000 sccm. If H2 is used, it will be introduced into the chamber at a flow rate of between about 100 sccm and about 5,000 sccm. With any of these gasses, pressure within the chamber during the anneal is maintained to between about 100 millitorr and about 900 torr, and more preferably to between about 1,000 millitorr and about 700 torr. The anneal is preferably performed for between about 10 seconds and about 6,000 seconds, and more preferably for about 90 seconds. After annealing the metal layer, wafer processing continues according to techniques known in the art to produce a completed semiconductor device.
Another gas which may be used to anneal a metal to result in decreased resistance but does not fit into the present definition of “hydrogen-rich gas” includes carbon monoxide (CO). While testing has not been performed using this gas, it is believed by the inventors herein that CO will function sufficiently for purposes of the present invention. The anneal and gas delivery conditions using CO would be within the range described above for the other gasses.
Annealing the completed metal layer in the presence of BH3, NH3, B2H6, H2, or CO decreases the resistance of the completed metal. For example, a ruthenium metal feature which has an as-deposited resistivity of about 110 μΩcm was calculated to have a post NH3 anneal resistivity of about 12 μΩcm or less. By comparison, the same film annealed only in nitrogen (N2) had a resistivity of about 55 μΩcm. The decrease in resistivity may be due to a reduction in contaminants such as carbon within the metal.
During the anneal the metal feature will decrease in volume, although the reduction has not been quantified. As discussed above, this reduction in volume may result from the decrease of the carbon contaminants within the metal. Unlike processes which reduce a metal oxide to a metal layer and result in substantial stresses on other layers from a large volumetric decrease of the metal compared to the metal oxide, annealing the pure metal layer to reduce the resistance provides a substantially stress-free metal layer.
The present invention may be used to form any number of different structures such as a container capacitor bottom plate and/or top plate and a solder wetting layer for wafer level processing. A first embodiment of an inventive method to form both top and bottom capacitor plates (electrodes) for a container capacitor such as a memory cell is depicted in
Also depicted is a second layer of dielectric 24 which may be one or more layers of TEOS and/or BPSG. With current technology, layer 24 may be about 14,000 Å thick. A layer of photoresist 26 defines openings 28 which overlie pads 18 to which the container capacitors will be electrically coupled. The structure of
After forming the openings 30, a blanket layer of metal 32 such as ruthenium metal is formed over exposed surfaces including pads 18. A ruthenium metal layer between about 40 Å thick and about 300 Å thick would be sufficient for this exemplary embodiment. Such as layer may be formed using one of the methods described above. However, the method of reducing RuO2 to Ru metal is not preferred in this particular exemplary embodiment of the invention, as the conversion of RuO2 to Ru metal will result in the oxidation of pads 18 and an undesirable electrical open between pads 18 and Ru layer 32.
Next, the metal layer 32 is annealed according to an embodiment of the present invention to result in the annealed layer 34 as depicted in
Subsequently, the openings 30 are filled with a sacrificial protective material 40 such as photoresist as depicted in
Subsequently, a metal capacitor top plate is formed, for example from ruthenium metal using one of the processes described above, resulting in the metal layer 62 of
Capacitor plates formed in accordance with the present embodiment will have reduced resistance compared with similar sized plates formed from the same material, thereby increasing the capacitance. Further, contamination is decreased, possibly through a reduction in the carbon content of the layer.
In use as a barrier layer, if layer 100 is formed directly on dielectric layer 96, metal layer 100 will provide a mobile ion source for layer 96. Mobile ions may migrate along dielectric 96 and change the conductivity of a conductive layer such as polysilicon (not depicted) which contacts the dielectric layer 96. The inventive layer 98 used as a barrier layer is more stable than the copper layer 100 and will reduce or eliminate mobile ion contamination of dielectric layer 96. In use as a seed layer, layer 98 facilitates deposition of copper layer (or copper based layer) 100.
While the processes herein describe the use of a thermal anneal, it is contemplated that a plasma anneal may also function sufficiently with the prescribed gasses. The wafer temperature during the plasma anneal may be lower than that described for the thermal anneal, possibly as low as room temperature but up to the maximum described for the thermal anneal. Plasma power may be in the range of 25 watts to 1,200 watts, and possibly higher depending on the maximum power allowable by the individual production tool. Various conditions for a plasma anneal may be determined by one of ordinary skill in the art.
As depicted in
The process and structure described herein can be used to manufacture a number of different structures comprising a metal layer formed according to the inventive process to result in a densified metal layer having decreased resistance and reduced contamination compared with conventional layers.
While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
