The present application relates to systems, devices and methods for memory access operations involving phase change memory units.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Phase change memory (“PCM”) is a relatively new nonvolatile memory technology, which is very different from any other kind of nonvolatile memory. First, the fundamental principles of operation, at the smallest scale, are different: no other kind of solid-state memory uses a reversible PHYSICAL change to store data. Second, in order to achieve that permanent physical change, an array of PCM cells has to allow read, set, and reset operations which are all very different from each other. The electrical requirements of the read, set, and reset operations make the peripheral circuit operations of a PCM very different from those of other nonvolatile memories. Obviously some functions, such address decoding and bus interface, can be the same; but the closest-in parts of the periphery, which perform set, reset, and read operations on an array or subarray, must satisfy some unique requirements.
The physical state of a PCM cell's memory material is detected as resistance. For each selected cell, its bitline is set to a known voltage, and the cell's access transistor is turned on (by the appropriate wordline). If the cell is in its low-resistance state, it will sink a significant current from the bit line; if it is not, it will not.
Set and Reset operations are more complicated. Both involve heat. As discussed below, a “set” operation induces the memory material to recrystallize into its low-resistance (polycrystalline) state; a “reset” operation anneals the memory material into its high-resistance (amorphous) state.
Write operations (Set and Reset) normally have more time budget than read operations. In read mode a commercial PCM memory should be competitive with the access speed (and latency if possible) of a standard DRAM. If this degree of read speed can be achieved, PCM becomes very attractive for many applications.
The phase change material is typically a chalcogenide glass, using amorphous and crystalline (or polycrystalline) phase states to represent bit states.
A complete PCM cell can include, for example: a top electrode (connected to the bit line), a phase change material (e.g. a chalcogenide glass), a conductive pillar which reaches down from the bottom of the phase change material, an access transistor (gated by a word line), and a bottom connection to ground. The phase change material can extend over multiple cells (or over the whole array), but the access transistors are laterally isolated from each other by a dielectric.
A conductive pillar 2050 connects the material 2030 to a bottom electrode 2040. In this example, no selection device is shown; in practice, an access transistor would normally be connected in series with the phase change material. The pillar 2050 is embedded in an insulator layer 2060.
When voltage is applied between the top 2020 and bottom 2040 electrodes, the voltage drop will appear across the high-resistivity zone 2070 (if present). If sufficient voltage is applied, breakdown will occur across the high-resistivity zone. In this state the material will become very conductive, with large populations of mobile carriers. The material will therefore pass current, and current crowding can occur near the top of the pillar 2050. The voltage which initiates this conduction is referred to as the “snapback” voltage, and
In the zone 2200 marked “READ,” the device will act either as a resistor or as an open (perhaps with some leakage). A small applied voltage will result in a state-dependent difference in current, which can be detected.
However, the curve with open circles, corresponding to the amorphous state of the device, shows some more complex behaviors. The two curves show behaviors under conditions of higher voltage and higher current.
If the voltage reaches the threshold voltage Vth, current increases dramatically without any increase in voltage. (This occurs when breakdown occurs, so the phase-change material suddenly has a large population of mobile carriers.) Further increases in applied voltage above Vth result in further increases in current; note that this upper branch of the curve with hollow circles shows a lower resistance than the curve with solid squares.
If the applied voltage is stepped up to reach the zone 2150, the behavior of the cell is now independent of its previous state.
When relatively large currents are applied, localized heating will occur at the top of the pillar 2050, due to the relatively high current density. Current densities with typical dimensions can be in the range of tens of millions of Amperes per square cm. This is enough to produce significant localized heating within the phase-change material.
This localized heating is used to change the state of the phase-change material, as shown in
In a single-bit PCM, as described above, only two phases are distinguished: either the cell does or does not have a significant high-resistivity “mushroom cap” 2070. However, it is also possible to distinguish between different states of the mushroom cap 2070, and thereby store more than one bit per cell.
The downwards drift of reset resistance may be due to, for example, shrinking size of the amorphous zone of the phase-change material, due to crystal growth; and, in some cells, spontaneous nucleation steepening the drift curve (possibly only slightly) due to introducing further conductive elements into the mushroom-shaped programmable region.
A variety of nonvolatile memory technologies have been proposed over recent decades, and many of them have required some engineering to provide reference values for sensing. However, the requirements and constraints of phase-change memory are fundamentally different from those of any other kind of nonvolatile memory. Many memory technologies (such as EEPROM, EPROM, MNOS, and flash) test the threshold voltage of the transistor in a selected cell, so referencing must allow for the transistor's behavior. By contrast, phase-change memory simply senses the resistance of the selected cell. This avoids the complexities of providing a reference which will distinguish two (or more) possibilities for an active device's state, but does require detecting a resistance value, and tracking external variations (e.g. temperature and supply voltage) which may affect the instantaneous value of that resistance.
The possibility of storing more than one bit of data in a single phase-change material has also been suggested. Phase-change memories implementing such architectures are referred to here as “multibit” PCMs. If the “Set” and/or “Reset” operations can be controlled to produce multiple electrically distinguishable states, then more than one bit of information can be stored in each phase-change material location. It is known that the current over time profile of the Set operation can be controlled to produce electrically distinguishable results, though this can be due to more than one effect. In the simplest implementation, shorter anneals—too short to produce full annealing of the amorphous layer—can be used to produce one or more intermediate states. In some materials, different crystalline phases can also be produced by appropriate selection of the current over time profile. However, what is important for the present application is merely that electrically distinguishable states can be produced.
For example, if the complete layer of phase-change material can have four possible I/V characteristics, two bits of information can be stored in each cell—IF the read cycle can accurately distinguish among the four different states.
(The I/V characteristics of the cells which are not in the fully Set state are typically nonlinear, so it is more accurate to distinguish the states in terms of current flow at a given voltage; resistance is often used as a shorthand term, but implies a linearity which may not be present.)
In order to make use of the possible multibit cell structures, it is necessary to reliably distinguish among the possible states. To make this distinction reliably, there must be some margin of safety, despite the change in characteristics which may occur due to history, manufacturing tolerances, and environmental factors. Thus the read architecture of multibit PCMs is a far more difficult challenge it is for PCMs with single-bit cells.
The present application discloses surprising new approaches to PCM memories and memory arrays, and to chips and systems in which PCM is used, as well as methods for operating such systems.
Reference values for reads of PCM cells in corresponding words are generated using resistances of PCM reference cells associated with the word. Two columns of reference cells are included in the PCM array (or subarray), and, for each row, the two reference cells are preferably in opposite states. Whenever a row is read, the current outputs of the two reference cells are averaged (possibly with weighting) to provide a reference value. Since the two reference cells are guaranteed to be in opposite states, the (possibly weighted) average of their outputs will be intermediate between the output of a cell in the Set state (which one of them is) and a cell in the Reset state (which the other of them is). This provides a reference which will closely match variations in cell output due to parameter variation, supply voltage variation, temperature, and change due to wearout over time.
One optional use of the two columns of reference cells is to carry a checksum. For example, if column BLR1 holds the XOR of the values in columns 1-B, and column BLR2 holds the opposite value, the two reference columns are still sure to include both a “1” and a “0” value for each row.
The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments and which are incorporated in the specification hereof by reference, wherein:
The numerous innovative teachings of the present application will be described with particular reference to presently preferred embodiments (by way of example, and not of limitation). The present application describes several inventions, and none of the statements below should be taken as limiting the claims generally.
The present application discloses a way to make a novel phase change memory cell reference, generally entirely overcoming the need for coarse trimming. The reference comprises a boundary, or switchover point, between values that will be discriminated by a sense amplifier as a “0”, and values that will be discriminated as a “1”. By using PCM cell pairs (“reference cells”), each pair storing one “0” and one “1” state in single-bit PCM, applying the same voltage across both members of a pair, and using some ratio of the total current generated as a reference, the reference can be reliably matched to other PCM cells in the memory.
PCM materials generally exhibit an inherent “resistance drift” associated with each storage cell. Typically, drift increases during service at a predictable time-dependent rate characteristic of a corresponding PCM material, with the drift versus time curve starting from the time (t=0) when a PCM phase change (e.g., a write) occurs. By writing reference cells contemporaneously with a corresponding word of PCM memory, drift characteristics of the reference cells can be matched to drift characteristics of the co-written storage cells.
The cells used to generate the reference track the resistance drift and resistance temperature response characteristics of cells in a corresponding word. Therefore, the generated reference can be guaranteed to be between actual PCM cell outputs corresponding to “0” and “1” logical states from cells in the corresponding word. Because outputs from the corresponding word that correspond to a “0” logical state will always fall on one side of the reference, and outputs from the corresponding word that correspond to a “1” state will always fall on the other side of the reference, the reference can be used to reliably distinguish between “0” and “1” outputs.
If PCM read output values are viewed as currents, then for a read output corresponding to a high resistance PCM cell, Ipcm0, a read output corresponding to a low resistance PCM cell Ipcm1, and a reference signal I_Reference, the reference should obey the following inequality in order to distinguish Ipcm0 from Ipcm1: Ipcm0<I_Reference<Ipcm1. Margins between Ipcm0 and I_Reference, and between I_Reference and Ipcm1, can be targeted to optimize read quality (e.g., reliability).
For example, a reference may be generated by taking an average for a single pair of (2) reference cells, comprising 2 total reference cells, where Ipcm0 is the output current for a PCM cell in a logical “0” state, and Ipcm1 is the output current for a PCM cell in a logical “1” state,
A weighted average can also be used as a reference. A weighted average can be used, for example, to compensate for greater drift or more sensitive temperature response in one PCM logical state than the other. For example, with a and b as respective weights,
In some embodiments, multiple pairs of reference cells are used in order to obtain a more accurate result, preferably with the same voltage across all reference cells used to generate a single reference. As the number of reference cell pairs increases, reference accuracy increases. In this case, a reference is generated by taking a ratio (e.g., a weighted or unweighted average) of the summed outputs of corresponding reference cells. For a reference current generated from an average for
pairs of reference cells (such that
is an integer), comprising n total reference cells,
In some embodiments, where multiple pairs of reference cells are used to obtain a more accurate result, and a weighted average is used,
Also, when a word of data-storing cells 10 corresponding to a wordline 20 WLk are written, the reference cells 10 accessed by WLk, BLR1 and BLR2 are written with complementary logical states (e.g., “0” and “1”), so that the reference cells 10 approximately perfectly track the drift characteristics of the corresponding data-storing word.
In
When data-storing cells 10 in a word are accessed by activating corresponding wordlines 20 and bitlines 30, one or more pairs of reference cells 10 corresponding to said word on one or more Reference Lines T 70 and one or more Reference Lines N 90 are also accessed. The read outputs of the accessed reference cells 10 are summed together and averaged by a current multiplier 100 to produce a reference I_Reference 110. The reference 110 is used by the sense amplifiers to interpret <0:M−1>Master Bitline 120 signals—i.e., mux outputs—into corresponding logical states stored by the accessed cells 10. Master Bitline 120 signals are mux 40 outputs corresponding to outputs from accessed cells 10.
On a bitline 30 comprising data-storing cells, a PCM cell 10 that is part of a word written contemporaneously with corresponding reference cells 10 is also accessed by turning its wordline 20 and bitline 30 “On”. The resulting output current is compared by the Sense Amplifier 50 to I_Reference 110. If the data-storing cell 10 output current is higher than 1 Reference 110, then the data-storing cell 110 is detected to be storing a “1”; if the data-storing cell 10 output current is lower than 1 Reference 110, then the data-storing cell 10 is detected to be storing a “0”.
In
Also, when a word of data-storing cells 10 corresponding to a wordline WLk are written, the reference complement cell 10 accessed by WLk and BLRC is written with the complement of logical state stored by the data-storing/reference cell 10 accessed by WLk and BLB, so that the reference complement cell 10 approximately perfectly tracks the drift characteristics of the corresponding data-storing word.
Configuration data can be loaded into non-volatile memory for runtime accesses. Configuration data can be used to tune PCRAM and other component (e.g., power control 170, processing unit 190 or I/O unit 200) behavior in a design, test, or as-manufactured context. Configuration data can comprise, for example, information used by processing system components to operate external units 210; redundancy information, used to redirect accesses (read and write requests) from defective or otherwise inoperative memory cells 10 to redundant (backup) memory cells 10; trim information, generally used to alter the state of an existing topology when device features as-manufactured show variation—which can be expected within some degree of statistical distribution—that can be corrected using measures built into the device; test information used to implement test functions, e.g., for device design, design testing or as-manufactured quality assurance purposes; or to change timing (e.g., sense amp timing, or setup and hold timing in a data path), internal supply voltages, whether ECC (error correction) or other memory or other component functionality is activated, or other component operation parameters (such as word length or instruction set).
In some embodiments, a pair of reference cells 10 can be used to store a bit of information in the ordering of the corresponding stored “0” and “1” logical states. More pairs of reference cells 10 can generally store more information. If the pairing constraint is relaxed so that “0”s and “1”s can be stored anywhere within a group of reference cells 10 corresponding to a word (e.g., so that complementary logical states do not have to be adjacent to each other, or so that different logical states can be stored by different numbers of reference cells 10 in a group of reference cells 10 corresponding to a word), the ordering of said logical states can be used to store an even larger amount of information. Some constraint changes can require a more complex encoder and decoder to properly arrange storage of logical states to both conform to reference cell rules and store increased amounts of information. A single reference cell 10 pair can store, for example, a checksum (such as an XOR) for a corresponding word; or may store other information.
The amount of information encodeable in reference cells 10 corresponding to a word is proportional to the number of reference cells 10 and the combination of “0”s and “1”s stored by said reference cells 10. For example, the amount of storable information may be different if there are more “1”s than “0”s stored, rather than having an equal number of “1”s and “0”s. Generally, embodiments encoding information using ordering of logical states as stored in reference cells 10 will not have True 70 and Complement Reference Bitlines 90, as “0”s and “1”s can coexist along reference bitlines in such embodiments.
In some embodiments, reference cells 10 can be physically distributed in a memory (e.g., throughout an array); in other embodiments, they may be gathered together (e.g., along bitlines). Preferably, reference cells 10 are located to optimize timing (e.g., voltage rise and hold timing, sense amplifier 50 timing, and read timing in general) and drift matching pursuant to the particular operational characteristics of a PCM memory and component architectures thereof such as of sense amplifiers 50.
In some embodiments, after a reference 110 is generated, it is current mirrored and distributed to corresponding sense amplifiers 50.
The disclosed innovations, in various embodiments, provide one or more of at least the following advantages. However, not all of these advantages result from every one of the innovations disclosed, and this list of advantages does not limit the various claimed inventions.
read operation with approximately perfect drift tracking;
no need for coarse trimming;
reduced memory error correction requirements;
more accurate memory reads;
faster memory as a result of a reduced rate of read errors.
According to some but not necessarily all embodiments, there is provided: A method of operating a memory comprising: when phase change memory cells within a word of phase change memory cells are written, contemporaneously writing multiple logical states to multiple phase change memory reference cells accessed by the same wordline as said word; and when one or more accessed cells in said word are read, generating a reference corresponding to said logical states in at least partial dependence on respective resistances of said reference cells, and outputting respective logical states of said accessed cells in dependence on respective comparisons between said reference and respective outputs of said accessed cells.
According to some but not necessarily all embodiments, there is provided: A method of operating a memory comprising: when phase change memory cells within a word of phase change memory cells are written, contemporaneously writing multiple logical states to multiple phase change memory reference cells; and when one or more accessed cells in said word are read, generating a reference corresponding to said logical states in at least partial dependence on respective resistances of said reference cells, and outputting respective logical states of said accessed cells in dependence on respective comparisons between said reference and respective outputs of said accessed cells.
According to some but not necessarily all embodiments, there is provided: A method of operating a memory comprising: when phase change memory cells within a word of phase change memory cells are written, contemporaneously writing a pair of complementary logical states to one or more pairs of phase change memory reference cells, wherein the polarity of said pairs of reference cells indicates a parity checksum of said word; and when one or more accessed cells in said word are read, using the respective resistances of said reference cells to provide a reference, wherein an ordering of said logical states in said reference cells encodes information.
According to some but not necessarily all embodiments, there is provided: A method of operating a memory, comprising: when phase change memory cells within a word of phase change memory cells are written, contemporaneously writing one or more phase change memory reference cells with a state configured to output, when read, an average of phase change memory read outputs corresponding to two adjacent logical states; and when one or more accessed cells in said word are read, generating a reference corresponding to said logical states in at least partial dependence on respective resistances of said reference cells, and outputting respective logical states of said accessed cells in dependence on respective comparisons between said reference and respective outputs of said accessed cells.
According to some but not necessarily all embodiments, there is provided: A method of operating a memory, comprising: when phase change memory cells on a selected one of multiple wordlines of phase change memory cells are written, contemporaneously writing complementary logical states to two phase change memory reference cells in two additional columns on said selected one of said wordlines; and when one or more accessed cells on an accessed one of said wordlines are read, using the respective resistances of said two phase change memory reference cells to provide a reference value for reading said accessed cells; wherein said phase change memory reference cell in a first one of said columns provides a checksum for data on the same wordline.
According to some but not necessarily all embodiments, there is provided: A method of operating a processing system, comprising: contemporaneously writing multiple cells in corresponding ones of multiple words of phase change memory cells and multiple corresponding phase change memory reference cells, said words and said reference cells being within a phase change memory unit and configured to store configuration data; reading accessed cells in said corresponding word, using multiple sense amplifiers, by comparing respective outputs of said accessed cells and a reference, and by outputting respective logical states of said accessed cells in dependence on said comparing; and operating external elements, using a processor and/or an input/output unit, in accordance with said configuration data, wherein said reference is generated in at least partial dependence on respective resistances of said corresponding reference cells.
According to some but not necessarily all embodiments, there is provided: A processing system, comprising: a phase change memory unit, a processor which executes programmable instruction sequences, and an input/output unit; multiple words of phase change memory cells within said phase change memory unit configured to store configuration data, multiple cells in corresponding ones of said words and multiple corresponding phase change memory reference cells configured to be written contemporaneously; and multiple sense amplifiers configured to read accessed cells in said corresponding word by comparing respective outputs of said accessed cells and a reference, and by outputting respective logical states of said accessed cells in dependence on said comparing, wherein said reference is generated in at least partial dependence on respective resistances of said corresponding reference cells, and wherein said processor and/or said input/output unit operate external elements in accordance with said configuration data.
According to some but not necessarily all embodiments, there is provided: A memory, comprising: one or more words of phase change memory cells, configured to contemporaneously write cells in a corresponding one of said words and one or more corresponding pairs of phase change memory reference cells, wherein said pairs of reference cells are written with a pair of complementary logical states, and wherein the polarity of said corresponding pairs of reference cells indicates a parity checksum of said corresponding word; and access logic configured to output, when one or more accessed cells in said corresponding word are read, respective logical states of said accessed cells in dependence on respective comparisons between said reference and respective outputs of said accessed cells, wherein said reference is generated corresponding to said logical states in at least partial dependence on respective resistances of said corresponding pairs of reference cells.
According to some but not necessarily all embodiments, there is provided: A memory, comprising: an array of phase change memory cells; multiple words of phase change memory cells within said array, such that multiple cells within corresponding ones of said words and multiple corresponding phase change memory reference cells are configured to be written contemporaneously, said corresponding reference cells being configured to be written with multiple logical states and to be accessed by the same wordline as said corresponding word; and multiple sense amplifiers configured to read accessed cells in said corresponding word by comparing respective outputs of said accessed cells and a reference, and by outputting respective logical states of said accessed cells in dependence on said comparing, wherein said reference is generated in at least partial dependence on respective resistances of said corresponding reference cells.
According to some but not necessarily all embodiments, there is provided: A memory, comprising: an array of phase change memory cells comprising multiple words of data-storing cells and multiple groups of multiple reference cells, corresponding ones of said groups corresponding to ones of said words, reference cells in said corresponding groups being configured to be written with multiple logical states contemporaneously with writes to cells in said corresponding words; multiple word lines, ones of said word lines connected to access rows of said cells, ones of said corresponding words comprising respective portions of said rows of cells accessed by corresponding ones of said word lines; multiple bit lines, ones of said bit lines connected to access columns of said cells; and multiple sense amplifiers configured to read accessed cells in said corresponding word by comparing respective outputs of said accessed cells and a reference, and by outputting respective logical states of said accessed cells in dependence on said comparing, wherein said reference is generated in at least partial dependence on respective resistances of reference cells in said corresponding group.
According to some but not necessarily all embodiments, there is provided: A memory, comprising: a processor, said processor being configured to generate memory read requests and memory write requests; an array of phase change memory cells; multiple words of phase change memory cells within said array, multiple cells within corresponding ones of said words and multiple corresponding phase change memory reference cells configured to be written contemporaneously in response to memory write requests, said corresponding reference cells being written with multiple logical states; multiple sense amplifiers configured to read accessed cells in said corresponding words, in response to at least one corresponding read request designating said accessed cells, by comparing respective outputs of said accessed cells and a reference, and by outputting respective logical states of said accessed cells in dependence on said comparing, wherein said reference is generated in at least partial dependence on respective resistances of said corresponding reference cells.
According to some but not necessarily all embodiments, there is provided: A memory, comprising: one or more words of phase change memory cells, corresponding ones of said words configured to be written contemporaneously with corresponding phase change memory reference cells, said corresponding reference cells configured to be written with a state configured to output when read an average of phase change memory read outputs corresponding to adjacent complementary logical states; and multiple sense amplifiers configured to read accessed cells in said corresponding word by comparing respective outputs of said accessed cells and a reference, and by outputting respective logical states of said accessed cells in dependence on said comparing, wherein said reference is generated in at least partial dependence on respective resistances of said corresponding pairs of reference cells.
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given. It is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.
In some embodiments, ones of one or more words in an array of PCM cells correspond to multiple pairs of reference PCM cells.
In some embodiments, one or more reference PCM cells correspond to (are shared by) multiple words. In such embodiments, it is preferable to write said multiple words as closely to contemporaneously as possible in order to match drift characteristics of cells in said multiple words to drift characteristics of said shared reference cells as closely as possible. This can be useful, for example, when a substantial segment—or entirety—of a PCM array is being written together, such as during testing.
In some embodiments, three or more reference PCM cells correspond to a word of PCM cells. This can be used to, for example, enhance reliability and accuracy of the resulting reference generated from the three or more reference cells.
In some embodiments, reference cells can be read differentially, i.e., by comparing a read output of a reference cell to a read output of another PCM cell. This can be used, for example, to enhance read reliability of the reference cell.
In some embodiments, reference PCM cells are not paired in high/low resistance pairs, i.e., there can be more high (or low) resistance reference cells than low (or high) resistance reference cells. This can be used to save memory area where, for example, outputs of low resistance cells are significantly more reliable (e.g., more consistent output) than outputs of high resistance cells (or vice versa).
In some embodiments, if the output current of a PCM data-storing cell is higher than I_Reference (see
Embodiments have been disclosed hereinabove with particular numbers and configurations of wordlines, bitlines, sense amplifiers, muxes, data-storing cells, reference cells and other features. However, it will be apparent to one of ordinary skill that different arrangements of such features may be used to implement the inventions disclosed herein.
In some embodiments, bitline contents may not be strictly divided into data-storage bitlines and reference bitlines.
In some embodiments, a weighted arithmetic mean, geometric mean, or other operation producing a reference obeying the inequality described above, Ipcm0<I_Reference<Ipcm1, may be used to generate a reference (these means and other operations are referred to as “averages” for this purpose).
In some embodiments, all or substantially all cells in a word are configured to be written contemporaneously.
In some embodiments, all or substantially all cells in a word are configured to be read contemporaneously.
In some embodiments, SET and RESET pulses can be configured to reset PCM cell drift characteristics of PCM cells storing “0” and “1” logical states, i.e., without requiring a logical state transposition to reset cell drift characteristics.
In some embodiments, a transposition can be used to reset cell drift characteristics.
In some embodiments, resistance values configured to produce read outputs corresponding to those of PCM cells storing adjacent logical states with a pre-determined drift amount (e.g., no drift) are hard-coded, e.g., in resistance trims, in a PCM memory. When a corresponding word of PCM cells is written, the resistance trims are read, and a state configured to produce a read output corresponding to an average of the resistance trims' read outputs is written into one or more corresponding PCM reference cells. When the corresponding word is read, the corresponding PCM reference cells are read. If there is only one corresponding reference cell for the corresponding word, the corresponding reference cell's output is used as the reference for the corresponding word. If there are multiple corresponding reference cells, then their summed outputs are divided by the number of corresponding reference cells (or by another value resulting in a reference obeying the constraints described herein for I_Reference), and the resulting current is used as the reference for the corresponding word. In some embodiments, one or more resistance trims are hard-coded with resistances configured to output on read the average of read outputs of PCM cells storing adjacent logical states.
Additional general background, which helps to show variations and implementations, may be found in the following publications, all of which are hereby incorporated by reference: Lam, Chung. “Phase Change Memory: A Replacement or Transformational Memory Technology,” IEEE Workshop on Microelectronics and Electron Devices (WMED), c. 2011. Choi, Youngdon, et al. “A 20 nm 1.8V 8 Gb PRAM with 40 MB/s Program Bandwidth.” ISSCC 2012/Session 2/High Bandwidth DRAM & PRAM/2.5. c. 2012.
None of the description in the present application should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope: THE SCOPE OF PATENTED SUBJECT MATTER IS DEFINED ONLY BY THE ALLOWED CLAIMS. Moreover, none of these claims are intended to invoke paragraph six of 35 USC section 112 unless the exact words “means for” are followed by a participle.
Additional general background, which helps to show variations and implementations, as well as some features which can be synergistically with the inventions claimed below, may be found in the following US patent applications. All of these applications have at least some common ownership, copendency, and inventorship with the present application, and all of them are hereby incorporated by reference: U.S. Provisional Pat. Nos. 61/637,331; 61/637,496; 61/637,513; 61/637,518; 61/637,526; 61/637,533; 61/638,217; 61/694,217; 61/694,220; 61/694,221; 61/694,223; 61/694,224; 61/694,225; 61/694,228; 61/694,234; 61/694,240; 61/694,242; 61/694,243; and 61/694,245.
The claims as filed are intended to be as comprehensive as possible, and NO subject matter is intentionally relinquished, dedicated, or abandoned.
Priority is claimed from U.S. Provisional Patent Applications 61/694,223, 61/694,224, and 61/694,225, all filed Aug. 28, 2012, and all hereby incorporated by reference.
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61694223 | Aug 2012 | US | |
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61694225 | Aug 2012 | US |