Patent Application
20240079376
The field relates to bonded structures and methods of forming a direct hybrid bonded structure using rapid thermal processing.
Microelectronic elements, such as integrated device dies or chips, may be mounted or stacked on other elements thereby forming a bonded structure. Hybrid bonding involves directly bonding non-conductive features (e.g., inorganic dielectrics) of different elements together, without intervening adhesives, while also directly bonding conductive features (e.g., metal pads or lines) of the elements together. For example, a microelectronic element can be mounted to a carrier, such as a package substrate, an interposer, a reconstituted wafer or element, etc. As another example, a microelectronic element can be stacked on top of another microelectronic element, e.g., a first integrated device die can be stacked on a second integrated device die. Each of the microelectronic elements can have conductive pads for mechanically and electrically bonding the elements to one another. There is a continuing need for improved methods for forming the bonded structure.
Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation.
Various embodiments disclosed herein relate to directly bonded structures in which two or more elements can be directly bonded to one another without an intervening adhesive. Such processes and structures are referred to herein as “direct bonding” processes or “directly bonded” structures. Direct bonding can involve bonding of one material on one element and one material on the other element (also referred to as “uniform” direct bond herein), where the materials on the different elements need not be the same. Direct bonding can also involve bonding of multiple materials on one element to multiple materials on the other element (e.g., hybrid bonding).
In some embodiments, the elements 102 and 104 are directly bonded to one another without an adhesive using a suitable direct bonding process. In various embodiments, a non-conductive field region that includes a non-conductive or dielectric material can serve as a first bonding layer 108a of the first element 102 which can be directly bonded to a corresponding non-conductive field region that includes a non-conductive or dielectric material serving as a second bonding layer 108b of the second element 104 without an adhesive. The non-conductive bonding layers 108a and 108b can be disposed on respective front sides 114a and 114b of base substrate portions 110a and 110b. In some embodiments, the base substrate portion can comprise a device portion, such as a bulk semiconductor (e.g., silicon) portion of the elements 102, 103, and back-end-of-line (BEOL) interconnect layers over such semiconductor portions. Active devices and/or circuitry can be patterned and/or otherwise disposed in or on the base substrate portions 110a and 110b. Active devices and/or circuitry can be disposed at or near the front sides 114a and 114b of the base substrate portions 110a and 110b, and/or at or near opposite backsides 116a and 116b of the base substrate portions 110a and 110b. In other embodiments, the base substrate portions 110a, 110b may not include active circuitry, but may instead comprise dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. Bonding layers can be provided on front sides and/or back sides of the elements. The non-conductive material can be referred to as a non-conductive bonding region or bonding layer 108a of the first element 102. In some embodiments, the non-conductive bonding layer 108a of the first element 102 can be directly bonded to the corresponding non-conductive bonding layer 108b of the second element 104 using dielectric-to-dielectric bonding techniques.
To effectuate direct bonding between the bonding layers 108a, 108b, the bonding layers 108a, 108b can be polished to a high degree of smoothness (e.g., by chemical-mechanical polishing, or CMP), activated with a suitable species, and bonded to one another at room temperature, without the need for application of a voltage, and without the need for application of external pressure or force beyond that used to initiate contact between the two elements 102, 104. The nonconductive bonding surfaces 112a and 112b can be polished using, for example, chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 112a and 112b can be less than 30 Å rms. For example, the roughness of the bonding surfaces 112a and 112b can be in a range of about 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms.
The bonding surfaces 112a and 112b can be cleaned and exposed to a plasma and/or etchants to activate the surfaces 112a and 112b. In some embodiments, the surfaces 112a and 112b can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces 112a and 112b, and the termination process can provide additional chemical species at the bonding surfaces 112a and 112b that alters the chemical bond and/or improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma to activate and terminate the surfaces 112a and 112b. In other embodiments, the bonding surfaces 112a and 112b can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. For example, in some embodiments, the bonding surface(s) 112a, 112b can be exposed to a nitrogen-containing plasma. Further, in some embodiments, the bonding surfaces 112a and 112b can be exposed to fluorine. For example, there may be one or multiple fluorine concentration peaks at or near a bond interface 118 between the first and second elements 102, 104. Typically, fluorine concentration peaks occur at interfaces between material layers.
Thus, in the directly bonded structure 100, the bond interface 118 between two non-conductive materials (e.g., the bonding layers 108a and 108b) can comprise a very smooth interface with higher nitrogen content and/or fluorine concentration peaks at the bond interface 118. Additional examples of activation and/or termination treatments may be found throughout U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes. The roughness of the polished bonding surfaces 112a and 112b can be slightly rougher (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or possibly rougher) after an activation process. Accordingly, non-conductive or dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749.
In various embodiments, the bonding layers 108a and/or 108b can comprise a non-conductive material such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon. Suitable dielectric bonding surface or materials for direct bonding include but are not limited to inorganic dielectrics including silicon, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon oxycarbonitride, low K dielectric materials, SiCOH dielectrics, silicon carbonitride or diamond-like carbon or a material comprising a diamond surface. Such carbon-containing ceramic materials can be considered inorganic, despite the inclusion of carbon. In some embodiments, the dielectric materials at the bonding surface do not comprise polymer materials, such as epoxy (e.g., epoxy adhesives, cured epoxies, or epoxy composites such as FR-4 materials), resin or molding materials.
In some embodiments, at least one of the elements to be bonded can comprise an organic or ceramic substrate (e.g., as the base substrate portion 110a, 110b of the element). In such embodiments, for example, an inorganic bonding layer can be deposited on a first element including the organic or ceramic substrate (e.g., a package substrate including one or more organic or ceramic materials). A second element can be directly bonded to the inorganic bonding layer without an adhesive. Additional details regarding direct bonding to organic or ceramic substrates may be found throughout (and including at least, e.g., ¶¶[0016]-[0026] and [0038]-[0039] of) U.S. patent application Ser. No. 18/145,607, filed Dec. 22, 2022, the entire contents of which are incorporated by reference herein in their entirety and for all purposes.
In other embodiments, the bonding layers 108a and/or 108b can comprise an electrically conductive material, such as a deposited conductive oxide material, e.g., indium tin oxide (ITO). Additional examples of directly bonded structures utilizing conductive oxide materials can be found throughout U.S. Provisional Patent Application No. 63/524,564, filed Jun. 30, 2023, the entire contents of which is incorporated by reference herein in its entirety and for all purposes.
Embodiments described herein are particularly useful for reducing thermal budget consumption for direct hybrid bonding. For example, in some embodiments, the base substrate portions 110a and 110b can have significantly different coefficients of thermal expansion (CTEs) defining a heterogenous structure. The CTE difference between the base substrate portions 110a and 110b, and particularly between bulk semiconductor, typically single crystal portions of the base substrate portions 110a, 110b, can be greater than 5 ppm or greater than 10 ppm. For example, the CTE difference between the base substrate portions 110a and 110b can be in a range of 5 ppm to 100 ppm, 5 ppm to 40 ppm, 10 ppm to 100 ppm, or 10 ppm to 40 ppm.
In some embodiments, one of the base substrate portions 110a and 110b can comprise optoelectronic single crystal materials, including perovskite materials, that are useful for optical piezoelectric or pyroelectric applications, and the other of the base substrate portions 110a, 110b comprises a more conventional substrate material. For example, one of the base substrate portions 110a, 110b comprises lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other one of the base substrate portions 110a, 110b comprises silicon (Si), quartz, fused silica glass, sapphire, or a glass. In other embodiments, one of the base substrate portions 110a and 110b comprises a III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other one of the base substrate portions 110a and 110b can comprise a non-III-V semiconductor material, such as silicon (Si), or can comprise other materials with similar CTE, such as quartz, fused silica glass, sapphire, or a glass. It can be challenging to form a reliable bonding between such heterogenous substrates, and the stress from the CTE difference calls for a lower thermal budget during the annealing process. Various rapid thermal processes disclosed herein can enable such lower thermal budgets for annealing for direct hybrid bonded. The skilled artisan will appreciate that lowering thermal budgets for annealing can be advantageous for a number of other types of direct bonding as well.
In some implementations (not illustrated), each bonding layer has one material. The materials of opposing bonding layers on the different elements can be the same or different, and may comprise elemental or compound materials. In such implementations, the bonding layers can be patterned, or can be unpatterned such that the bonding surface of each element includes a blanket deposited material. For example, in some embodiments, nonconductive bonding layers can be blanket deposited over the base substrate portions without being patterned with conductive features (e.g., without pads). In other embodiments, the bonding layers can be patterned on one or both elements, and can be the same or different from one another, but one material from each element is directly bonded without adhesive across the surface(s) of the elements (or across the surface of the smaller element if the elements are differently-sized). For such directly bonded nonconductive bonding layers, it may be that only nonconductive materials are bonded to one another (e.g., there are no conductive direct bonds between the elements). Such direct bonding processes may be referred to as “uniform” direct bond to signify that only one material on each element is directly bonded. Example uniform direct bonding processes include the ZIBOND® techniques commercially available from Adeia of San Jose, CA. In such uniform direct bonding processes, one or both of the nonconductive bonding layers may be without any conductive features patterned therein. Alternatively, one or both of the nonconductive bonding layers may include one or more conductive features, but the conductive features are not involved in the bonding. An alternative example of uniform direct bonding processes can include electrically conductive material(s), such as deposited conductive oxides, as disclosed in U.S. Provisional Patent Application No. 63/524,564, filed Jun. 30, 2023, the entire contents of which are incorporated by reference in their entirety and for all purposes.
In various embodiments, hybrid bonds can be formed without an intervening adhesive. Most commonly, hybrid bonds involve opposing nonconductive surfaces that are directly bonded without an intervening adhesive and opposing conductive features that are directly bonded without an intervening adhesive. For example, as explained above, nonconductive bonding surfaces 112a and 112b can be prepared for direct bonding, such as by polishing to a high degree of smoothness, activating and/or terminating with a suitable species, and bringing into contact with one another (for example, at room temperature and without application of pressure beyond that used to bring the elements 102, 104 into contact). In hybrid bonding, conductive features 106a of the first element 102 can also be directly bonded to corresponding conductive features 106b of the second element 104 without an adhesive (e.g., without solder or other conductive adhesive intervening between the conductive features 106a, 106b). For example, a direct hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along the bond interface 118 that includes covalently direct bonded non-conductive-to-non-conductive (e.g., dielectric-to-dielectric) surfaces, prepared as described above. In various embodiments, the conductor-to-conductor (e.g., conductive feature 106a to conductive feature 106b) direct bonds and the dielectric-to-dielectric direct bonds can be formed using the hybrid bonding techniques disclosed at least in U.S. Pat. No. 9,716,033, the entire contents of which are incorporated by reference herein in their entirety and for all purposes. In hybrid bonding embodiments described herein, conductive features are provided within non-conductive bonding layers, and both conductive and nonconductive features are prepared for direct bonding, such as by the planarization, activation and/or termination treatments described above. Thus, the bonding surface prepared for hybrid bonding includes both conductive and non-conductive features.
For example, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b (for example, inorganic dielectric surfaces) can be prepared and directly bonded to one another without an intervening adhesive as explained above. Conductive contact features (e.g., conductive features 106a and 106b which may be at least partially surrounded by non-conductive dielectric field regions within the bonding layers 108a, 108b) may also directly bond to one another without an intervening adhesive. In various embodiments, the conductive features 106a, 106b can comprise discrete pads or traces at least partially embedded in the non-conductive field regions. In some embodiments, the conductive contact features can comprise exposed contact surfaces of through substrate vias (e.g., through silicon vias (TSVs)).
In some embodiments, prior to direct bonding portions of the respective conductive features 106a and 106b can be recessed below exterior (e.g., upper) surfaces (non-conductive bonding surfaces 112a and 112b) of the dielectric field region or non-conductive bonding layers 108a and 108b, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm. The recess can be at or near the middle or center of the cavity in which the conductive features 106a, 106b are disposed, and, additionally or alternatively, can extend or be disposed along sides of the cavity in which the conductive features 106a, 106b are disposed. In various embodiments, prior to direct bonding, the recesses in the opposing elements can be sized such that the total gap between opposing contact pads is less than 15 nm, or less than 10 nm.
The non-conductive bonding layers 108a and 108b can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure 100 can be annealed. Upon annealing, the conductive features 106a and 106b can expand and contact one another to form a metal-to-metal direct bond. Beneficially, the use of Direct Bond Interconnect, or DBI®, techniques commercially available from Adeia of San Jose, CA, can enable high density of conductive features 106a and 106b to be connected across the direct bond interface 118 (e.g., small or fine pitches for regular arrays).
In some embodiments, a pitch p of the conductive features 106a and 106b, such as conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 100 μm, less than 10 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive features 106a and 106b to one of the dimensions (e.g., a diameter) of the bonding pad is less than is less than 20, or less than 10, or less than 5, or less than 3 and sometimes desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range between 0.3 μm to 50 μm, e.g., in a range of 0.3 μm to 20 μm, 0.3 μm to 3 μm, 0.5 μm to 50 μm, 0.75 μm to 25 μm, or 1 μm to 5 μm. In various embodiments, the conductive features 106a and 106b and/or traces can comprise copper or copper alloys, although other metals may be suitable. For example, the conductive features disclosed herein, such as the conductive features 106a and 106b, can comprise fine-grain metal (e.g., a fine-grain copper). Further, a major lateral dimension (e.g., a pad diameter) can be small as well, e.g., in a range of about 0.25 μm to 30 μm, in a range of about 0.25 μm to 5 μm, or in a range of about 0.5 μm to 5 μm.
Thus, in direct bonding processes, a first element 102 can be directly bonded to a second element 104 without an intervening adhesive. In some arrangements, the first element 102 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element 102 can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 104 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element 104 can comprise a carrier or substrate (e.g., a wafer). The embodiments disclosed herein can accordingly apply to wafer-to-wafer (W2 W), die-to-die (D2D), or die-to-wafer (D2 W) bonding processes. In W2 W processes, two or more wafers can be directly bonded to one another (e.g., direct hybrid bonded) and singulated using a suitable singulation process. After singulation, side edges of the singulated structure (e.g., the side edges of the two bonded elements) can be substantially flush (substantially aligned x-y dimensions) and/or the edges of the bonding interfaces for both bonded and singulated elements can be coextensive, and may include markings indicative of the common singulation process for the bonded structure (e.g., saw markings if a saw singulation process is used).
As explained herein, the first and second elements 102 and 104 can be directly bonded to one another without an adhesive, which is different from a deposition process and results in a structurally different interface compared to a deposition. In one application, a width of the first element 102 in the bonded structure is similar to a width of the second element 104. In some other embodiments, a width of the first element 102 in the bonded structure 100 is different from a width of the second element 104. Similarly, the width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element. The first and second elements 102 and 104 can accordingly comprise non-deposited elements. Further, directly bonded structures 100, unlike deposited layers, can include a defect region along the bond interface 118 in which nanometer-scale voids (nanovoids) are present. The nanovoids may be formed due to activation of the bonding surfaces 112a and 112b (e.g., exposure to a plasma).
As explained above, the bond interface 118 can include concentration of materials from the activation and/or last chemical treatment processes. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen concentration peak can be formed at the bond interface 118. The nitrogen concentration peak can be detectable using secondary ion mass spectroscopy (SIMS) techniques. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace OH groups of a hydrolyzed (OH-terminated) surface with NH2 molecules, yielding a nitrogen-terminated surface. In embodiments that utilize an oxygen plasma for activation, an oxygen concentration peak can be formed at the bond interface 118. In some embodiments, the bond interface 118 can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers 108a and 108b can also comprise polished surfaces that are planarized to a high degree of smoothness.
For hybrid bonded elements 102, 104, as shown, the orientations of one or more conductive features 106a, 106b from opposite elements can be opposite to one another. As is known in the art, conductive features in general can be formed with close to vertical sidewalls, particularly where directional reactive ion etching (RIE) defines the conductor sidewalls either directly though etching the conductive material or indirectly through etching surrounding insulators in damascene processes. However, some slight taper to the conductive features' sidewalls can be present, wherein the conductor becomes narrower farther away from the surface initially exposed to the etch. The taper can be even more pronounced when the conductive sidewall is defined directly or indirectly with isotropic wet or dry etching. In the illustrated embodiment, at least one conductive feature 106b in the bonding layer 108b (and/or at least one internal conductive feature, such as a BEOL feature) of the upper element 104 may be tapered or narrowed upwardly, away from the bonding surface 112b. By way of contrast, at least one conductive feature 106a in the bonding layer 108a (and/or at least one internal conductive feature, such as a BEOL feature) of the lower element 102 may be tapered or narrowed downwardly, away from the bonding surface 112a. Similarly, any bonding layers (not shown) on the backsides 116a, 116b of the elements 102, 104 may taper or narrow away from the backsides, with an opposite taper orientation relative to front side conductive features 106a, 106b of the same element.
As described above, the non-conductive bonding layers 108a, 108b can be directly bonded to one another without an adhesive and, subsequently, the bonded structure 100 can be annealed. Upon annealing, the conductive features 106a, 106b can expand and contact one another to form a metal-to-metal direct bond. In some embodiments, the materials of the conductive features 106a, 106b can interdiffuse during the annealing process. In various embodiments, the metal-to-metal bonds between the conductive features 106a and 106b can be joined such that metal grains grow into each other across the bond interface 118. In some embodiments, the metal is or includes copper, which can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface 118. In some embodiments, the conductive features 106a and 106b may include nanotwinned copper grain structure, which can aid in merging the conductive features during anneal. The bond interface 118 can extend substantially entirely to at least a portion of the bonded conductive features 106a and 106b, such that there is substantially no gap between the non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer may be provided under and/or laterally surrounding the conductive features 106a and 106b (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the conductive features 106a and 106b, for example, as described in U.S. Pat. No. 11,195,748, which is incorporated by reference herein in its entirety and for all purposes.
As described herein, in direct bonding processes, such as uniform direct bonding and hybrid bonding, two elements are bonded together without an intervening adhesive. In non-direct bonding processes that utilize an adhesive, an intervening material is typically applied to one or both elements to effectuate a physical connection between the elements. For example, in some nonconductive adhesive-based processes, a flowable adhesive (e.g., an organic adhesive, such as an epoxy) can be applied to one or both elements and cured to form the physical connection between elements. In such nonconductive adhesive processes, the adhesive does not form a strong chemical bond with either element. In other processes, a conductive adhesive (e.g., solder) can be provided between the two elements, heated to melt the conductive adhesive, and cooled to form the connection between the two elements. In both nonconductive and conductive adhesive processes, the resulting attachment of the two adhered elements results from an intervening material that sticks or adheres to the two opposing elements to be joined. The connection is primarily a physical connection between the two elements, and does not involve the formation of covalent bonds or grain growth across the elements.
By contrast, direct bonding processes join two elements by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials and/or by causing grain growth across the bonding interface between opposing conductive materials. For example, in direct bonding processes between nonconductive materials, one or both nonconductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and/or terminated) such that when the elements are brought into contact, strong chemical bonds (e.g., covalent bonds) are formed, which are stronger than Van der Waals or hydrogen bonds. In some implementations (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bonds can occur spontaneously at room temperature upon being brought into contact. In some implementations, the chemical bonds can be strengthened after annealing the elements (e.g., for opposing conductive oxide structures, such as opposing ITO layers).
In hybrid bonding processes the interface includes conductive direct bonds and the conductive material (e.g., metallic material) typically expands upon annealing, but the direct bonds between surrounding nonconductive materials resist separation of the elements, such that the thermal expansion increases the internal contact pressure between the opposing conductive features. Annealing can also cause metallic grain growth across the bonding interface, such that grains from one element migrate across the bonding interface at least partially into the other element, and vice versa. Thus, in direct bonding processes that include conductive direct bonds, opposing conductive materials are joined without melting the conductive materials, such that bonds can form with much lower anneal temperatures compared to adhesive-based processes, such as soldering, where the conductive materials are heated above the melting temperature.
Various embodiments disclosed herein relate to using a rapid thermal process (RTP) to anneal the bonded structure 100. The RTP uses radiant energy sources to heat the bonded structure 100. The RTP can enable the bonded structure 100 to be heated to a target temperature, such as a temperature in a range of 250° C. to 500° C., very quickly compared to conventional convection oven annealing (e.g., less than 10 seconds, 7 seconds, 5 seconds, or 3 seconds). The RTP can more quickly heat the bonded structure 100 than other types of heating process, such as convection heating and conductive heating processes. Although RTP has been employed for annealing in a number of other contexts, it has been challenging to obtain temperature uniformity across substrates due to the nature of rapid radiant heating.
Various embodiments disclosed herein can utilize two or more heating mechanisms for heating a bonded structure. For example, the bonded structure can be heated by way of the RTP and a non-RTP heating process such as a convection or conduction heating that does not use radiant energy for heating the bonded structure. In some embodiments, the bonded structure can be heated by way of the RTP, and separately heated by the non-RTP heating process in a separate anneal tool.
In some embodiments, an anneal system can include both an RTP zone (such as the illustrated RTP system 1), as well as a non-RTP heating system 2 having a second heating source 19, as shown in
The first non-conductive field region 20 of the first element 5 is directly bonded to the second non-conductive field region 24 without an intervening adhesive along a bond interface 18. Surfaces of the first non-conductive field region 20 and the second non-conductive field region 24 can be prepared for direct bonding prior to contacting the first and second elements 5, 6, as described herein. For example, one or both of the surfaces of the first and second elements 5, 6 can be polished to have a surface roughness of less than 15 Å rms, less than 10 Å rms, or less than 5 Å rms. For example, the one or both of the surfaces of the first and second elements 5, 6 can have a surface roughness in a range of 1 Å rms to 15 Å rms, 1 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. As noted above, the direct bond between non-conductive materials of the two elements can be formed at room temperature, and can include formation of covalent bonds.
The conductive features 22, 26 can be recessed below respective bonding surfaces of the non-conductive field region 20, 24. For example, the conductive features 22, 26 can be recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm, relative to the respective bonding surfaces of the non-conductive field region 20, 24. In some embodiments, the recesses in the opposing elements 5, 6 can be sized such that the total gap between opposing conductive features 22, 26 is less than 15 nm, or less than 10 nm after the room temperature bonding of non-conductive materials and prior to annealing.
The first and second conductive features 22, 26 can comprise any suitable conductive material. In some embodiments, the first and second conductive features 22, 26 can comprise metal, such as copper. For example, the first and second conductive features 22, 26 can comprise a fine grain metal (e.g., fine grain copper). The fine grain metal can be defined as a metal having an average grain width less than 20 nm, less than 50 nm, less than 100 nm, less than 300 nm, or less than 500 nm. For example, the maximum width of grain in the fine grain metal can be in a range of 10 nm to 500 nm, 20 nm to 500 nm, or 100 nm to 300 nm. Various benefits of using the RTP disclosed herein may be pronounced when a fine grain metal is used as the first and/or second conductive features 22, 26 as compared to using larger grain metals. Additional details of fine grain metals may be found throughout U.S. patent application Ser. Nos. 17/684,841, 18/066,159, and 18/305,149, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
The RTP can quickly increase the temperature of the bonded structure 4a such that the first and second conductive features 22, 26 expand to make contact with one another. For example, the RTP can bring the temperature of the bonded structure 4a to a target temperature, such as a temperature in a range of 250° C. to 500° C., in, for example, less than 10 seconds, 7 seconds, 5 seconds, or 3 seconds. In some embodiments, due to the material characteristics of the non-conductive portion (the first and second non-conductive field region 20, 24) and the conductive portion (the first and second conductive features 22, 26), the radiation used in the RTP can raise the temperature of the conductive portion more quickly than the non-conductive portion. For example, silicon and dielectric materials conventionally used to form microelectronic elements, such as integrated circuits, tend to be more transparent to wavelengths used in RTP tools as compared to conductive materials like metals. This can cause problems in some contexts, since the temperature of the overall substrate or element can be measured but may not reflect the actual temperature of more absorbent conductive materials. Nevertheless, the non-uniform absorption of radiant heat can be beneficial for annealing in the direct hybrid bonding context. Because the temperature of the conductive portion can be raised more quickly than the non-conductive portion, the conductive portion can be heated to a higher temperature than the non-conductive portion at a given time. Conventional hybrid bonding anneals rely on differences in coefficients of thermal expansion (CTE) between the conductive materials and their surrounding non-conductive materials to achieve differential expansion of the conductive materials into contact. However, in the present disclosure, radiant heat aids thermal expansion of the conductive materials by providing differential temperatures in addition to differential CTE. Both temperature differentials and CTE differentials contribute to differential expansion of the conductive materials relative to the surrounding non-conductive materials, which can enable a reliable bond between the first and second conductive features 22, 26 at lower temperatures and/or lower anneal times compared to conventional annealing.
The anneal may include multiple phases, of which one or more phases are rapid thermal anneals. For example,
As a result of the first annealing process, the bonded structure 4b can include a rapid growth structure 40 characteristic of an RTP anneal. In some embodiments, the rapid growth structure 40 can be different from a result of a non-RTP heating process. For example, the rapid growth structure 40 can comprise grain configurations traversing the bond interface 18 (see
In the bonded structure 4b, interdiffusion between the bonded first and second conductive features 22, 26 may take place. However, in some embodiments, a majority of the interdiffusion between the bonded first and second conductive features 22, 26 can take place in a second annealing process (see
In the embodiment of
After the second annealing process, at least a portion of the rapid growth structure 40 can remain as a rapid growth structure 40′. In other words, some of the grain configurations characteristic of RTP anneal can remain near the bond interface 18 of the conductive features 22, 26. In some embodiments, the rapid growth structure 40′ can include a stress gradient and/or a gradient of interdiffused metal atoms. In some embodiments, the bonded structure 4c can be the final structure and the following step(s) (
At block 44, a second element can be provided. The second element can include a second non-conductive field region and a second conductive feature. The second element can be prepared for hybrid direct bonding, with a bonding layer including the second non-conductive field region and the second conductive feature, as well as planarization, activation and/or termination, as disclosed herein.
At block 46, the first element and the second element can be directly bonded to one another to form a bonded structure. The first non-conductive field region is directly bonded to the second non-conductive field region without an intervening adhesive, and the first conductive feature is aligned with the second conductive feature. Alignment need not be perfect. In some embodiments, the bonded structure can be annealed at a low temperature to strengthen the nonconductive-to-nonconductive bond between the first non-conductive field region and the second non-conductive field region. The temperature of the low temperature anneal can be less than 200° C., or less than 150° C. At block 46, direct contact between the first and second conductive features are not formed.
At block 48, the bonded structure can be heated or annealed by way of an annealing process to form contact between the first and second conductive features. The annealing process can comprise a rapid thermal process (RTP). As described above, such RTP can be implemented by radiant heating. Including attendant overhead (substrate loading, purging, temperature ramping up, temperature ramping down, substrate unloading), the annealing process at block 48 can be in a range of 4 minute to 8 minutes. Excluding overhead, the actual high temperature plateau portion of the annealing process at block 48 may be, for example, less than 10 seconds, 7 seconds, 5 seconds, or 3 seconds for contact to be formed. The bonded structure can be annealed for a longer duration (e.g., 10 seconds to 20 minutes) for forming more contact between the first and second conductive features.
The RTP of the first annealing process 48 can enable the first and second conductive features to make contact relatively quickly. Without being limited to theory, the rapid growth structures 40 described above may facilitate early contact during anneal by RTP. The early contact between the first and second conductive features can reduce the duration of the second annealing process to make a desired final structure, including strengthened contact between conductive features and non-conductive features, compared to a process within the first annealing process 48. The first annealing process can enable the total duration of annealing process(es) to be shortened as compared to a conventional annealing process. Thus, various embodiments disclosed herein can enable manufacture of a bonded structure with a lower thermal budget than conventional methods.
The bonded structure 7a of
The bonded structure 4b can be annealed at peak temperature T2 by way of the non-RTP heating process (e.g., conductive or convective heating) for a duration of t2. The duration t2 can be greater than the duration t1. The duration t2 of the second anneal 50 can be between about 10 minutes and 180 minutes, more particularly between about 30 minutes and 120 minutes. The peak temperature for the non-RTP phase (second anneal 50) can be between about 120° C. and 300° C., more particularly between about 150° C. and 250° C.
In
In
A suitable annealing process and a suitable annealing duration can be selected based at least in part on the materials and dimensions of various components of a bonded structure.
A thermal treatment process can include a preparation process, an annealing process (e.g., one or more rapid thermal processes (RTPs) as disclosed herein), and a cooling process. For example, the preparation process can include loading a bonded structure (e.g., the bonded structure 4a shown in
The thermal treatment system 70 can include a load lock 72, a rapid thermal process (RTP) chamber 74, and a cooling chamber 76. The load lock 72, the RTP chamber 74, and the cooling chamber 76 can be connected, for example, by isolation valves 78. A bonded structure 4a can be provided in the load lock 72 in a preparation process. After the preparation process, the bonded structure 4a can be provided in the RTP chamber 74 for annealing to provide an annealed bonded structure 82 (e.g., the bonded structure 4b, 4c, 4d, 7a, 7b, 7c, 7d of
In some embodiments, the load lock 72 can be a vacuum chamber. The load lock 72 can transfer the bonded structure 4a between two environments with different levels of cleanliness or atmospheric conditions. For example, the two environments can be the RTP chamber 74 and an outside environ of the RTP chamber 74. Implementing the load lock 72 can contribute to increasing throughput. In the load lock 72, the bonded structure 4a can be purged with, for example, an inert gas (e.g., nitrogen (N2)). Although shown as directly communicating with the RTP chamber 74, the skilled artisan will appreciate that the load lock 72 can communicate substrates through an isolatable transfer chamber, and that such a transfer chamber can directly communicate substrates (through gate valves) to each of the RTP chamber 74 and the cooling chamber 76, rather than directly connecting the two chambers 74, 76. Additionally, convective or conductive ovens can also be provided in a cluster tool to add multiple anneal phases to the process as described herein.
In the RTP chamber 74, any one or more of the annealing processes disclosed herein can be conducted. The annealing process(s) in the RTP chamber 74 can directly bond the first and second conductive features 22, 26 of the bonded structure 4a to be bonded, thereby creating a conductor-to-conductor direct bonding.
In some embodiments, the cooling chamber 76 can include an actively cooled chuck 80 that has a cooling mechanism integrated or coupled therewith. The annealed bonded structure 82 can be held by the actively cooled chuck 80 to reduce the temperature of the annealed bonded structure 82 to a desired temperature. In some embodiments, the annealed bonded structure 82 can be instead or additionally convectively cooled by way of purging in the cooling chamber 76. For example, the annealed bonded structure 82 can be purged with a cooled inert gas (e.g., nitrogen (N2)). The actively cooled chuck 80 and/or the purge cooling can enable the annealed bonded structure 82 to be cooled more quickly than natural or passive cooling, thereby reducing the thermal budget. The skilled artisan will appreciate that after cooling the annealed bonded structure 82 can be unloaded through a separate isolation valve, or back through the load lock chamber 72 (by way of the intervening RTP chamber 78, or through any intervening transfer chamber).
The annealing chamber 92 can include a heat source 10 (e.g., lamps or laser sources as described above), and a cooling mechanism (e.g., the actively cooled chuck 80). In the first state (the heating cycle), the bonded structure 4a can be spaced apart from the actively cooled chuck 80 by way of, for example, pins 94 or pillars that can extend between the actively cooled chick 80 and the bonded structure 4a. In the second state (the cooling cycle), the bonded structure 4a can be closer to (e.g., in contact with) the actively cooled chuck 80. The pins 94 can lift and descend the bonded structure 4a relative to the actively cooled chuck 80. The load lock 72 and the annealing chamber 92 can contribute to increasing throughput, and the active cooling mechanism (e.g., the actively cooled chuck 80) and/or the purge cooling can enable the annealed bonded structure 82 to be cooled more quickly than natural or passive cooling, thereby reducing the thermal budget. The purge cooling as described with respect to
In one aspect, a method of forming a bonded structure is disclosed. The method includes providing a first element including a first non-conductive field region and a first conductive feature, and directly bonding the first element to a second element. The second element includes a second non-conductive field region and a second conductive feature such that the first non-conductive field region is directly bonded to the second non-conductive field region without an intervening adhesive. The first conductive feature is aligned with the second conductive feature. The method also includes, after directly bonding the first element to the second element, annealing the first and second elements by way of rapid thermal process.
In some embodiments, after directly bonding the first element to the second element and before annealing the first and second elements by way of rapid thermal process, the first and second conductive features are spaced by a gap. The gap between the first and second conductive features can be bridged by expansion of the first and second conductive features due to the rapid thermal process. The method can further include annealing the first and second elements by way of a convection or conduction heating process to strengthen a bonding strength between the first non-conductive field region and the second non-conductive field region prior to annealing the first and second elements by way of rapid thermal process. The method can further include annealing the first and second elements by way of a convection or conduction heating process after electrically connecting the first and second conductive features for a duration that is longer than a duration of the rapid thermal process.
In one embodiment, annealing the first and second elements by way of rapid thermal process includes forming a rapid growth structure connecting the first conductive feature to the second conductive feature in multiple locations.
In some embodiments, the rapid thermal process includes heating the bonded first and second elements by way of a radiant energy source. The radiant energy source can include radiant heat lamps. The radiant heat lamps can include infrared halogen lamps.
In some embodiments, the first element further includes a first device portion and the second element further includes a second device portion. The first device portion can include an optoelectronic single crystal material. The second device portion can include silicon (Si), quartz, fused silica glass, sapphire, or a glass. The first device portion can include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3).
In one embodiment, the method further includes, after directly bonding the first element to the second element and prior to annealing the first and second elements, providing the first and second elements in a load lock.
In one embodiment, the method further includes, after annealing the first and second elements, actively cooling the first and second elements.
In another aspect, a method of direct bonding is disclosed. The method includes directly bonding non-conductive regions of a first element to non-conductive regions of a second element to form a bonded structure. The method includes, after directly bonding the non-conductive regions, annealing the bonded structure to bridge a gap between aligned conductive features of the first element and the second element in the bonded structure. Annealing includes exposing the bonded structure to radiant heating.
In one embodiment, the method further includes polishing a bonding surface of the first element to have a surface roughness in a range of 1 Å rms to 15 Å rms.
In one embodiment, annealing the bonded structure further includes exposing the bonded structure to a convection or conduction heating process prior to exposing the bonded structure to radiant heating.
In one embodiment, annealing the bonded structure further includes exposing the bonded structure to a convection or conduction heating process after exposing the bonded structure to the radiant heating. Exposing to the convection or conduction heating process can be conducted for a duration that is longer than a duration of exposing to the radiant heating at a temperature that can be lower than a peak temperature of the bonded structure during exposing to the radiant heating.
In one embodiment, exposing the bonded structure to the radiant heating includes forming extensions between the aligned first and second conductive features of the first and second elements.
In some embodiments, annealing the bonded structure includes annealing the bonded structure for a duration in a range of 0.5 seconds to 5 minutes at a maximum temperature in a range of 200° C. to 500° C. A ramp up rate during exposing the bonded structure to radiant heating before reaching the maximum temperature can be in a range of 10° C. per second to 150° C. per second.
In one embodiment, a majority of the first element includes a first material having a first coefficient of thermal expansion and a majority of the second element includes a second material having a second coefficient of thermal expansion that is at least 5 ppm different from the first coefficient of thermal expansion.
In another aspect, a method of forming a bonded structure is disclosed. The method includes providing a first element including a first surface dielectric region and surface metal region, and directly bonding the first element to a second element. The second element includes a second surface dielectric region and a second surface metal region such that the first surface dielectric region is directly bonded to the second surface dielectric region without an intervening adhesive. The first surface metal region is aligned with the second surface metal region. The method also includes, after directly bonding the first element to the second element, annealing the first and second elements by way of an annealing process thereby providing a conductive contact between the first and second surface metal regions. The annealing process includes a phase with a ramp up rate in a range of about 10° C. per second to 150° C. per second.
In one aspect, a bonded structure is disclosed. The bonded structure includes a first element including a first non-conductive field region and a first conductive feature. The bonded structure includes a second element including a second non-conductive field region and a second conductive feature. The second element is directly bonded to the first element along a bond interface such that the first non-conductive field region is directly bonded to the second non-conductive field region without an intervening adhesive. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive. The bond interface between the first and second conductive features includes a rapid growth structure indicative of annealing by a rapid thermal process.
In one embodiment, the rapid growth structure includes a plurality of grain extensions between the first and second conductive features.
In one embodiment, the rapid growth structure includes a stress gradient and/or a gradient of interdiffused metal atoms.
In some embodiments, the first element is a wafer or a die. The second element can be a wafer or a die.
In one embodiment, the first element further includes a first device portion and the second element includes a second device portion. The first device portion can include a first material having a first coefficient of thermal expansion and the second device portion can include a second material having a second coefficient of thermal expansion that is at least 5 ppm different from the first coefficient of thermal expansion.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
This application claims priority to U.S. Provisional Patent Application No. 63/374,881, filed Sep. 7, 2022, titled “RAPID THERMAL PROCESSING FOR DIRECT BONDING,” the entire contents of each of which are hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63374881 | Sep 2022 | US |
