Claims
- 1. A memory device comprising:
- an array of memory cells arranged in addressable rows and columns;
- the memory device receiving row addresses, column addresses, control signals and data representing an image for display;
- logic apparatus responsive to the control signals for generating a selected control signal;
- a row decoder, responsive to individual ones of the row addresses, for selecting a selected row of the array of memory cells; and
- a column decoder, responsive to individual ones of the column addresses and the selected control signal, for selecting either a single column of the array of memory cells or a plurality of columns of the array of memory cells for writing the data representing the image, the data being simultaneously written into the plurality of columns of the array of memory cells.
- 2. The memory device, in accordance with claim 1, further comprising:
- a color register;
- a data bus for applying the data representing the image to the color register; and
- a multiplexer, responsive to the selected control signal, for selecting the data from the color register, that data being simultaneously written into a plurality of memory cells in the selected row of the array.
- 3. The memory device, in accordance with claim 2, further comprising:
- a mask register;
- the data bus for also applying data to the mask register for storage; and
- a circuit for writing a portion of the data, stored in the color register and masked by the data stored in the mask register, simultaneously to a plurality of memory cells in the selected row of the memory array.
- 4. The memory device, in accordance with claim 3, wherein:
- the writing circuit writes a portion of plural different data, masked by the first data stored in the mask register, to a plurality of memory cells in different selected rows of the memory array during plural memory cycles.
- 5. The memory device, in accordance with claim 1, further comprising:
- a mask register;
- the bus applying first data to the mask register for storage; and
- a circuit for writing a portion of second data, masked by the first data stored in the mask register, simultaneously to a plurality of memory cells in the selected row of the memory array.
- 6. The memory device, in accordance with claim 5, wherein:
- the writing circuit writes a portion of plural different data, masked by the first data stored in the mask register, to a plurality of the memory cells in different selected rows of the memory array during plural memory cycles.
- 7. A data processing system comprising:
- a central processing unit generating row address signals, column address signals, and control signals; and
- a memory device comprising:
- an array of memory cells arranged in addressable rows and columns;
- the memory device receiving the row addresses, column addresses, control signals and data representing an image for display;
- logic apparatus responsive to the control signals for generating a selected control signal;
- a row decoder, responsive to individual ones of the row addresses, for selecting a selected row of the array of memory cells; and
- a column decoder, responsive to individual ones of the column addresses and the selected control signal, for selecting either a single column of the array of memory cells or a plurality of columns of the array of memory cells for writing the data representing the image, the data being simultaneously written into the plurality of columns of the array of memory cells.
Parent Case Info
This is a division of application Ser. No. 07/535,243, filed 06/06/90, now abandoned, which is a continuation of Ser. No. 07/089,634, filed Aug. 26, 1987, now abandoned, which is a continuation in part of Ser. No. 07/053,200, filed May 21, 1987, now U.S. Pat. No. 4,817,058.
This application is a continuation-in-part of my prior copending application Ser. No. 053,200 (TI-I2073), filed on May 21, 1987 and assigned to Texas Instruments Incorporated.
This application is related to prior copending applications Ser. No. 081,926 (TI-12074), and Ser. No. 081,948 (TI-12921), both filed Aug. 5, 1987 and assigned to Texas Instruments Incorporated.
US Referenced Citations (12)
Foreign Referenced Citations (3)
Number |
Date |
Country |
61-288240 |
Dec 1986 |
JPX |
62-279596 |
Dec 1987 |
JPX |
822290 |
Apr 1981 |
SUX |
Divisions (1)
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Number |
Date |
Country |
Parent |
535243 |
Jun 1990 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
80634 |
Aug 1987 |
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Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
53200 |
May 1987 |
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