Patent Application
20140158414
Mounting of discrete components on a substrate using surface mount methods can lead to an electronics package having undesirable package height, commonly referred to as a z-height. Using surface mount technologies, discrete components, such as capacitors, resistors, inductors, and other components are typically attached to a die side substrate surface with solder balls on the substrate that are reflowed when the component is placed on the balls. This provides a secure electrical and retentive connection of the component directly to the substrate. Many times, the z-height of a resulting package and component is higher than desired in a product in which the package will be used.
A device includes an organic multiple layer substrate having patterned conductors disposed on a recessed layer of the organic multiple layer substrate. A discrete component is coupled to the recessed layer via a surface mount process such that the component is recessed from a top layer of the organic multiple layer substrate.
A method includes patterning conductors on a selected layer of an organic multiple layer substrate, forming a releasable layer on the selected layer between the patterned conductors, forming an additional layer on the selected layer and releasable layer, forming an opening through the additional layer to form a recess in the multiple layer substrate, removing the releasable layer, and attaching a component to substrate within the recess.
A further method includes patterning conductors on a selected layer of an organic multiple layer substrate, forming a releasable layer on the selected layer between the patterned conductors, forming an additional layer on the selected layer and releasable layer, forming an opening through the additional layer to form a recess in the multiple layer substrate, removing the releasable layer, and attaching the discrete component to the selected layer such that the component is recessed in the organic multiple layer substrate.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
The discrete component 130 may be mounted on a layer by the use of a standard surface mount process corresponding to each electrical connection to be made between the component and metal lands on the corresponding layer of the substrate. In one embodiment, the surface-mount process utilizes a solder paste (solder and flux mix) that is dispensed onto lands. The discrete component 130 is placed on top of that paste and reflowed (melted) into place. In various embodiments, the discrete component may be a capacitor, resistor, inductor, or other component. Such discrete components may not be easily reduced in height. By recessing the discrete component in the substrate 100, lower Z-height profiles of resulting packages that include the substrate 100 may be obtained without expending resources in attempting to reduce the height of the components themselves. Recessing the components may also provide for reduced parasitic effects, including reduced parasitic capacitance and parasitic resistance.
Process steps to form substrate 200 having a recessed discrete component are illustrated in schematic cross section in
In
In one embodiment, the component is recessed at or below the top surface of the substrate 200. In further embodiments, the component may be recessed such that a top of the component is still above the substrate top surface, but lower than it would be had it been attached to the substrate top surface.
1. A method comprising:
patterning conductors on a selected layer of an organic multiple layer substrate;
forming a releasable layer on the selected layer between the patterned conductors;
forming an additional layer on the selected layer and releasable layer;
forming an opening through the additional layer to form a recess in the multiple layer substrate;
removing the releasable layer; and
attaching a component to substrate within the recess.
2. The method of example 1, wherein the substrate comprises a polymer core with multiple symmetric layers formed on a top and a bottom of the core.
3. The method of example 2, wherein forming an additional layer comprises forming multiple additional layers; and
wherein the forming an opening comprises forming a recess through multiple layers to the selected layer.
4. The method of any of examples 1-3, wherein the component is a capacitor.
5. The method of any of examples 1-4, wherein the component is a resistor.
6. The method of any of examples 1-5, wherein the component is an inductor.
7. The method of any of examples 1-6, wherein the opening is formed via laser scribing.
8. The method of any of examples 1-7, wherein the releasable layer is formed via a squeeze process.
9. The method of any of examples 1-8, wherein attaching a component to the substrate within the recess is performed by:
dispensing solder paste through a nozzle onto the patterned conductors on the selected layer;
placing the component on the solder paste; and
reflowing the solder paste to solder the component to the patterned conductors.
10. A method comprising:
patterning conductors on a selected layer of an organic multiple layer substrate;
forming a releasable layer on the selected layer between the patterned conductors;
forming an additional layer on the selected layer and releasable layer;
forming an opening through the additional layer to form a recess in the multiple layer substrate;
removing the releasable layer;
surface mounting a discrete component to the selected layer such that the component is recessed in the organic multiple layer substrate.
11. The method of example 10, wherein the substrate comprises a glass reinforced resin core with multiple symmetric layers formed on a top and a bottom of the core.
12. The method of example 11, wherein forming an additional layer comprises forming multiple additional organic layers; and
wherein the forming an opening comprises forming a recess through multiple layers to the selected layer.
13. The method of any of examples 10-12, wherein the component is a discrete capacitor.
14. The method of any of examples 10-13, wherein the component is a discrete resistor.
15. The method of any of examples 10-14, wherein the component is an discrete inductor.
16. The method of any of examples 10-15, wherein the releasable layer is formed via a squeeze process.
17. A device comprising:
an organic multiple layer substrate;
patterned conductors disposed on a recessed layer of the organic multiple layer substrate; and
a discrete component coupled to the recessed layer such that the component is recessed from a top layer of the organic multiple layer substrate.
18. The device of example 17, wherein multiple layers of the organic multiple layer substrate are symmetrically disposed about an organic core.
19. The device of any of examples 17-18, wherein the organic multiple layer substrate comprises a polymer core with multiple symmetric layers formed on a top and a bottom of the core.
20. The device of example 19, wherein the component is recessed multiple layers.
21. The device of any of examples 19-20, wherein the component is a capacitor.
22. The device of any of examples 19-21, wherein the component is a resistor.
23. The device of any of examples 19-22, wherein the component is an inductor.
Although a few embodiments have been described in detail above, other modifications are possible. For example, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. Other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Other embodiments may be within the scope of the following claims, such as packages with pin grid array, land grid array, die connected to substrate through wire bond, etc.
The Abstract is provided to comply with 37 C.F.R. Section 1.72(b) requiring an abstract that will allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
