Patent Application
20220399236
The present invention relates in general to semiconductor devices and, more particularly, to a device and method for positioning regions of interests during laser-assisted bonding.
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
Many aspects of the manufacturing process become problematic and must be improved or replaced when semiconductor devices are reduced in size. Semiconductor die are typically mounted onto a substrate by disposing solder bumps of the semiconductor die in contact with contact pads of the substrate. The assembly is heated in an oven to reflow the solder bumps and thereby attach the semiconductor die to the substrate.
As semiconductor die, along with accompanying interconnect structures, are made smaller and thinner, the impact of the reflow oven process is more damaging to the electrical parts. Laser-assisted bonding (LAB) has been adopted as an improved solution. LAB uses a laser to apply energy directly to the back side of the die being mounted, which is converted to thermal energy to reflow solder bumps on the front side of the die. LAB provides more localized heat than a reflow oven and is able to reflow bumps with a shorter cycle time. The result is that LAB can be used to mount a die to a substrate with a reduced likelihood of damaging thin die and interconnect layers.
An important aspect of LAB is the use of an infrared (IR) camera to monitor the temperature of the die in real time. The temperature is monitored inside specific areas of the die known as regions-of-interest (ROI). Currently, the IR camera is positioned manually by an engineer, and then specific pixels on the IR camera are monitored as ROI to maintain acceptable temperatures. The manual IR camera placement is susceptible to human error that can cause the ROI locations to be misplaced. Reliably replicating ROI positioning is difficult. Accordingly, a need exists for an improved method and system for aligning the IR camera to regions-of-interest during laser-assisted bonding.
The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.
Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental protection. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contacts within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, bond wires, or other suitable interconnect structure. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.
An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer 112 operates as contact pads electrically connected to the circuits on active surface 110.
An electrically conductive bump material is deposited over conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, combinations thereof, or other suitable conductive materials with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, bump 114 is formed over an under-bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. Bump 114 can also be compression bonded or thermocompression bonded to conductive layer 112. Bump 114 represents one type of interconnect structure that can be formed over conductive layer 112. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.
In
To incorporate semiconductor die 104 into an electronic device, bumps 114 are typically reflowed onto contact pads 124 of a larger substrate 120 as shown in
Substrate 120 is formed from a base insulating material with conductive layers 124 formed over top and bottom surfaces of the interposer and interleaved between layers of the insulating material. Conductive layers 124 include contact pads, conductive traces, and conductive vias configured as necessary to implement a desired signal routing. Portions of conductive layers 124 are electrically common or electrically isolated depending on the design and function of the device being formed. Conductive layers 124 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In some embodiments, passivation or solder resist layers are formed over the top and bottom surfaces of substrate 120 with openings to expose contact pads of conductive layer 124.
Substrate 120 can also be any suitable laminate interposer, PCB, wafer-form, strip interposer, leadframe, or other type of substrate. Substrate 120 may include one or more laminated layers of polytetrafluoroethylene (PTFE) pre-impregnated (prepreg), FR-4, FR-1, CEM-1, or CEM-3 with a combination of phenolic cotton paper, epoxy, resin, woven glass, matte glass, polyester, and other reinforcement fibers or fabrics. Insulating material of substrate 120 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), and other material having similar insulating and structural properties. Substrate 120 can also be a multi-layer flexible laminate, ceramic, copper clad laminate, glass, or semiconductor wafer including an active surface containing one or more transistors, diodes, and other circuit elements to implement analog or digital circuits. Substrate 120 can be any suitable substrate for a semiconductor package or electronic device.
In laser-assisted bonding, a LAB assembly 130 is disposed over semiconductor die 104 with the semiconductor die sitting on substrate 120. LAB assembly 130 is mounted onto a gantry that allows the X-Y position of the LAB assembly to be controlled. X-Y position means that the position can be controlled along the X and Y axes, but not necessarily the Z-axis. The X-Y plane is oriented parallel to the major surfaces of substrate 120. The X-axis is the axis that extends left-to-right in
LAB assembly 130 includes a laser homogenizer 132. Homogenizer 132 receives a laser beam input via a fiber optic cable, waveguide, or other suitable mechanism, and outputs a homogenized laser beam 134 over semiconductor die 104. A beam homogenizer is a device that smooths out the irregularities in a laser beam profile and creates a more uniform one. Most beam homogenizers use a multifaceted mirror with square facets. The mirror reflects light at different angles to create a beam with substantially uniform power across the entire profile of beam 134.
The energy of beam 134 is absorbed by semiconductor die 104 and converted to thermal energy to reflow bumps 114. In some embodiments, back surface 108 includes an electrically conductive layer formed over semiconductor die 104 as an electromagnetic interference (EMI) shielding layer. The conductive layer also improves efficiency of conversion from laser energy to thermal energy during LAB. Back surface 108 can also have other types of laser absorbing layers formed from any material that increases the absorption of the laser's energy.
Numerous substrates 120 and semiconductor die 104 are placed on carrier 122 at the same time, and LAB assembly 130 is moved by the gantry to perform LAB one at a time on each die. After one semiconductor die 104 has been processed, vision camera 138 is used to align LAB assembly 130 over the next die by finding fiducial markers on substrate 120 or by identifying the corners of the die. The gantry moves LAB assembly 130 until laser homogenizer 132 is aligned with the next semiconductor die 104 as reported by vision camera 138.
An infrared (IR) camera 136 is attached to LAB assembly 130 and positioned off to the side of laser homogenizer 132. Due to the positioning of IR camera 136, the IR camera typically needs to be tilted at an angle theta (θ) to properly view die 104. The angle θ is typically about 70 degrees but can vary. IR camera 136 provides a thermal image of semiconductor die 104 during the LAB process. The thermal image is used to monitor temperatures of semiconductor die 104 in real time while LAB is performed.
ROI 150a at the center of die 104 is positioned equidistant between each pair of opposing sides of the die as shown in
Each ROI 150a-150e is typically the same size, a dimension 156 along the X-axis and a dimension 158 along the Y-axis. If dimensions 156 and 158 are different, ROI 150 are rectangular. If dimension 156 equals dimension 158, ROI 150 are square. ROI 150 are shaped differently from each other or shaped irregularly in other embodiments.
Distances 152, 154, 162, and 164 and dimensions 156 and 158 are all measured in number of pixels on the image captured by IR camera 136. The goal during LAB is to monitor temperature on fixed pixels of IR camera 136 relative to the corners of semiconductor die 104. Due to the realities of manufacturing equipment having moving mechanical parts, IR camera 136 can move slightly relative to the rest of LAB assembly 130 during the manufacturing process. If IR camera 136 is moved slightly, then the pixels of IR camera 136 being monitored will no longer be in the correct location relative to the corners of semiconductor die 104.
Angular offset 172 is enough to significantly move ROI 150 within the footprint of semiconductor die 104, as shown in
Similarly,
After image processing, the resultant image in
Using bitmap 192, the exact pixel locations of die center 153a and corners 153b-153e can be easily identified as shown in
The ROI coordinate list from table 1, along with ROI size, can be manually entered or automatically imported into the LAB software that actually does the temperature monitoring for the ROI 150. The coordinates indicate a corner pixel for each ROI 150, which, along with the ROI size, tell the LAB software specifically which pixels of IR image 190 to monitor. The ROI pixels can be recalculated for each die 104 being bonded or the same pixels can be reused for each die 104 being processed either for an entire carrier 122 or for as long as different units of the same die 104 and substrate 120 are being processed. The coordinates can optionally be reused until LAB assembly 130 is manually touched, until a positioning error is detected, or automatically recalculated periodically (e.g., daily or hourly).
The image processing software creates a bitmap showing the exact location of die 104 in the IR image, and then automatically pinpoints the exact pixels for the corners as indicated by markers 212b-212e and the center as indicated by marker 212a. The image processing software then places ROI 150a-150e based on the pixels identified by the markers. ROI 210b-210e are placed with one corner four pixels inward in both the X and Y directions from markers 212b-212e, respectively. The opposite corner of each corner ROI 210b-210e is placed four additional pixels inward in both the X and Y directions.
Center marker 212a is placed at the average position of all four corner markers 212b-212e. Center ROI 210a is placed at center marker 212a with a size of four pixels by four pixels. A distance 216 in the Y direction is the same between edges of semiconductor die 104 in both directions. A distance 218 in the X direction is the same between edges of semiconductor die 104 in both directions. The square representations of ROI 210b-210e illustrate the pixels of the image that will be monitored during LAB.
The image processing software creates a bitmap showing the exact location of die 104 in the IR image, and then pinpoints the exact pixels for the corner as indicated by markers 222b-222e. The image processing software places one corner of corner ROI 220b-220e eight pixels inward in both the X and Y directions from markers 222b-222e, respectively. The opposite corner of each corner ROI 220b-220e is placed eight additional pixels inward in both the X and Y directions.
A center marker 222a is placed at the average position of all four corner markers 222b-222e. Center ROI 220a is placed at center marker 222a with a size of eight pixels by eight pixels. A distance 226 in the Y direction is the same between edges of semiconductor die 104 in both directions. A distance 228 in the X direction is the same between edges of semiconductor die 104 in both directions. The square representations of ROI 220b-220e correspond to the pixels of the image that will be monitored during LAB. LAB proceeds with the pixels identified as ROI being monitored to keep temperatures of semiconductor die 104 within acceptable limits.
Once all die 104 on a substrate 120 are bonded via LAB, manufacturing proceeds with other desired steps. Any type of package can be formed. Just one example of the many possibilities in
The panel formed by substrate 120 and encapsulant 230 is singulated in
Electronic device 350 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 350 can be a subcomponent of a larger system. For example, electronic device 350 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device 350 can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor die or electrical components.
PCB 300 provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces 302 are formed over a surface or within layers of PCB 300 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 302 provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces 302 also provide power and ground connections to the semiconductor packages as needed.
In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB 300. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB 300.
For the purpose of illustration, several types of first level packaging, including bond wire package 356 and flipchip 358, are shown on PCB 300. Additionally, several types of second level packaging, including ball grid array (BGA) 360, bump chip carrier (BCC) 362, land grid array (LGA) 366, multi-chip module (MCM) 368, quad flat non-leaded package (QFN) 370, and quad flat package 372 are shown mounted on PCB 300 along with die 104 and package 234. Conductive traces 302 electrically couple the various packages and components disposed on PCB 300.
Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 300. In some embodiments, electronic device 350 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
