Patent Application
20080165569
The present invention is directed generally to memory circuitry and, more particularly, to phase change memories.
The possibility of using phase change materials (PCMs) in nonvolatile memory cells has recently gained momentum as more is learned about these materials and their integration into integrated circuits. When incorporated in a memory cell, for example, these materials may be toggled between higher and lower electrical resistivity phases by applying a pulse of electrical current (“switching current pulse”) to the memory cell which acts to heat the PCM. Applying a switching current pulse that results in the PCM heating above its crystallization temperature causes the PCM to achieve a relatively low resistivity crystalline phase. Applying a larger magnitude switching current pulse (often called a “RESET” current pulse), on the other hand, causes the PCM to melt and to enter a relatively high resistivity amorphous phase during the subsequent cooling. After writing to the memory cell in this way, the overall electrical resistance state of the given memory cell may be determined (i.e., read) by applying a low magnitude sensing voltage to the memory cell in order to determine its electrical resistance state. Presently, binary and ternary chalcogenide alloys such as doped SbTe and Ge2Sb2Te5 (GST) are showing the greatest promise for use in practical PCM-based memory cells.
Notably, many PCM-based memory cells are capable of being reproducibly switched between greater than two resistance states by varying the magnitude of the switching current pulse. This phenomenon was reported in, for example, U.S. Pat. No. 5,296,716 to Ovshinsky et al., entitled “Electrically Erasable, Directly Overwritable, Multibit Single Cell Memory Elements and Arrays Fabricated Therefrom,” and may be attributable to placing differing portions of a given volume of PCM into crystalline and amorphous phases. Advantageously, such a dynamic frequently gives a PCM-based memory cell the ability to simultaneously store more than one bit of data.
Nevertheless, despite their apparent advantages, a multibit PCM-based memory cell frequently displays an extremely high overall resistance when a portion of its PCM volume is in an amorphous phase.
For the foregoing reasons, there is a need for a multibit PCM-based memory cell design that allows the incorporated PCM to be configured into a higher resistivity phase without causing the memory cell to have an extremely high overall resistance value and a relatively slow reading speed.
Embodiments of the present invention address the above-identified needs by providing a multibit PCM-based memory cell design that allows the incorporated PCM to be configured into a higher resistivity phase without causing the memory cell to have an extremely high overall resistance value and a relatively slow reading speed.
In accordance with an aspect of the invention, a memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a PCM and a resistor material. At least a portion of the PCM is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.
In accordance with an illustrative embodiment of the invention, a memory cell comprises a lower electrode and an upper electrode between which is disposed a composite material. The composite material comprises a PCM interspersed with a multiplicity of resistor clusters. At least a portion of the PCM is operative to switch between a lower resistivity crystalline phase and a higher resistivity amorphous phase in response to the passing of a pulse of current through the composite material. The resistor clusters, in turn, comprise a resistor material that has a lower resistivity than the PCM when the PCM is in its higher resistivity amorphous phase. Advantageously, when reading the memory cell having at least a portion of the PCM is in its higher resistivity amorphous phase, some of the read current passes through the resistor clusters. The overall resistance of the memory cell is thereby reduced by using the composite material rather than using a PCM alone. Reading speed may thereby be enhanced.
These and other features and advantages of the present invention will become apparent from the following detailed description which is to be read in conjunction with the accompanying drawings.
The present invention will be described with reference to illustrative embodiments. For this reason, numerous modifications can be made to these embodiments and the results will still come within the scope of the invention. No limitations with respect to the specific embodiments described herein are intended or should be inferred.
Particularly with respect to processing steps, it is emphasized that the descriptions provided herein are not intended to encompass all of the processing steps which may be required to successfully form a functional integrated circuit device. Rather, certain processing steps which are conventionally used in forming integrated circuit devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description. However one skilled in the art will readily recognize those processing steps omitted from these generalized descriptions. Moreover, details of the processing steps used to fabricate such integrated circuit devices may be found in a number of publications, for example, S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Volume 1, Lattice Press, 1986 and S. M. Sze, VLSI Technology, Second Edition, McGraw-Hill, 1988.
The term “phase-change material” (PCM) as used herein is intended to encompass any material displaying more than one programmable electrical resistivity state for use in integrated circuits. It is recognized that this definition may encompass more materials than are customarily included within this term. PCMs as used herein comprise, for example, various chalcogenides and transition metal oxides and include, but are not limited to, doped or undoped GeSb, SbTe, Ge2Sb2Te5 (GST), SrTiO3, BaTiO3, (Sr,Ba)TiO3, SrZrO3, In2Se3, Ca2Nb2O7, (Pr,Ca)MnO3, Ta2)5, NiOx and TiOx, as well as other suitable materials.
It should be noted that the figures are not drawn to scale. Moreover, the figures are simplified to illustrate aspects of the invention and, as a result, some elements required to form a functional semiconductor device may not be explicitly shown. These missing elements will be familiar to one skilled in the art.
In accordance with aspects of the invention, the composite material 330 comprises a PCM 332 and a resistor material. The resistor material is in the form of discrete resistor clusters 334 that are dispersed throughout the PCM. Moreover, the resistor material forming the resistor clusters has a lower resistivity than the PCM when the PCM is in its substantially amorphous phase. The composition and formation of the PCM and resistor clusters will be described in greater detail below.
Storing data in the memory cell 300 comprises placing some fraction of the total volume of the PCM 332 into a higher resistivity amorphous phase while the remainder of the PCM remains in a lower resistivity crystalline phase. In this way, the method of writing to the memory cell 300 is similar to that used to write to a conventional multibit PCM-based memory cell like, for example, memory cell 100 shown in
The duration of the switching current pulse is preferably between about 1 and about 500 nanoseconds and has a fast falling edge (i.e., less than about ten nanoseconds), although the invention is not limited to any particular duration and/or rise or fall time of the switching current pulse. The fast falling edge acts to freeze the PCM 332 in its current phase without allowing additional time for the bonds within the material to continue to rearrange.
After writing to the memory cell 300, reading the state of the memory cell may be accomplished by applying a sensing voltage to the memory cell, again via the lower and upper electrodes 310, 320. The sensing voltage is preferably of low enough magnitude to provide negligible ohmic heating in the PCM 332. Accordingly, the electrical resistance state of the memory cell may be determined in this manner without disturbing its written electrical resistance state. Data integrity is thereby maintained while reading the data.
Advantageously, the inclusion of the resistor clusters 334 in the composite material 330 substantially reduces the overall resistance of the memory cell 300 when some portion of the PCM 332 is in its amorphous phase.
If the resistor material, moreover, has a resistivity higher than that of the PCM 332 in its crystalline phase, the read current will avoid the resistor clusters 334 in those portions of the composite material 330 comprising the PCM in its lower resistivity crystalline phase. This is the condition shown in
As stated above, the lower and upper electrodes 310, 320 and the composite material 330 in the memory cell 300 are formed into a pillar arrangement. Nonetheless, this is just one design contemplated for a memory cell in accordance with aspects of this invention.
Alternatively, a memory cell in accordance with aspects of the invention may appear like memory cell 500 shown in
As even another alternative, a memory cell may be configured like memory cell 600 shown in
Generally, the choice of the particular resistor material in a given memory cell embodiment will depend on the choice of the associated PCM. As stated before, the resistivity of the resistor material will be lower than that of the PCM in its amorphous phase (and, optionally, higher than the PCM in its crystalline phase). GST in its amorphous phase typically has a resistivity of about one KΩ-cm, depending on how the GST is deposited and whether the GST is doped. Suitable resistor material may therefore comprise a myriad of metallic and semiconductor materials. Such materials will preferably be commonly used in semiconductor processing for ease of manufacture and will not interdiffuse into the PCM and cause the PCM properties to be degraded. Possible choices include, for example, tantalum nitride, tantalum silicon nitride, titanium nitride, tungsten or tungsten nitride.
Formation of the composite material may be accomplished using several different techniques, many of which are variations on semiconductor processing steps that will be familiar to one skilled in that art. Sputter deposition, for example, is one of the most widely used techniques for the fabrication of thin film structures on semiconductor wafers. It is usually carried out in diode plasma systems known as magnetrons, in which a target is sputtered by ion bombardment and emits atoms and molecules, which are then deposited on the wafer in the form of a thin film. Several such sputter deposition tools are commercially available from semiconductor tool vendors such as Applied Materials, Inc.® (Santa Clara, Calif., USA). GST sputter targets, moreover, are commonly available from a number of vendors such as Applied Material, Inc. and Canon Anelva Corp (Tokyo, Japan). The composition of a given sputter target, moreover, may be custom tailored for a particular application. A single sputter target, may, for example, comprise more than one type of material for deposition.
Accordingly, one method for depositing the composite material is to sputter the composite material using a mixed sputter target comprising both the PCM and the resistor material. Alternatively, the composite material may be formed using two sputter targets, one comprising the PCM and the other comprising the resistor material. The two sputter targets may then be alternated as the deposition progresses.
As even another alternative, sputter deposition or other deposition techniques may be used to deposit a PCM that is heavily doped with the chosen resistor material. If the concentration of the resistor material in the PCM is higher than the solubility level of the PCM, the resistor material will segregate out from the PCM and form the desired resistor clusters.
What is more, the composite material may be formed using pre-formed resistor clusters. Pre-formed nanometer sized resistor clusters (e.g., 3-10 nm in size) may, for example, be suspended in a solution and deposited by a conventional spin coating process. In spin coating, the solution is placed on the substrate as the substrate is rotated at high speed in order to spread the solution by centrifugal force. The solution may comprise, for example, a volatile alcohol that may be removed by evaporation after the spin coating process is completed.
As even another alternative, nanometer sized particles (nanoparticles) of material other than the resistor material may be used in conjunction with largely conventional semiconductor processing techniques to form the composite material.
It should be noted that, while the composite materials 860 and 960 in the memory cells shown in
It should also be noted that the memory cells described above are part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and is stored in a computer storage medium (such as a disk, tape, physical hard drive or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (i.e., as a single wafer that has multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product (e.g., motherboard) or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Although illustrative embodiments of the present invention have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made to these embodiments by one skilled in the art without departing from the scope of the appended claims.
