Patent Application
20230089791
The present application relates to a semiconductor memory device and a method of forming the same. More particularly, the present application relates to an analog resistive memory device structure and/or method of fabricating an analog resistive memory.
RRAM is considered a promising technology for electronic synapse devices or memristors for neuromorphic computing as well as high-density and high-speed non-volatile memory applications. RRAM is a type of non-volatile random access memory that works by changing the resistance across a dielectric solid-state material. The basic idea is that the dielectric solid-state material, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage. The conduction path can arise from different mechanisms, including vacancy or metal defect migration. Once the filament is formed, it may be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by another voltage. Many current paths, rather than a single filament, are possibly involved.
In neuromorphic computing applications, a resistive memory device can be used as a connection (i.e., synapse) between a pre-neuron and a post-neuron, representing the connection weight in the form of device resistance. Multiple pre-neurons and post-neurons can be connected through a crossbar array of RRAMs, which naturally expresses a fully connected neural network.
Moreover, nonvolatile RRAM memory has emerged as a viable device for storage and analog computing, e.g., especially due to its compatibility for CMOS logic processing.
However, in current designs, the resistance of current RRAM devices exhibit abrupt changes when responding to electrical pulses, so such RRAM devices are not suitable for analog computing in artificial intelligence (AI) applications.
The present application provides an analog resistive memory device, i.e., a resistive random access memory (RRAM) cell, with at least one electrode having varying compositions so that the resistance of the inventive RRAM changes gradually.
In an aspect, the RRAM structure is capable of exhibiting a gradual change of resistance, e.g., in response to electrical pulses/voltage levels, thereby rendering it suitable for AI applications.
The provided RRAM structure capable of exhibiting a gradual change of resistance operation is formed as a 2-terminal RRAM cell and includes an electrode with gradually varying compositions to make a RRAM change its resistance gradually in response to electrical pulses/voltage levels.
The present application provides a method for forming a RRAM structure capable of exhibiting a gradual change of resistance in response to electrical pulses/voltage levels, thereby rendering it suitable for AI applications.
According to first aspect, there is provided a resistive memory device. The resistive memory device comprises: a first metal electrode layer having a varying metal material composition; a resistive dielectric material layer over a top surface and a sidewall surface of the first electrode; and a second metal electrode over the resistive dielectric material layer.
According to further aspect, there is provided a resistive memory device. The resistive memory device comprises: a stack of alternating first metal electrode material layers and insulating material layers therebetween, each successive first metal electrode material layer of the stack having a different metal material composition; a resistive dielectric material layer on a top surface and sidewall surface of the stack; and a second metal electrode over the resistive dielectric material layer, wherein the conductance of the resistive memory device changes gradually during application of a voltage applied between the stack of the alternating first metal electrode material layers and the second metal electrode.
In accordance with another aspect, there is provided a method of forming a memory device. The method comprises: forming a first electrode layer on a substrate wherein the first electrode has varying metal material composition; patterning the first electrode to expose a sidewall; depositing a resistive element on the sidewall of the first electrode; and forming a second electrode over the resistive element.
The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
Referring first to
The transition metal oxide that is formed between a top electrode 172 (e.g., an anode) and a bottom electrode (e.g., a cathode) of the RRAM device 102 includes an HfOx switching medium situated between two electrodes. Conductive filaments can be formed between the two electrodes to provide a conducting path between the electrodes. The filaments can be formed by applying an appropriate amount of voltage to the RRAM device that program the resistive element 102 to store a logic or weight value corresponding to either a high-resistance cell state, a low-resistance cell state, or other resistive states.
As known from the reference to H.-L. Chang entitled “Physical Mechanism of HfO2-based Bipolar Resistive Random Access Memory,” Symp. VLSI-TSA, 2011, the resistance switching between high resistance state (HRS) and low resistance state (LRS) of HfO2-based RRAM is based on the formation and rupture of Hf filaments via an electrochemical redox process in a region of a few nm near the metal terminal (i.e., anode).
For example, shown in
2O2−→2O+4e−
while the Hf4+ ions (a type of oxygen vacancies) reduce at cathode in a reduction operation according to:
Hf
4++4e−→Hf
As shown in
2O+4e−→2O2−
while Hf filaments oxidize to have Hf4+ ions in an oxidation operation according to:
Hf→Hf
4++4e−
The recombination of Hf4+ and O2− according to:
Hf
4++2O2−→HfO2
causes the filaments to rupture partially (a few nm) near the anode, making RRAM exhibit HRS after a RESET. Once a positive voltage (<forming voltage) is applied, the filaments form again in the rupture region, switching RRAM back to LRS after SET. The rupture and reformation of the Hf filaments occurring in a few nm near anode explains the high-speed (<5 ns) switching of the RRAM.
Thus, an initial state of most RRAM devices is a High Resistance State (HRS), in which the RRAM resistance is considered higher than a specific value. The first operation to turn the RRAM device to the Low Resistance State (LRS) is the “forming” operation. The LRS resistance is preferred to be smaller than the HRS resistance by a sufficient amount so that a supporting circuit is able to discern the RRAM state unambiguously. In the “forming” operation in which an applied voltage across the device exceeds a certain level, i.e., a forming voltage, the RRAM cell responsively starts changing its state from HRS to LRS. In a circuit, the maximum current of the RRAM device can be constrained by a current limiter, e.g., a transistor (not shown).
After the forming operation in which the RRAM devices are rendered into a LRS, to transition the RRAM device operation between low resistance and high resistance states, a reset operation is performed in which the applied voltage across the device sweeps negatively and upon exceeding a certain “reset” voltage limit, the RRAM device will change the state from LRS back to HRS. This process is called a RESET operation. When the voltage changes to positive again and exceeds another “set” voltage limit, the RRAM will change its state from HRS to LRS. This process is called a SET operation. The RRAM device can be worked back and forth between HRS and LRS by respective RESET and SET operations wherein a sufficiently low negative voltage RESETs the device, and a sufficiently high positive voltage can SET the device.
The present embodiment provides a method and structure for forming resistive memory (RRAM) cells. For HfOx-based RRAM, changing resistance of HfOx relies on adding or extracting oxygen vacancies in HfOx.
In an embodiment herein, there is formed a RRAM cell with gradual changing Ti % (Ti % is the concentration of titanium) in a TiN (titanium nitride) electrode. Generally, the principles herein are applicable to RRAM cells having a metal-nitride material electrode and gradually changing the metal concentration. In the case of a TiN material electrode, different titanium (Ti) concentrations in the electrode results in different concentration of oxygen vacancy in the corresponding section of the RRAM. The total resistance of the inventive RRAM is equivalent to multiple RRAM with different concentration of oxygen vacancy (thus different resistance change as a response to number of pulses or voltage).
In an embodiment, a semiconductor manufacturing method provides a first step of depositing a TiN bottom electrode with gradually changing Ti %, patterning the TiN bottom electrode, and then forming HfOx on TiN sidewalls so that different height of HfOx butting different Ti % sections of TiN bottom electrode.
A resistive memory cell formed according to a first embodiment is shown in
Different Ti concentrations in the first electrode 270 results in a different concentration of oxygen vacancy in the corresponding section of the RRAM cell. The total resistance of the formed RRAM is equivalent to multiple RRAM in parallel with different concentration of oxygen vacancy (and thus a different resistance change as a response to number of applied pulses or voltage).
Such an RRAM can be used for some applications (e.g., analog computing or neuromorphic applications) in which it is desired to have a gradual change of RRAM resistance instead of simple binary resistance (High resistance/Low resistance) states.
As conceptually depicted in
G
total
=G
1
+G
2
+ . . . +G
n
In view of the first embodiment of
During a RESET operation, the conductance “G” will not drop sharply due to the different Ti % (oxygen vacancy concentration and thus different RESET characteristics).
Initially, there is provided a semiconductor substrate 505, e.g., at a front-end-of-the-line (FEOL) level, that includes one or more semiconductor devices (not shown) formed on a surface of a semiconductor substrate. The one or more semiconductor devices can include, but are not limited to, transistors, resistors, isolation structures, contacts, and/or diodes. The FEOL level can be formed utilizing techniques that are well known to those skilled in the art.
In other embodiments of the present application, substrate 505 is a lower back-end-of-the (BEOL) level that includes one or more electrically conductive structures that are embedded in one or more interconnect dielectric materials. In such an embodiment, a FEOL level is typically located beneath the lower interconnect level.
Semiconductor substrate 505 includes a bulk semiconductor substrate that may include a semiconductor material or a stack of semiconductor materials such as, for example, Si, Ge, SiGe, SiC, SiGeC, Ge alloys, GaAs, InAs, InP as well as other III/V or II/VI compound semiconductors. In one embodiment, the bulk semiconductor substrate includes a single crystalline semiconductor material such as, for example, single crystalline silicon. The thickness of the bulk semiconductor substrate can be from 30 μm to about 2 mm, although lesser and greater thicknesses can also be employed. The bulk semiconductor substrate may be doped with dopants of p-type or n-type. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. Examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium. “N-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. Examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. The dopant concentration in the bulk semiconductor substrate can range from 1×1014 atoms/cm3 to 3×1017 atoms/cm3.
Alternatively, a semiconductor-on-insulator substrate can be used in place of the bulk semiconductor substrate shown in
After providing the semiconductor substrate as described above, a bottom electrode material layer 510 is formed on the surface of the semiconductor substrate. In an embodiment, electrode material layer 510 serving as a bottom electrode of a RRAM memory device can be oriented in a horizontal direction. Each electrode material layer (e.g., electrode material layers 510) is composed of first electrode material such as, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W) or tungsten nitride (WN) or other materials including, but not limited to: tantalum carbide (TaC), titanium carbide (TiC), and titanium aluminum carbide (TiAlC). For the exemplary embodiment depicted in
The electrode material layer 510 can be formed utilizing a deposition process including, for example, CVD, PECVD, atomic layer deposition (ALD), sputtering or plating. In an embodiment, the percent concentration of Ti increases per time unit as the TiN layer 510 is grown in the vertical direction. When formed, the bottom electrode material layer 510 can have a thickness (i.e., height) ranging from between 30 nm to 300 nm, more preferably between 50 nm to 200 nm, and most preferably between 60 nm to 100 nm, although greater and lesser thicknesses are contemplated.
In an embodiment, to achieve the gradual changing of the metal, e.g., Ti of the TiN material, in an example CVD process, TiN films can be deposited in a reaction chamber by thermally decomposing tetrakis-dimethyl-amino-titanium (TDMAT) precursor in an nitrogen (N2) ambient. The various Ti % can be achieved by gradually tuning the gas flow ratio between TDMAT and N2. In one embodiment, the bottom (first) electrode material layer 510 is formed vertically is processed to achieve a changing concentration Ti % varying from 15% (atomic concentration) to 85%, and more preferably, from 30% to 70%.
For the case of a TaN bottom electrode 510 formed vertically, the process achieves a changing Ta % concentration varying from 25% to 75%.
The bottom electrode serves dual purposes (1) being an electrode and (2) an oxygen scavenging layer, meaning it has interaction with the dielectric layer (e.g., HfOx) to produce oxygen vacancies at the interface between the bottom electrode and HfOx.
In an embodiment, formed above the bottom electrode 510 is a hardmask layer 515. This hardmask layer 515 may be composed of SiN, though other suitable hardmask dielectric materials such as silicon carbide (SiC), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), fluorine-doped silicon oxide (SiO:F), silicon-carbon-nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicoboron carbonitride (SiBCN), silicon oxycabonitride (SiOCN), silicon oxide, and combinations thereof, can be used. The hardmask layer 515 may be formed utilizing a deposition process including, for example, CVD, PECVD, ALD, PVD, sputtering, chemical solution deposition or plating. The hardmask layer 515 may have a thickness from 20 nm to 100 nm; other thicknesses are possible and can be used in the present application as the thickness of the hardmask layer.
In embodiments, the RRAM cell dielectric middle layer 540, 541 can be comprised of a high k gate dielectric. The term “high k” when referring to dielectric layer 540, 541 denotes any transition metal oxide material such as, HfOx, TiOx, NiOx, WOx, TaOx, VOx, CuOx, etc., and can be deposited by atomic layer deposition (ALD) processes or other suitable processes or any suitable combination of multiple processes, including but not limited to, thermal oxidation, chemical oxidation, thermal nitridation, plasma oxidation, plasma nitridation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), and other like deposition processes. etc. In some embodiments, the HfOx dielectric material layer is a conformal layer. By “conformal layer” it is meant that the thickness of the layer is substantially the same (i.e., ±10%) on all surfaces, or that the variation is less than 15% of the nominal thickness. In one embodiment, the hafnium oxide dielectric layer 540, 541 has a thickness ranging from 2 nm to 20 nm, although more preferably between 3 nm to 10 nm and even 4 nm to 6 nm—although less thickness and greater thickness are also possible.
In
In an embodiment, the top electrode 550 can include a material, including but not limited to, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), platinum (Pt), or any other suitable conductive material. The metal contact can further include a barrier layer. The barrier layer can be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbon nitride (WCN), or combinations thereof. In various embodiments, the barrier layer can be deposited in a trench(es) by ALD, CVD, MOCVD, PECVD, or combinations thereof. In various embodiments, the metal fill can be formed by ALD, CVD, PVD, and/or plating, to form the electrical contacts.
With respect to the forming of the top electrode 550, there is additionally patterning step to pattern the top electrode. Patterning can be performed by any suitable patterning techniques, including but not limited to, lithography followed by etching (e.g., reactive ion etch), sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned multiple patterning (SAMP), etc.
In an embodiment, the hardmask layer 510 can be removed prior to depositing the dielectric layer 540. If it is removed, a mini RRAM is formed between the top surface of the bottom electrode and the top electrode. In this case, the mini-RRAM has a uniform Ti % bottom electrode.
The RRAM cell structure 700 of
Formed between each successive metal-nitride material layer is an insulator layer 704, e.g., of an insulating material to prevent any potential metal material (e.g., Ti) interaction between adjacent RRAM portions. In an embodiment, each insulator layer is a metal nitride insulator such as SiN, although other insulators can be inserted between the adjacent sections of the varying Ti % bottom electrode 770.
Formed transverse to each bottom electrode layer 702A, 702B, 702C and connecting each bottom electrode layer sidewall of the bottom electrode stack 770 is a middle layer 771 of a resistive switching dielectric material, e.g., a transition metal oxide such HfO2. Formed above the middle layer 771 is a second (top) electrode 772 of a uniform metal-nitride concentration (e.g., TiN). In an embodiment, the second (top) electrode 772 layer is a nitride-rich concentration. It is understood that, in the second embodiment, the memory cell can be configured oppositely, e.g., the bottom metal-nitride electrode (e.g., TiN layer) having a uniform concentration and the top electrode TiN layer having multiple sections that form a gradually changing Ti concentration.
As different Ti concentrations in the first bottom electrode 770 sections result in a different concentration of oxygen vacancy in the corresponding section of the RRAM cell, as shown in the RRAM bottom electrode structure 770, each TiN material layer having varying Ti % exhibits varying oxygen vacancy. That is, as shown in
Given that the different Ti concentrations in the first bottom electrode stack structure 770 results in a different concentration of oxygen vacancy in the corresponding layers 702A, 702B, 702C of the RRAM cell, the total resistance of the formed RRAM is equivalent to multiple RRAM in parallel with different concentration of oxygen vacancy (and thus a different resistance change as a response to number of applied pulses or voltage) as shown in the equivalent conductance circuit configuration of
Each bottom electrode alternating layer serves dual purposes of: (1) being an electrode and (2) an oxygen scavenging layer, meaning it has interaction with the dielectric layer (e.g., HfOx) to produce oxygen vacancies at the interface between the bottom electrode and HfOx.
Such an RRAM can be used for some applications (e.g., analog computing or neuromorphic applications) in which it is desired to have a gradual change of RRAM resistance instead of simple binary resistance (High resistance/Low resistance) states.
The material stack 800, which is present on substrate 801, is formed in the BEOL. As mentioned above, the material stack 800 is composed of alternating layers of bottom electrode material (e.g., bottom metal-nitride electrode material layers 802, 804, 806 each layer with corresponding increased metal material concentration) and hardmask dielectric material layers (e.g., dielectric material layers 803, 805). In the present application, the number of bottom electrode material layers and dielectric hardmask material layers of the material stack 800 can vary so long as each hardmask insulating material layer is sandwiched between successive bottom electrode material layers. In the second embodiment depicted, a top insulating material layer 807 is formed above the topmost bottom electrode material layer 806.
Each hardmask insulating material layer can be composed of a dielectric material such as, for example, silicon nitride, however, can be any other suitable dielectric material, including but not limited to: silicon carbide (SiC), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), fluorine-doped silicon oxide (SiO:F), silicon-carbon-nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicoboron carbonitride (SiBCN), silicon oxycabonitride (SiOCN), silicon oxide, and combinations thereof. Each hardmask layer 803, 805, 807 may have a thickness from 20 nm to 100 nm although other thicknesses are possible and can be used in the present application as the thickness of the hardmask layers.
Each bottom electrode material layer (e.g., electrode material layers 802, 804, 806) is composed of first electrode material such as, for example, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), platinum (Pt), or any other suitable conductive material. The metal contact can further include a barrier layer. The barrier layer can be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbon nitride (WCN), or combinations thereof. For the exemplary second embodiment depicted in
Each bottom electrode material layer 802, 804, 806 can be formed utilizing a deposition process including, for example, CVD, PECVD, atomic layer deposition (ALD), sputtering or plating. In an embodiment, the percent concentration of Ti increases per time unit as each TiN layer 802, 804, 806 is grown in the vertical direction. When formed, each individual bottom electrode material layer 802, 804, 806 can have a thickness (height) ranging from between 5 nm to 60 nm, more preferably between 10 nm to 30 nm, and most preferably 20 nm to 30 nm. Each TiN electrode material layer 802, 804, 806 can have the same thickness or different thicknesses.
In embodiments, the RRAM cell dielectric middle layer 840, 841 can be comprised of a high k gate dielectric. The term “high k” when referring to dielectric layer 540, 541 denotes any transition metal oxide material such as, HfOx, TiOx, NiOx, WOx, TaOx, VOx, CuOx, etc., and can be deposited by atomic layer deposition (ALD) processes or other suitable processes or any suitable combination of multiple processes, including but not limited to, thermal oxidation, chemical oxidation, thermal nitridation, plasma oxidation, plasma nitridation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), and other like deposition processes. etc. In some embodiments, the HfOx dielectric material layer 840, 841 is a conformal layer having a thickness ranging from 2 nm to 20 nm, although more preferably between 3 nm to 10 nm and even 4 nm to 6 nm—although less thickness and greater thickness are also possible.
In
In an embodiment, the top electrode 850 can include a material, including but not limited to, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), platinum (Pt), or any other suitable conductive material. The metal contact can further include a barrier layer. The barrier layer can be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbon nitride (WCN), or combinations thereof. In various embodiments, the barrier layer can be deposited in a trench(es) by ALD, CVD, MOCVD, PECVD, or combinations thereof. In various embodiments, the metal fill can be formed by ALD, CVD, PVD, and/or plating, to form the electrical contacts.
The RRAM array embodiments depicted in
While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
