Patent Application
20230317680
Embodiments described herein generally relate electronic devices, such as semiconductor devices. Some specific embodiments described relate to signal shielding technologies.
In operation, wire bond connections may carry high speed data signals. As device sizes continually shrink, and data speeds continually increase, challenges such as adjacent wire bond crosstalk become more pronounced. It is desirable to reduce negative effects such as adjacent wire bond crosstalk and electromagnetic interference (EMI). Configurations described below address these, and other technical challenges related to wire bond connections.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
A first channel substrate terminal 214A and a second channel substrate terminal 214B are shown. A number of wire bond connections 220 are shown coupled from the dies 210 to the channel substrate terminals 214A, 214B. In the example shown, the number of wire bond connections 220 include two separate rows of wire bond connections 220 from two adjacent dies in the offset stack going to respective channel substrate terminals 214A, 214B. The invention is not, however, limited to any one channel configuration or to offset dies, or to multiple die stacks.
In operation, wire bond connections 220 may carry high speed data signals. As device sizes continually shrink, and data speeds continually increase, challenges such as adjacent wire bond crosstalk become more pronounced. It is desirable to reduce negative effects such as adjacent wire bond crosstalk.
A ribbon bond connection can be oriented a number of ways. In one orientation, a width dimension is generally parallel to a major plane of the substrate 202. This orientation can be defined as a horizontal ribbon bond. In another orientation, the width dimension can lie within a plane that is orthogonal to the major plane of the substrate 202. This orientation can be defined as a vertical ribbon bond. In one example, a ribbon bond connection may include some portions along a ribbon bond length that are horizontal, and some portions that are vertical. In one example, it is useful from a manufacturing standpoint to attach a ribbon bond connection to a surface such as a substrate 202 or a die 210 in a horizontal orientation, then to twist, or otherwise reorient a middle portion of a ribbon bond connection.
As noted above,
In one example, one or more vertical ribbon bond connections 222 are coupled to ground voltage and serve as shielding structures. Other voltages apart from ground are also within the scope of the invention. In the example shown, a vertical ribbon bond connection 222 is located between at least two wire bond connections 220. In one example, one or more vertical ribbon bond connections 222 are interspersed within a row of wire bond connections 220 from a die 210 to the substrate 202. In one example, a vertical ribbon bond connections 222 is interspersed as alternating between every wire bond connection 220 from the die 210 to the substrate 202. As shown in
The presence of the vertical ribbon bond connection 222 at ground voltage provides at least some shielding effect, and reduces crosstalk noise, and/or provides some electromagnetic interference (EMI) protection. Because the vertical ribbon bond connection 222 is flat and vertical, it provides a greater shielding effect than if it were a single wire with a round cross section.
A first channel substrate terminal 614A and a second channel substrate terminal 614B are shown. Multiple rows of wire bond connections 620, 622, 624, 626 are shown coupled from multiple dies 610 in the stack of offset semiconductor dies to the substrate to the channel substrate terminals 614A, 614B.
In one example, the at least one row of ribbon bond connections 627 are coupled to ground voltage at terminal 623 and serve as shielding structures. Other voltages apart from ground are also within the scope of the invention. In one example, the inclusion of at least one row of ribbon bond connections 627 provides at least some shielding effect, and reduces crosstalk noise, and/or provides some electromagnetic interference (EMI) protection. Because the row of ribbon bond connections 627 is flat and horizontal, it provides a greater shielding effect from above and below than if it were a single wire with a round cross section.
In one example, at least one row of wire bond connections (620, 622, 624, 626) is bounded by a row of ribbon bond connections from above and below. For example, at least one row of wire bond connections (one or more of 620, 622) is bounded by the row of ribbon bond connections 627 from above and by the second row of ribbon bond connections 628 from below.
In one example, a row of ribbon bond connections vertically separates two rows of the multiple rows of wire bond connections. For example, in
In one embodiment, processor 810 has one or more processor cores 812 and 812N, where 812N represents the Nth processor core inside processor 810 where N is a positive integer. In one embodiment, system 800 includes multiple processors including 810 and 805, where processor 805 has logic similar or identical to the logic of processor 810. In some embodiments, processing core 812 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 810 has a cache memory 816 to cache instructions and/or data for system 800. Cache memory 816 may be organized into a hierarchal structure including one or more levels of cache memory.
In some embodiments, processor 810 includes a memory controller 814, which is operable to perform functions that enable the processor 810 to access and communicate with memory 830 that includes a volatile memory 832 and/or a non-volatile memory 834. In some embodiments, processor 810 is coupled with memory 830 and chipset 820. Processor 810 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna 878 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
In some embodiments, volatile memory 832 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 834 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
Memory 830 stores information and instructions to be executed by processor 810. In one embodiment, memory 830 may also store temporary variables or other intermediate information while processor 810 is executing instructions. In the illustrated embodiment, chipset 820 connects with processor 810 via Point-to-Point (PtP or P-P) interfaces 817 and 822. Chipset 820 enables processor 810 to connect to other elements in system 800. In some embodiments of the example system, interfaces 817 and 822 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
In some embodiments, chipset 820 is operable to communicate with processor 810, 805N, display device 840, and other devices, including a bus bridge 872, a smart TV 876, I/O devices 874, nonvolatile memory 860, a storage medium (such as one or more mass storage devices) 862, a keyboard/mouse 864, a network interface 866, and various forms of consumer electronics 877 (such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset 820 couples with these devices through an interface 824. Chipset 820 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.
Chipset 820 connects to display device 840 via interface 826. Display 840 may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor 810 and chipset 820 are merged into a single SOC. In addition, chipset 820 connects to one or more buses 850 and 855 that interconnect various system elements, such as I/O devices 874, nonvolatile memory 860, storage medium 862, a keyboard/mouse 864, and network interface 866. Buses 850 and 855 may be interconnected together via a bus bridge 872.
In one embodiment, mass storage device 862 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 866 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
While the modules shown in
To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:
Example 1 includes an electronic device. The electronic device includes a semiconductor die coupled to a substrate, one or more wire bond connections from the semiconductor die to the substrate, and one or more vertical ribbon bond connections from the semiconductor die to the substrate, wherein at least a portion of the one or more vertical ribbon bond connections is oriented with a ribbon plane orthogonal to a major plane of the substrate.
Example 2 includes the electronic device of example 1, wherein the one or more vertical ribbon bond connections is coupled to a ground voltage when in operation.
Example 3 includes the electronic device of any one of examples 1-2, wherein the one or more vertical ribbon bond connections includes a twist to translate a portion of the vertical ribbon bond connection from horizontal to vertical.
Example 4 includes the electronic device of any one of examples 1-3, wherein the one or more vertical ribbon bond connections are interspersed within a row of wire bond connections from the semiconductor die to the substrate.
Example 5 includes the electronic device of any one of examples 1-4, wherein vertical ribbon bond connections are included alternating between data signal wires within a row of wire bond connections from the semiconductor die to the substrate.
Example 6 includes the electronic device of any one of examples 1-5, wherein the semiconductor die includes a memory die.
Example 7 includes the electronic device of any one of examples 1-6, wherein the semiconductor die is a memory die included within a stack of memory dies.
Example 8 includes the electronic device of any one of examples 1-7, wherein vertical ribbon bond connections are included alternating between data signal wires within multiple rows of wire bond connections between different level dies in the stack of memory dies and the substrate.
Example 9 includes an electronic device. The electronic device includes a stack of offset semiconductor dies coupled to a substrate, multiple rows of wire bond connections from multiple dies in the stack of offset semiconductor dies to the substrate, and a row of ribbon bond connections from a die in the stack of offset semiconductor dies to the substrate, wherein the row of ribbon bond connections is vertically adjacent to at least one row of wire bond connections from the multiple rows of wire bond connections.
Example 10 includes the electronic device of example 9, wherein the row of ribbon bond connections is between two different channels in the stack of offset semiconductor dies.
Example 11 includes the electronic device of any one of examples 9-10, wherein the row of ribbon bond connections is coupled to a ground voltage when in operation.
Example 12 includes the electronic device of any one of examples 9-11, wherein the row of ribbon bond connections vertically separates two rows of the multiple rows of wire bond connections.
Example 13 includes the electronic device of any one of examples 9-12, wherein two or more cascades of ribbon bond connections are electrically coupled together, and vertically separate two rows of the multiple rows of wire bond connections.
Example 14 includes the electronic device of any one of examples 9-13, further including one or more vertical ribbon bond connections from the semiconductor die to the substrate, wherein at least a portion of the one or more vertical ribbon bond connections is oriented with a ribbon plane orthogonal to a major plane of the substrate.
Example 15 includes the electronic device of any one of examples 9-14, wherein the vertical ribbon bond connection is on an edge of at least one row of wire bond connections from the multiple rows of wire bond connections.
Example 16 includes the electronic device of any one of examples 9-15, wherein at least one row of wire bond connections from the multiple rows of wire bond connections is bounded by a row of ribbon bond connections from above and below, and wherein the at least one row of wire bond connections from the multiple rows of wire bond connections is bounded on sides by vertical ribbon bond connections.
Example 17 includes a method that includes attaching a first end of a bond ribbon to a first surface, twisting the bond ribbon to orient a ribbon plane orthogonal to a major plane of the first surface to form a vertical bond ribbon, extending a length of the vertical bond ribbon to a second surface, twisting the bond ribbon to orient the ribbon plane parallel to a major plane of the second surface, and attaching a second end of the bond ribbon to the second surface.
Example 18 includes the method of example 17, further including coupling the vertical bond ribbon to a ground voltage when in operation.
Example 19 includes the method of any one of examples 17-18, further including coupling the vertical bond ribbon laterally between two data signal bond wires.
Example 20 includes the method of any one of examples 17-19, further including coupling the vertical bond ribbon at a lateral edge of a row of wire bond connections, the row of wire bond connections coupled between a die and a substrate.
Example 21 includes the method of any one of examples 17-20, further including coupling a row of ribbon bond connections vertically adjacent to the row of wire bond connections.
Example 22 includes an electronic device. The electronic device includes a semiconductor die coupled to a substrate, two data wire bond connections from the semiconductor die to the substrate, and a ground voltage vertical group of wire bond connections from the semiconductor die to the substrate, wherein the vertical group of wire bond connections both lie in a vertical plane that is oriented orthogonal to a major plane of the substrate, and wherein the vertical group of wire bond connections is between the two data wire bond connections.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single disclosure or inventive concept if more than one is, in fact, disclosed.
The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
As used herein, the term “or” may be construed in either an inclusive or exclusive sense. Moreover, plural instances may be provided for resources, operations, or structures described herein as a single instance. Additionally, boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in a context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within a scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configurations may be implemented as a combined structure or resource. Similarly, structures and functionality presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within a scope of embodiments of the present disclosure as represented by the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
The foregoing description, for the purpose of explanation, has been described with reference to specific example embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The example embodiments were chosen and described in order to best explain the principles involved and their practical applications, to thereby enable others skilled in the art to best utilize the various example embodiments with various modifications as are suited to the particular use contemplated.
It will also be understood that, although the terms “first,” “second,” and so forth may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the present example embodiments. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used in the description of the example embodiments herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used in the description of the example embodiments and the appended examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context.
