This description relates generally to semiconductor device fabrication, and more particularly to a selective epitaxy to create a double-diffused channel over planar or underlying topography.
In metal-oxide-semiconductor (MOS) transistors generally, a control voltage applied to a gate changes the conductivity of a channel between a source and a drain, thus modulating current flow through the channel. The shorter the length of the channel, the higher the transconductance of the MOS field effect transistor (MOSFET), and thus the higher the voltage gain and power gain of the MOS transistor. As source-drain separation decreases, patterning expense increases and fabrication variation becomes problematic because of the quantization effects of atomic layers.
In a double-diffused MOS (DMOS) transistor, a double-diffused channel is formed, and its channel length is specified by a difference in a lateral extent of impurity profiles of first and second dopants having different diffusion characteristics. For example, a DMOS transistor can have both a faster-diffusing p-type dopant (e.g., boron, gallium, or indium) and a slower-diffusing n-type dopant (e.g., phosphorus, arsenic, or antimony) implanted and subsequently diffused (e.g., upon anneal) into a silicon transistor body (e.g., through a single mask opening or against a single gate edge). The p-type dopant diffuses more in all directions into the transistor body than the n-type dopant, which provides simultaneous formation of (n+) source and (p) channel regions with a short channel length (e.g., less than about one micrometer) without needing to use small-dimension lithographic masks to pattern source and drain regions that are very close together. Double-diffused channels thus address increased fabrication cost and physical drawbacks associated with pattern-based channel length reduction. DMOS transistors are useful in amplifiers such as microwave power amplifiers, RF power amplifiers, and audio power amplifiers.
An example method of manufacturing a semiconductor device includes forming a gate on a semiconductor layer of a substrate. A hard mask is formed over the gate and the semiconductor layer to expose a portion of the semiconductor layer. The exposed portion of the semiconductor layer is isotropically etched away to form a recess having a depth. A first selective epitaxial growth of a first semiconductor material doped with a first dopant is performed on the semiconductor layer in the recess. A second selective epitaxial growth of a second semiconductor material doped with a second dopant is performed on the first semiconductor material in the recess. The hard mask is then removed.
An example integrated circuit includes a semiconductor device that includes a semiconductor layer of a substrate and a gate disposed over the semiconductor layer. The semiconductor layer has a recess adjacent and partially under the gate. A first region, disposed in the recess partially under the gate, is of a first selectively epitaxially grown semiconductor material doped with a first dopant. A second region, disposed in the recess over the first semiconductor material and partially under the gate, is of a second selectively epitaxially grown semiconductor material doped with a second dopant. The first and second regions form a double-diffused channel of the semiconductor device.
An example method of fabricating an integrated circuit that includes a fin-based lateral double-diffused metal-oxide-semiconductor (LDMOS) field effect transistor includes forming, over a corrugated region of the transistor, a gate with a first hard mask layer thereover. A second hard mask is deposited over the gate and the corrugated region, and is then etched back to selectively expose a portion of the corrugated region. Silicon of the exposed portion of the corrugated region, is isotropically etched to a depth. A first selective epitaxial growth of silicon doped with boron at a concentration of between about 1×1017 ions/cm2 and about 1×1019 ions/cm2 is performed on the etched exposed portion of the corrugated region. A second selective epitaxial growth of silicon doped with arsenic at a concentration of between about 1×1019 ions/cm2 and about 1×1021 ions/cm2 is performed on the silicon doped with boron. The second hard mask, and the first hard mask layer over the gate, are then removed.
A method includes the use of selective epitaxy to create a double-diffused channel over planar or underlying topography, for example, in a folded transistor such as a fin-based lateral double-diffused metal-oxide-semiconductor (LDMOS) field effect transistor. In a folded transistor, a channel of the transistor is provided on the transistor as a corrugated structure of alternating semiconductor trenches and semiconductor fins. The corrugated trench-fin structure increases the effective area of the channel within the available surface area of an integrated circuit on which the transistor is fabricated. The curvatures of the surfaces of the trenches and fins, along with the relative depths of the trenches as compared to the tops of the fins, can present a difficulty in providing uniform doping of the tops and sidewalls of the fins and the bottom surfaces of the trenches between fins using directed-beam implantation techniques. Because the slope of the curvature of a fin can vary over a fin's surface in the direction of the rise and fall of the fin, a dopant ion implantation beam aimed at the surface of the integrated circuit at an implantation angle that is normal to one portion of a fin's surface may not be normal to other portions of the fin's surface. Fins may also shadow surfaces of other fins during beam implantation. Consequently, the use of directed-beam implantation to dope the trench and fin surfaces may result in the provided dopant concentration not being uniform over the surface of the fin and inside a trench between neighboring fins. The lack of uniform doping over the surfaces of fins and trenches in a folded transistor can result in the transistor having a double-diffused channel of undesirably or inoperatively non-uniform concentrations of the faster-diffusing and/or slower-diffusing channel dopants.
Methods described herein can be used to fabricate an integrated circuit that includes an active semiconductor device, such as a transistor (e.g., a folded transistor), a voltage source, a current source, or a diode. The methods can include doping of the surfaces of trenches and fins made uniform by using selective epitaxy to grow the differential-doped portions of a channel of the active semiconductor device. The methods can also be used to fabricate planar devices (e.g., planar transistors) that do not have a folded structure.
An example of the fabrication method 100 is shown broadly in the flow diagram of
The second hard mask can be formed, for example, of iARC, silicon dioxide, silicon nitride, or silicon oxynitride. In examples in which the transistor is a folded transistor having a corrugated fin-and-trench structures of semiconductor material between long finger-like gate structures, of which an example is illustrated in
After the second hard mask deposition and etch-back at 104, portions of the semiconductor material on the surface of the transistor are left exposed and are not coated by the second hard mask. The exposed portion of the semiconductor material is then isotropically etched at 106 to a depth. The etch 106 can be implemented, for example, as a liquid-phase etch (e.g., using an aqueous solution), a gas-phase etch (e.g., in an epitaxial growth reactor using chlorine gas), or an etch using an isotopic plasma (e.g., in a reduced-pressure plasma process in a diode reactor).
When the transistor is, for example, a folded transistor, the etch 106 has the effect of eroding the exposed surface(s) of the fins and trenches, without eroding semiconductor material that is coated by the second hard mask, or the gate, which is also coated by the second hard mask. In selected locations on the surface of the folded transistor where the second hard mask has been removed during the second hard mask etch-back at 104, and thus where the isotropic etch 106 is performed, the depth of the isotropic etch 106 is approximately uniform over the exposed portion of the transistor surface. The isotropic etch 106 thus forms a recess within the exposed portion of the substrate semiconductor layer. For example, the recess has a volume and follows the contours of trenches and fins of the folded transistor. As a result, the surfaces of the trenches and fins are eroded approximately uniformly by the isotropic etch 106. The depth to which the isotropic etch 106 is performed can be, for example, about equal to the sum of thicknesses of first and second epitaxial growths 108, 110 performed subsequent to the etch 106. In some examples, the etch 106 can be to a depth of between about 20 nanometers and about 200 nanometers, e.g., between about 50 nanometers and about 150 nanometers. The isotropic nature of the etch 106 has the benefit that it removes surface semiconductor material equally on all exposed surface faces of the transistor, and undercuts the edge of the gate and its coating of the second hard mask.
At 108, a first selective epitaxial growth is performed with semiconductor material (e.g., silicon) in-situ doped with a first dopant (e.g., boron, gallium, or indium). This first selective epitaxial growth can form a body region of the transistor. At 110, a second selective epitaxial growth 110 is performed with semiconductor material (e.g., silicon) in-situ doped with a second dopant (e.g., phosphorus, arsenic, or antimony) over of the semiconductor material doped with the first dopant created by the first selective epitaxial growth 108. This second selective epitaxial growth can form a source region of the transistor. The first and selective epitaxial growths 108, 110 can each form a respective material growth to a respective depth to fill the recess between about 30 percent and about 70 percent (e.g., about 50 percent) of the depth of etch 106, e.g., each of the first and second epitaxial growths 108, 110 can respectively fill to a depth of between about 10 nanometers and about 140 nanometers, e.g., between about 20 nanometers and about 130 nanometers, e.g., between about 40 nanometers and about 120 nanometers. In some examples, the semiconductor material includes silicon, the first dopant includes boron, and the second dopant includes arsenic. The selectiveness of the first and second epitaxial growths 108, 110 has the benefit that it precludes the deposition of an amorphous or polysilicon layer on the non-etched areas (the areas of the surface that are coated by hard mask). In other examples, a non-selective deposition could be performed, in which the amorphous or polysilicon layer is removed by floating off the hard mask.
In some examples, the dopant concentration of boron can be between about 1×1017 ions/cm2 and about 1×1019 ions/cm2, e.g., about 1×1018 ions/cm2. In some examples, the dopant concentration of arsenic can be between about 1×1019 ions/cm2 and about 1×1021 ions/cm2, e.g., about 1×1020 ions/cm2. For example, the first dopant can be boron with a dopant concentration of about 1×1018 ions/cm2 and the second dopant can be arsenic with a dopant concentration of about 1×1020 ions/cm2. By way of example, etch 106 can be performed to a depth of about 100 nanometers, first selective epitaxial growth 108 can form boron-doped silicon to a depth of between about 30 nanometers and about 70 nanometers, and second selective epitaxial growth 110 can form arsenic-doped silicon to a depth of between about 70 nanometers and about 30 nanometers over the boron-doped silicon. In some examples, the first and second selective epitaxial growths 108, 110 re-fill about the entirety of the isotropically etched depth.
The first and second epitaxial growths 108, 110 with in-situ doping of first and second dopants, respectively, can also include, in some examples, doping with germanium and/or carbon to provide specific transistor device performance properties. For example, germanium allows the inclusion of higher levels of boron by reducing strain, which potentially allows the channel (the body region between source and drift regions) to be made very short. Carbon retards the diffusion of boron. The selective epitaxial growths 108, 110 can be performed using gas-phase or vapor-phase processes, with the uniformity of doping being provided by reaction kinetics, or using atomic layer deposition (ALD) to form extremely uniform reacted layers of deposited precursors. The epitaxial growth processes 108, 110 can grow material at different crystal orientations and can be controlled so as to achieve comparable growth rates on different crystal facets. The selective epitaxial growths 108, 110 can be performed at lower temperature and, in some examples, reduced pressure as compared to any blanket (flat, non-selective) epitaxial growth processes performed near the substrate and/or around a buried layer. The second hard mask formed by deposition and etch 104 is then removed with another etch 112.
The cross-sectional diagrams of
In some examples, the first and second semiconductor materials 214, 216 of the first and second selectively epitaxial growths include silicon, the first dopant includes boron, and the second dopant includes arsenic. In some examples, the dopant concentration of arsenic is between about 1×1019 ions/cm2 and about 1×1021 ions/cm2, e.g., about 1×1020 ions/cm2. For example, the first dopant can be boron with a dopant concentration of about 1×1018 ions/cm2 and the second dopant can be arsenic with a dopant concentration of about 1×1020 ions/cm2. In the selected locations on the surface of the transistor where the hard mask 204 is not present and thus where the first selective epitaxial growth is performed, the second selective epitaxial growth can fill about the remainder of the eroded depth 210 with the second selectively epitaxially grown semiconductor material doped with the second dopant 216.
The three-dimensional sectional diagrams of
The three-dimensional view of
The structure of the folded transistor of
The semiconductor material of the folded transistor may have a first conductivity type (e.g., p-type). The semiconductor material can have an average resistivity of between about 10 ohm-cm and about 100 ohm-cm, for example. First conductivity type dopants can be introduced into substrate semiconductor material of the transistor to provide a desired threshold voltage for the folded transistor. The folded transistor can have a channel of a second conductivity type different from the first conductivity type (e.g., making it an n-channel transistor in the case of a p-type semiconductor material). Examples of p-type dopants include boron, gallium, and indium. Examples of n-type dopants include phosphorus, arsenic, and antimony. Opposite-type versions (e.g., p-channel versions) of the folded transistor can be formed by appropriate changes in polarities of dopants. The trenches of the folded transistor can be formed by a reactive ion etch (RIE) process using, for example, fluorine radicals, and can have an average depth of, for example, between about 400 nanometers and about 1200 nanometers.
The conformal doping methods of the present application use sequential epitaxial depositions that can be selective based on process kinetics to control channel doping and to make channel doping isotropic to follow device contours. The conformal doping methods of the present application can be used in both planar and folded transistor device structures. In folded transistors, the methods of the present application provide uniform doping of top and sidewall surfaces of semiconductor fins and bottom trench surfaces between fins. The conformal doping methods of the present application thus permit for highly uniform, very deep doping of fins and trenches, using existing semiconductor device implantation tools. The conformal doping methods of the present application provide the ability to increase the doping density of the transistor body to withstand punch-through and maintain high carrier mobility, even as channel length is precisely scaled. The doping of the three-dimensional facets of fin and trench structures can be made uniform, with equal concentration of dopants provided on top, bottom and side surfaces of fins. For LDMOS transistors, the conformal doping methods of the present application allow creation of a channel region with an equal threshold voltage for all fin surfaces. The use of epitaxy thus allows creation of very short, steep, and potentially graded junctions with improved transition time, resistance, punch-through leakage, and capacitance. The conformal doping methods of the present application allow for the increase of conductivity of the channel region for the same wafer layout area. The sequential epitaxial methods described herein can create a double-diffused transistor body without creating source/drain extensions formed by beam implantation. The conformal doping methods of the present application facilitate design of LDMOS devices with low specific on-resistance Rsp. Specific on-resistance Rsp is a figure of merit for MOS transistors equal to the product of the drain-source on-resistance RDs(on) (the total resistance between the drain and source when the MOS transistor is on) and the area of the MOS transistor.
In this description, the term “based on” means based at least in part on. Also, in this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device, element, or component couples to a second device, element, or component, that coupling may be through a direct coupling or through an indirect coupling via other devices, elements, or components and connections. Similarly, a device, element, or component that is coupled between a first component or location and a second component or location may be through a direct connection or through an indirect connection via other devices, elements, or components and/or couplings. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.