Patent Application
20070056925
1. Field of the Invention
The invention relates to semiconductor devices. More specifically, the invention relates to semiconductor devices with a layer of a high dielectric constant material.
2. Description of the Related Art
Since, flash memory is widely used in portable electronic devices, such as laptop computers, mobile phones, PDAs, etc, the demand to reduce operation voltage, so as to reduce energy consumption has been ever increasing.
An ONO (oxide nitride oxide) layer has been used in flash memory device gate stack for memory storage. However, the dielectric constant of ONO is not enough to meet the ever increasing demand in operation voltage, so high dielectric constant material (or referred as to high k material) has been introduced to replace ONO.
The dielectric constant of SiO2 is about 3.9. If high k material like Al2O3 is used to replace SiO2, the dielectric constant will increase to around 9.0. Other than Al2O3, HfO2, Ta2O3 are also considered as the candidates for high k materials in flash memory gate stack to replace ONO. Among them, Al2O3, HfO2 and Al2O3/HfO2/Al2O3 sandwich structure have been used.
Etching of high k material has been found to be more difficult compared to etching ONO, because of lower volatility of its etch byproduct. Because of this, the etch rate, and the its selectivity to polysilicon film has been found to be much lower compared to ONO film. Efforts have been made to increase the etch rate and selectivity of high k material to polysilicon.
To achieve the foregoing and in accordance with the purpose of the present invention, a method for selectively etching a high k layer with respect a silicon based material is provided. The high k layer over a silicon based layer is placed into an etch chamber. An etchant gas is provided into the etch chamber, wherein the etchant gas comprises H2. A plasma is generated from the etchant gas to selectively etch the high k layer with respect to the silicon based material.
In another manifestation of the invention, a method for etching a stack with a high k layer over a silicon based layer is provided. The stack is placed into an etch chamber. The high k layer is selectively etched with respect to the silicon based layer. The selective etching comprises providing a high k layer etchant gas into the etch chamber, wherein the high k layer etchant gas comprises H2 and generating a plasma from the high k layer etchant gas to selectively etch the high k layer with respect to the silicon based layer
In another manifestation of the invention, an apparatus for forming flash memory with a high k dielectric layer over a silicon based layer is provided. A plasma processing chamber, comprising a chamber wall forming a plasma processing chamber enclosure, a substrate support for supporting a substrate within the plasma processing chamber enclosure, a pressure regulator for regulating the pressure in the plasma processing chamber enclosure, at least one electrode for providing power to the plasma processing chamber enclosure for sustaining a plasma, a gas inlet for providing gas into the plasma processing chamber enclosure, and a gas outlet for exhausting gas from the plasma processing chamber enclosure is provided. A gas source is in fluid connection with the gas inlet and comprises an H2 gas source, a BCl3 gas source, and a Cl2 gas source. A controller is controllably connected to the gas source and the at least one electrode and comprises at least one processor and computer readable media. The computer readable media comprises computer readable code for selectively etching the high k layer with respect to the silicon based layer, computer readable code to stop the selectively etching the high k layer with respect to the silicon based layer, and computer readable code for selectively etching the silicon based layer with respect to the high k layer. The computer readable code for selectively etching the high k layer with respect to the silicon based layer comprises computer readable code for providing H2 from the H2 gas source, computer readable code for providing BCl3 from the BCl3 gas source, computer readable code for providing Cl2 from the Cl2 gas source, and computer readable code for generating a plasma from the H2, BCl3, and Cl2 to selectively etch the high k layer with respect to the silicon based layer.
These and other features of the present invention will be described in more details below in the detailed description of the invention and in conjunction with the following figures.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
To facilitate understanding,
In the specification and claims, a high dielectric constant material has a dielectric constant of at least 8 (K≧8).
A poly-silicon layer 312 is then formed over the high k layer 304 (step 208). A patterned mask 316, such as a photoresist mask is placed over the poly-silicon layer 312 (step 212). An antireflective coating 314 may be between the patterned mask 316 and the poly-silicon layer 312, to facilitate the formation of the patterned mask 316. The poly-silicon layer 312 is then etched through the mask (step 216).
The high k layer 304 is then etched using an H2 addition (step 220), as shown in
An ion implantation is performed (step 224) to create the source and drain regions.
U.S. Pat. No. 6,511,872, by Donnelly, Jr. et al., issued Jan. 28, 2003 discloses a method of etching a high dielectric constant layer over a substrate. An etch chemistry of BCl3 and Cl2 is disclosed. However, a process with a high etch selectivity of the high k dielectric layer to substrate is not disclosed. The article “Etching of high-k dielectric Zr1-xAlxOy films in chlorine-containing plasmas” by K. Pelhos et al., published in the Journal of Vacuum Science Technology A 19(4) July/August 2001 pp. 1361-1366 discusses the same etch chemistry and also does not disclose a process with a high etch selectivity.
The article “Plasma Etching Selectivity of ZrO2 to Si in BCl3/Cl2 Plasmas,” by Lin Sha and Jane P. Chang, in the Journal of Vacuum Science Technology A 21(6) July/August 2001 pp. 1915-1922 discloses a method of etching a high dielectric constant layer over a substrate. An etchant chemistry of BCl3, Cl2 and 5% Ar is disclosed. This article states that the highest etch selectivity of 1.5 was reached by using pure BCl3. It is desirable to have higher etch selectivities to minimize the etching of the substrate.
In a preferred embodiment of the invention, the high dielectric constant layer may be formed from a material with a dielectric constant of at least 8, such as Hf silicate (K≅11), HfO2 (K≅25-30), Zr silicate (K≅11-13), ZrO2 (K≅22-28), Al2O3 (K≅8-12)), La2O3 (K≅25-30), SrTiO3 (K≅200), SrZrO3 (K≅25), TiO2 (K≅80), and Y2O3 (K≅8-15), which are oxides. More preferably, the high dielectric constant layer is a binary metal oxide.
A gate oxide layer is formed (step 608).
A floating gate etch is performed (step 616) to etch the first polysilicon layer 716, to the form as shown in
A mask is formed over the second polysilicon layer (step 628).
The interpoly dielectric layer 712 is etch using an H2 addition (step 636), as shown in
Example of High k Dielectric Etch
In an example of the high k dielectric etch, during the high k layer etch using an H2 addition (steps 220 and 636), the wafer is placed in an etch chamber. The etch chamber may be used for etching the poly-silicon layer (step 216) or a different chamber may be used to for etching the poly-silicon layer.
Attached to system bus 820 is a wide variety of subsystems. Processor(s) 822 (also referred to as central processing units or CPUs) are coupled to storage devices, including memory 824. Memory 824 includes random access memory (RAM) and read-only memory (ROM). As is well known in the art, ROM acts to transfer data and instructions uni-directionally to the CPU and RAM is used typically to transfer data and instructions in a bi-directional manner. Both of these types of memories may include any suitable of the computer-readable media described below. A fixed disk 826 is also coupled bi-directionally to CPU 822; it provides additional data storage capacity and may also include any of the computer-readable media described below.
Fixed disk 826 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 826 may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 824. Removable disk 814 may take the form of any of the computer-readable media described below.
CPU 822 is also coupled to a variety of input/output devices, such as display 804, keyboard 810, mouse 812, and speakers 830. In general, an input/output device may be any of video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers. CPU 822 optionally may be coupled to another computer or telecommunications network using network interface 840. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely upon CPU 822 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
In addition, embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
An etchant gas of BCl3, and inert diluent, Cl2, and an H2 addition is provided from the gas source 410 to the area of the plasma volume. The inert diluent may be any inert gas such as neon, argon, or xenon. More preferably, the inert diluent is argon. Therefore, the gas source 410 may comprise a BCl3 source 412, a Cl2 source 414, an H2 source 415, and an argon source 416. The controller 435 is able to control the flow rate of the various gases.
In this example, the etchant gas the etchant gas consists essentially of BCl3, Cl2, Ar, CxHy, and H2. Preferably the total gas flow is 5-1,000 sccm, where the ratio by volume of Cl2 to BCl3 is 0-2:1, the ratio by volume of H2 to BCl3 is 0.2-5:1, and the ratio by volume of CxHy to BCl3 is 0-0.5:1, and the flow of the Ar or another inert gas is between 0-500 sccm. The etch was done with about 200% over etch and the polysilicon loss after this is about 100 A. The thickness of high k material is about 250 A, so 200% over etch is equivalent to 500 A of high k dielectric etch. Based on above, the high k to polysilicon etch selectivity is estimated at about 5.
In this example, the high k dielectric is Al2O3 is over a polysilicon. The gas source 410 provides an etchant gas comprising BCl3, argon, Cl2, and an H2 addition to the process chamber. During the etch, the wafer is maintained at a temperature between 20°-80° C. Although other methods may require a high temperature, which requires heating, to provide a selective etch, the invention may be performed without heating the wafer, which prevents thermal damage to the wafer. In addition, the lower temperatures create less problems than methods that require that the wafer is heated. The controller 435 controls the exhaust pump 448 and gas source 410 to control the chamber pressure. The chamber pressure is maintained between 2-20 mTorr, during the etch.
A D.C. bias may be applied to the lower electrode. Preferably, the absolute value of the D.C. bias is between 0-300 volts. Most preferably, the absolute value of the D.C. bias is less than 50 volts. Preferably, the upper RF source provides a power of 200-1400 Watts (TCP) through the coil 404 to the etch chamber at a frequency of about 13.56 MHz. As a result, a plasma density of 109-1011 ions/cm3 is provided.
The effect of inert gas addition is to increase of the sputtering so that no residue is formed during the etch. Another effect of inert gas dilution is to improve etch rate uniformity.
The ratio of BCl3 to Cl2 allows Cl2 to clean up deposits from the BCl3, which prevents the formation of footers in a tapered etch, without significantly sacrificing selectivity.
Without wishing to be bound by theory, it is also believed that the use of a lower chamber pressure and high TCP cause high dissociation of BCl3 and BCl2+. It is further believed that the more further dissociated species provides the desired etching.
The H2 addition is believed to both increase the Al2O3 etch rate and decrease the polysilicon etch rate. Without being bound by theory, it is believed that the H2 addition facilitates the dissociation of Al2O3 into Al3+ and O2− to increase the etch rate of the high k dielectric. In addition, the H2 forms passivation on the polysilicon surface to decrease the etch rate of the polysilicon.
Experiments with the inventive H2 addition have been found to increase the Al2O3 to polysilicon selectivity to be greater than 3:1, more preferably greater than 5:1. One experiment found a selectivity of 48.7:1.
Experiments with the inventive H2 addition have been found to increase etch rate of between 50-200 Å/minute. More preferably, the inventive high constant layer etch is able to provide and etch rate of between 100-1000 Å/minute. In one experiment an etch rate of 696 Å/minute of the high k dielectric was achieved. Experiments have found that the H2 addition provided a 7% increase in Al2O3 and a 50% increase in selectivity. The selectivity increase with H2 addition is expected even more if VDC is low.
The invention also unexpectedly provides good etch uniformity. The invention provides a selective etch of a high k dielectric with respect to a silicon based material. Preferably, the silicon based material is at least one of silicon, such as crystalline silicon and polysilicon, and silicon nitride. More preferably, the silicon based material is silicon, such as crystalline silicon on polysilicon. A low selectivity has been found for silicon oxide. Preferably, the high k dielectric is binary metal oxide.
While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, modifications, and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, modifications, and various substitute equivalents as fall within the true spirit and scope of the present invention.
