The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a polysilicon gate electrode and fabrication process thereof.
MOS transistors are used extensively in semiconductor integrated circuit devices.
For improvement of operational speed of MOS transistors, decrease of gate length is effective, and thus, efforts are being made for miniaturization of MOS transistors. As a result, ultrafine MOS transistors having a gate length of less than 60 nm are realized these days.
In order to attain the desired high speed operation, in other words, large current drivability and suppress short channel effect at the same time with such ultrafine MOS transistors, it is important to reduce the film thickness of gate insulation film in accordance with so-called scaling law.
More specifically, the density of carriers induced in the channel region of a MOS transistor is proportional to a gate capacitance, while the gate capacitance is in inverse proportion to the film thickness of the gate insulation film. Thus, it is possible to increase the current drivability of the MOS transistor by reducing the film thickness of the gate insulation film.
Further, it should be noted that the electric field induced by the gate electrode right underneath thereof is distributed between the gate insulation film and the depletion layer formed in the channel region right underneath the gate insulation film. Thus, by reducing the film thickness of the gate insulation film, the electric field applied to the depletion layer is increased and it becomes possible to suppress the short channel effect effectively.
On the other hand, when the film thickness of the gate insulation film is reduced as such, there arise new problems such as deterioration of reliability of the gate insulation film.
More specifically, in the case such thin gate insulation film is used, there tends to occur the problem that impurity element introduced into the gate electrode as dopant penetrates through the gate insulation film and invades into the channel. When invasion of impurity element into to such a channel region is caused, there occurs the problem of deterioration of TDDB (time-dependent dielectric breakdown) characteristics.
Further, in the case the film thickness of the gate insulation film is reduced to 10 nm or less, the effect of depletion layer extending upward with minute distance in the gate electrode from the interface to the gate insulation film becomes no longer ignorable, and there occurs increase of effective film thickness of the gate insulation film. As a result, there occurs decrease of density of carriers induced in the channel region, resulting in decrease of current drivability of the MOS transistor.
Japanese Laid-Open Patent Application 2001-068662 official gazette
Japanese Laid-Open Patent Application 06-244136 official gazette
Here, the construction of the MOS transistor of a related art of the present invention and the fabrication process thereof will be explained for the case of n-channel MOS transistor with reference to
Referring to
Further, a polysilicon film is deposited on the entire surface of the silicon substrate 41 by a CVD process so as to cover the insulation film 44 with a thickness of 100 nm, and P (phosphor) is introduced as the dopant impurity element by an ion implantation process under an acceleration energy of 10 keV with a dose of 6×1015 cm−2. Further, by patterning the polysilicon film thus obtained, there is formed a polysilicon gate electrode pattern 45 with a gate length of 60 nm.
Furthermore, P or As (arsenic) is introduced into the silicon substrate 41 by an ion implantation process while using the polysilicon gate electrode pattern 45 as a mask. With this, a pair of n-type extension diffusion regions 46 are formed in the p-type well 43 at respective sides of the gate electrode 45.
Further, a pair of sidewall insulation films 47 are formed at respective sides of the gate electrode pattern 45, and P or As ions are introduced by an ion implantation process while using the gate electrode pattern 45 and the sidewall insulation films as a mask. With this, there are formed n+-type diffusion regions 48 in the device region 43 at respective outer sides of the sidewall insulation films as the source and drain regions of the p-channel MOS transistor.
Furthermore, a rapid thermal annealing process (RTA) is applied to the structure thus introduced with the impurities element by the ion implantation process at the temperature of 1000° C. for activation of the injected impurity element.
Finally, a silicide layer 49 is formed on the polysilicon gate electrode pattern 45 and on the surface of the n+-type diffusion region 48 by a salicide process.
Referring to
It should be noted that the grain diameter of such columnar Si crystal grains changes depending on the film thickness of the polysilicon film thus formed as shown in
Meanwhile, it has been discovered, in the investigation made on the TDDB characteristics for the MOS transistors having the polysilicon gate electrode 45 on the gate insulation film 44, that there occurs improvement of TDDB characteristics in the case the grain diameter of the Si crystal grains is suppressed in the polysilicon gate electrode pattern 45. This effect appears particularly conspicuously in the case of an n-channel MOS transistor in which the polysilicon gate electrode pattern 45 is doped with P.
Thus, it can be seen that, in order to improve the TDDB characteristics of MOS transistors, it is effective to decrease the film thickness of the polysilicon gate electrode pattern 45.
However, with the polysilicon gate electrode pattern 45 of reduced film thickness, there arises a problem that the gate insulation film vital to operation of MOS transistor is affected at the time of formation of the silicide layer 49. Further, taking into consideration the fact that the silicide layer 49 on the gate electrode pattern 45 is formed at the same time to the silicide layer 49 on the source/drain region 48, it is difficult to simply reduce the film thickness of the polysilicon gate electrode pattern 45. More specifically, it should be noted that the distance between the silicide layer 49 on the source/drain region 48 and the silicide layer 49 on the gate electrode pattern 45 separated with each other by the sidewall insulation film 47 is reduced when the thickness of the gate electrode pattern 45 is reduced, while this tends to lead to the risk of causing short circuit therebetween.
Contrary to this, there is a technology in a related art of the present invention shown in
With the structure of
Thus, the technology of
Meanwhile, Patent Reference 1 describes a technology of forming a thin amorphous silicon film on a gate insulation film, crystallizing the same to form a polysilicon film of Si crystal grains of small grain diameter, forming a thick polysilicon film further thereon with a larger crystal grain diameter, and conduct ion implantation process of an impurity element into the polysilicon film of the dual layer structure thus obtained.
Further, Patent Reference 2 describes a technology of obtaining a polysilicon electrode film of relaxed stress in the form of a polysilicon film of small grain diameter, by repeating the process of depositing a thin doped amorphous silicon film and causing crystallization therein.
In the technology of Patent Reference 1, however, there arises a problem noted below in relation to the selection of ion implantation energy.
Referring to
In this case, the atoms of P thus introduced do not reach the lower part of the upper polysilicon film 53 as shown in
Thus, as a result of the thermal annealing process applied to such a structure, the amorphous state part 54 undergoes crystallization as shown in
On the other hand, the impurity element caused diffusion from the impurity injection region 54 does not reach the lower polysilicon film 52 or only very small amount of the impurity element reaches the lower polysilicon film 52, and thus, it is not possible to introduce the n-type impurity element into the lower polysilicon film 52 with satisfactory concentration.
In the case the polysilicon film of the multilayer structure such as the one shown in
However, with such a construction, there is a tendency that depletion takes place in the polysilicon gate electrode when a gate voltage is applied thereto in view of the low impurity concentration level of the polysilicon gate electrode particularly at the lower part thereof. Thereby, there is caused increase of the effective film thickness in the gate electrode, and this results in decrease of the current drivability of the transistor.
On the other hand, in the case the ion implantation process is conducted to a deep level with large energy in the structure of
With such a polysilicon film 58, it is not possible to suppress the diffusion of the impurity element into the channel region.
On the other hand, with the method of Patent Reference 2, it is certainly possible to avoid the problem of gate depletion and the problem of deterioration of the TDDB characteristics caused by coarse grain texture of the polysilicon gate electrode, while there is imposed a constraint on the elements usable for the impurity element in view of the fact that the gate electrode is formed in the state in which the impurity element is doped. Thereby, there arises a problem that it is difficult to fabricate a semiconductor integrated circuit device having both a p-type gate electrode and an n-type gate electrode such as a CMOS device, or the like. When to form a p-type gate electrode and an n-type gate electrode by using such so-called in-situ doped gate electrode, it is necessary to form these by separate film-forming processes. However, formation of the gate electrodes with different film-forming processes is not realistic in dual-gate devices such as a CMOS device.
It is an object of the present invention to provide a semiconductor device and fabrication process thereof in which it is possible to improve the TDDB characteristics while suppressing depletion of the polysilicon gate electrode at the same time.
Another object of the present invention is to provide a semiconductor device and fabrication process thereof wherein it is possible to suppress short channel effect without complicating the fabrication process thereof.
In a first aspect, the present invention provides a semiconductor device, comprising:
a substrate;
a device isolation structure formed on said substrate, said device isolation structure defining a first device region of a first conductivity type and a second device region of a second conductivity type on said substrate;
a first polycrystalline semiconductor gate electrode structure formed in said first device region via a gate insulation film, said first polycrystalline semiconductor gate electrode structure having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, said first polycrystalline gate electrode structure being doped to said second conductivity type;
a second polycrystalline semiconductor gate electrode structure formed in said second device region via a gate insulation film, said second polycrystalline semiconductor gate electrode structure having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, said second polycrystalline gate electrode structure being doped to said first conductivity type;
a pair of diffusion regions of said second conductivity type formed in said first device region at respective lateral sides of said first gate electrode structure; and
a pair of diffusion regions of said first conductivity type formed in said second device region at respective lateral sides of said second gate electrode structure,
wherein, in each of said first and second polycrystalline semiconductor gate electrode structures, said lower polycrystalline semiconductor layer includes semiconductor crystal grains of a grain diameter smaller than semiconductor crystal grains forming said upper polycrystalline semiconductor layer,
in each of said first and second polycrystalline semiconductor gate electrode structures, said lower polycrystalline semiconductor layer has a dopant concentration level equal to or higher than a dopant concentration level of said upper polycrystalline semiconductor layer.
In another aspect, the present invention provides a semiconductor device, comprising:
a substrate;
a device isolation structure formed on said substrate, said device isolation structure defining a first device region of a first conductivity type and a second device region of a second conductivity type on said substrate;
a first polycrystalline semiconductor gate electrode structure formed in said first device region via a gate insulation film, said first polycrystalline semiconductor gate electrode structure having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, said first polycrystalline semiconductor gate electrode structure being doped to said second conductivity type;
a second polycrystalline semiconductor gate electrode structure formed in said second device region via a gate insulation film, said second polycrystalline semiconductor gate electrode structure having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, said second polycrystalline semiconductor gate electrode structure being doped to said first conductivity type;
a pair of diffusion regions of said second conductivity type formed in said first device region at respective lateral sides of said first polycrystalline semiconductor gate electrode structure;
a pair of diffusion regions of said first conductivity type formed in said second device region at respective lateral sides of said second polycrystalline semiconductor gate electrode structure;
wherein, in each of said first and second polycrystalline semiconductor gate electrode structures, said lower polycrystalline semiconductor layer comprises semiconductor crystal grains of a grain size smaller than semiconductor crystal grains constituting said upper polycrystalline semiconductor layer,
in each of said first and second polycrystalline semiconductor gate electrode structures, said lower polycrystalline semiconductor layer has a dopant concentration of 1×1020 cm−3 or more.
Further, in another aspect, the present invention provides a semiconductor device, comprising:
a substrate;
a device isolation structure formed on said substrate, said device isolation structure defining a first device region of a first conductivity type and a second device region of a second conductivity type on said substrate;
a first polycrystalline semiconductor gate electrode structure formed in said first device region via a gate insulation film, said first polycrystalline semiconductor gate electrode structure having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, said first polycrystalline gate electrode structure being doped to said second conductivity type;
a second polycrystalline semiconductor gate electrode structure formed in said second device region via a gate insulation film, said second polycrystalline semiconductor gate electrode structure having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, said second polycrystalline gate electrode structure being doped to said first conductivity type;
a pair of diffusion regions of said second conductivity type formed in said first device region at respective lateral sides of said first polycrystalline semiconductor gate electrode structure; and
a pair of diffusion regions of said first conductivity type formed in said second device region at respective lateral sides of said second polycrystalline semiconductor gate electrode structure,
wherein, in each of said first and second polycrystalline semiconductor gate electrode structures, said lower polycrystalline semiconductor layer comprises semiconductor crystal grains of a grain diameter smaller than semiconductor crystal grains constituting said upper polycrystalline semiconductor layer,
wherein, in each of said first and second polycrystalline semiconductor gate electrode structures, said lower polycrystalline semiconductor layer has a smaller film thickness as compared with said upper polycrystalline semiconductor layer.
In another aspect, the present invention provides a method for fabricating a semiconductor device, comprising the steps of:
forming a first polycrystalline semiconductor film on a substrate via a gate insulation film;
doping said first polycrystalline semiconductor film with an impurity element of a first conductivity type by an ion implantation process;
forming a second polycrystalline semiconductor film over said first polycrystalline semiconductor film;
patterning said first and second polycrystalline semiconductor films to form a gate electrode structure in which said first and second polycrystalline semiconductor films are stacked; and
forming source and drain diffusion regions doped to said first conductivity type at respective lateral sides of said gate electrode structure and simultaneously doping said second polycrystalline semiconductor film in said gate electrode structure to said first conductivity type, by introducing an impurity element of a conductivity type identical to said first impurity element while using said gate electrode structure as a mask.
In another aspect, the present invention provides a method for fabricating a semiconductor device, comprising the steps of:
forming a first polycrystalline semiconductor film over a semiconductor substrate via a gate insulation film;
doping said first polycrystalline semiconductor film by an ion implantation process with an impurity element of a first conductivity type;
depositing a dummy gate pattern over said first polycrystalline semiconductor film;
forming a dummy gate pattern by patterning said first polycrystalline semiconductor film and a dummy insulation film thereon;
forming dummy sidewall insulation films on respective sidewall surfaces of said dummy gate pattern;
exposing said first polycrystalline semiconductor film by removing said dummy insulation film selectively with regard to said dummy sidewall insulation films;
forming source and drain regions over said semiconductor substrate by growing a semiconductor layer selectively at respective outer sides of said dummy sidewall insulation films and simultaneously forming a stacked gate electrode structure by selectively growing a second polycrystalline semiconductor layer over said first polycrystalline semiconductor layer; and
forming source and drain diffusion regions respectively in said source and drain regions by introducing an impurity element into said source by an ion implantation process and drain regions and simultaneously introducing said impurity element into said second polycrystalline semiconductor layer by an ion implantation process.
According to the present invention, it becomes possible to realize a semiconductor device suppressing depletion of polysilicon gate electrode and simultaneously suppressing deterioration of TDDB characteristics without complicating the fabrication process. According to such a semiconductor device, doping of the polysilicon gate electrode is achieved by ion implantation process, and thus, it is possible with the present invention to form a CMOS device, or the like, having polysilicon gates of different conductivity type, with simple process.
Further, according to the semiconductor device of the present invention, it is possible to form the source/drain regions on the semiconductor substrate such that the bottom edge of the source/drain regions is located near the surface of the silicon substrate by a regrowth process concurrently to the formation of the upper polysilicon layer of the polysilicon gate structure of multilayer construction and by doping the re-grown source/drain regions thus formed to the desired conductivity type by an ion implantation process. Thereby, it becomes possible to suppress the short channel effect effectively.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.
Referring to
Further, in the semiconductor substrate 1, there are formed source and drain extension regions 7a and 7b respectively in correspondence to a pair of mutually opposing sidewall surfaces of the polycrystalline semiconductor gate electrode 3, and there are formed source and drain regions 7A and 7B in continuation respectively to the source and drain extension regions 7a and 7b at the respective outer sides of the sidewall insulation films formed on the corresponding sidewall surfaces of the polycrystalline semiconductor gate electrode 3.
Further, on the surface of the source region 7A, there is formed a silicide layer 6S, while a silicide layer 6D is formed on the drain region 7B, and a silicide layer 6G is formed on the surface of the polysilicon gate electrode 3.
As shown in
With the semiconductor device of
Further, with the semiconductor device of
While such problem of gate depletion or deterioration of TDDB characteristics appears conspicuously in n-type semiconductor devices that use P for the dopant impurity element, the present invention is effective also in the case of p-type semiconductor devices that use B for the dopant element. Further, by doping such lower polycrystalline semiconductor layer 4 and the upper polycrystalline semiconductor layer 5 to p-type or n-type by an ion implantation process after formation thereof, it becomes possible to form dual gate semiconductor devices such as a CMOS device easily on a single semiconductor substrate.
Next, fabrication process of a CMOS device according to a first embodiment of the present invention will be explained with reference to
Referring to
Further, the resist pattern 14 is removed in the step of
Further, while using the silicon nitride film 13 and the thermal oxide film 12 as a stopper, the SiO2 film 12 on the silicon substrate 11 is removed by a CMP (chemical mechanical polishing) process, followed by removal of the silicon nitride film 13 and the SiO2 film 12 by etching. With this, a device isolation region 17 is formed.
Next, in the step of
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Further, in the step of
In the polysilicon film 23, while there is caused slight increase of grain diameter in the Si crystal grains constituting the film 23 as compared with the Si crystal grains in the polysilicon film 20, 90% or more, substantially 100% of the Si crystal grains have the grain diameter of 10-50 nm, which is generally equal to the film thickness of the polysilicon film 23, similarly to the case of the polysilicon film 20. It should be noted that such grain diameter distribution is confirmed by observing the vertical cross-section of the polysilicon film 23.
Further, in the step of
Next, in the step of
Further, in the device region 11B, a polysilicon gate electrode structure 24GB of the p-channel MOS transistor is formed on the device region 11B in the form of the stack of the polysilicon films 23B and 24B formed on the gate insulation film 19 and doped to the p-type. In the step of
Next, in the step of
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Further, in the step of
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Further, in the step of
Further, by forming an interlayer insulation film not illustrated and forming via contact structure and interconnection structure according to the needs, there is completed a CMOS device in which the n-channel MOS transistor and the p-channel MOS transistor are connected in series. Further, in the case of forming an upper level interconnection structure on the interlayer insulation film in the form of a multilayer interconnection structure by using a damascene process, there are conducted formation of interconnection trenches and via-holes after formation of the interlayer insulation film, and a Cu interconnection layer is formed so as to fill such interconnection trenches and the via-holes. Further, excessive Cu layer on the interlayer insulation film is removed by a CMP process. If more complex interconnection structure is desired, such a process may be repeated as necessary.
According to the semiconductor device of the present embodiment thus formed, it should be noted that the lower polysilicon film is introduced with the impurity element of the corresponding conductivity type in each of the stacked gate electrode structures 24GA and 24GB before the upper polysilicon film is formed with low acceleration energy and high impurity concentration level, and it becomes possible to effectively resolve the problem of depletion caused in the polysilicon gate. Further, in view of small film thickness of the lower polysilicon film, the present invention can suppress the crystal grain diameter to 50 nm or less in such a part, and it becomes possible to attain the improvement of TDDB characteristics at the same time.
Further, with such stacked gate electrode structures 24GA and 24GB, it becomes possible to secure sufficiently large film thickness for the gate electrode structure as a whole, and it becomes possible to carry out the silicide formation process without damaging the gate insulation film.
Thus, because the ion implantation process to the lower polysilicon film is conducted separately to the ion implantation process for the formation of source and drain regions as shown in
Because the undoped polysilicon film 34 is patterned with the patterning process of
Next, the fabrication process of a semiconductor device according to a second embodiment of the present invention will be described with reference to
Referring to
Next, in the step of
Next, in the step of
Incidentally, in the event the patterning of the stacked gate electrode pattern is conducted in the device region 11B not illustrated simultaneously to the patterning process of
Next, in the step of
Next, in the step of
Further, by applying a thermal annealing process to the structure of
Further, a Co film is deposited on the structure of
Further, by forming an interlayer insulation film not illustrated on the structure of
According to the semiconductor device of the present embodiment thus formed, too, it should be noted that the lower polysilicon film is introduced with the impurity element of the corresponding conductivity type in each of the stacked gate electrode structures 24GA and 24GB before the upper polysilicon film is formed with low acceleration energy and high impurity concentration level, and it becomes possible to effectively resolve the problem of depletion caused in the polysilicon gate. Further, in view of small film thickness of the lower polysilicon film, the present invention can suppress the crystal grain diameter to 50 nm or less in such a part, and it becomes possible to attain the improvement of TDDB characteristics at the same time.
Further, with such stacked gate electrode structure, it becomes possible to secure sufficiently large film thickness for the gate electrode structure as a whole, and it becomes possible to carry out the silicide formation process without damaging the gate insulation film.
Thus, because the ion implantation process to the upper polysilicon film is conducted separately to the ion implantation process for the formation of source and drain regions with the present embodiment, it becomes possible to guarantee sufficient impurity concentration level for the stacked polysilicon gate electrode structure when forming shallow junction at the source and drain regions by using reduced ion implantation energy for suppressing short channel effect, even when the thickness of the polysilicon film forming the upper part of the stacked polysilicon gate electrode structure is increased. Thus, it becomes possible to set the overall height of the stacked gate electrode structure a height sufficient for silicide formation.
In each of the embodiments described heretofore, it is also possible to use other n-type impurity elements such as As (arsenic) in place of P.
Because the problem of deterioration of TDDB characteristics appears conspicuously in n-channel MOS transistors, it is also possible to carry out the separated ion implantation processes to the lower polysilicon film 20 and to the upper polysilicon film 24A explained with reference to
Next, fabrication process of a semiconductor device according to a third embodiment of the present invention that suppresses short channel effect with reference to
In the explanation hereinafter, only n-channel MOS transistor will be explained similarly as before, while it should be noted that the explanation is applicable also to p-channel MOS transistors. Further, it is possible to construct a dual gate device such as a CMOS device, by combining the n-channel MOS transistor of the present embodiment with a p-channel MOS transistor formed by a similar process.
Referring to
Further, in the step of
The n-type polysilicon film 23A and the corresponding p-type polysilicon film thus formed have a film thickness of 10-50 nm and hence are formed by the Si crystal grains having the grain diameter of 10-50 nm.
Next, in the step of
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Similarly, the p-type polysilicon film corresponding to the n-type polysilicon film 23A and the surface of the silicon substrate 11 are exposed also in the device region 11B. The selective etching process of the dummy insulation film 24I can be conducted by a wet etching process that uses pyrophosphoric acid etchant.
Next, in the step of
Further, with such epitaxial growth of the silicon layer in the step of
Further, in the step of
Next, in the step of
Further, similar ion implantation process of p-type impurity element such as B is conducted into the device region 11B.
Next, in the step of
Similar crystallization and silicide formation are caused also in the device region 11B not illustrated, and as a result, there is formed a p-channel MOS transistor having epitaxial regions projecting upward from the silicon substrate surface similarly to the one shown in
As shown in
Thus, by setting the acceleration energy at the time of doping the source and drain regions 11e and 11f in the step of
Because the polysilicon film 24A of coarse grain structure is formed on the polysilicon film 23A of fine grain structure in the gate electrode structure with the present embodiment at the time of forming the epitaxial layers 11S and 11D, it becomes possible to attain improvement of the TDDB characteristics and suppression of depletion of the polysilicon gate electrode explained with previous embodiments simultaneously.
While it is possible with the present embodiment to form the source and drain extension regions 11a and 11b immediately after the formation of the dummy gate structure 24GAd of
Further, while the foregoing embodiments are described for the case of conducting the activation annealing process of the impurity elements introduced by the ion implantation by dedicated thermal annealing process, it is also possible to carry out such activation processing by using other processes that includes thermal annealing process. For example, it is possible to crystallize the lower polysilicon layer by utilizing the process of depositing the upper polysilicon layer.
Further, while the present embodiment has been explained for the case of the gate insulation film formed of an SiON film, the present invention is not limited to such a specific film and it is also possible to use an siO2 film or SiN film. Further, it is also possible to use a so-called high-K film such as a Ta2O5 film.
Further, the substrate 11 is not limited to a bulk silicon substrate but it is also possible to use an SOS substrate in which a silicon epitaxial layer is formed on a sapphire substrate or an SOI substrate in which a monocrystalline silicon layer in formed on a silicon substrate via an insulation film.
Further, in each of the foregoing embodiments, the substrate 11 is not limited to a silicon substrate but it is also possible to sue a SiGe mixed crystal substrate, an SiC mixed crystal substrate in which a small amount of C is added to Si, or even a SiGeC mixed crystal substrate.
In each of the foregoing embodiments, it is not necessary to form the layers constituting the gate electrode in the form of a polysilicon layer but it is also possible to form the same as an amorphous silicon layer.
Further, in each of the CMOS devices of the foregoing embodiments, the silicon layers constituting the gate electrode of the MOS transistor are not limited to polysilicon layers but it is also possible to form the gate electrode of some of the MOS transistors by a monocrystalline silicon layer.
Further, while it has been explained with the foregoing description that the gate electrode is formed of stack of polysilicon films, at least one of the lower and upper polysilicon films constituting the stacked gate electrode structure may contain Ge or C in addition to Si or both of Ge and C in addition to Si.
Further, in each of the foregoing embodiments, it is noted that the gate insulation film 19 is patterned simultaneously to the patterning process of the stacked gate electrode structures 26GA and 26GB in the step of
For example, it is possible to leave the gate insulation film 19 continuously on the surface of the silicon substrate in the case the gate insulation film 19 has a film thickness of 2 nm or more. In this case, the ion implantation process for forming the source extension region and the drain extension region is conducted through such remaining insulation film. On the other hand, in the case the gate insulation film 19 has a thickness of 2 nm or more and the gate insulation film 19 is not patterned spontaneously at the time of patterning the stacked gate electrode structure, it is also possible to intentionally pattern the gate insulation film 19.
While the present invention has been explained with regard to preferred embodiments, the present invention is by on means limited to such specific embodiments and various variations and modifications may be made without departing from the scope of the invention as set forth in patent claims.
According to the present invention, it becomes possible to realize a semiconductor device capable of suppressing depletion of polysilicon gate electrode and simultaneously capable of suppressing deterioration of TDDB characteristics without complicating the fabrication process. According to such a semiconductor device, doping of the polysilicon gate electrode is achieved by ion implantation process, and thus, it is possible with the present invention to form a CMOS device, or the like, having polysilicon gates of different conductivity type, with simple process.
Further, according to the semiconductor device of the present invention, it is possible to form the source/drain regions on the semiconductor substrate such that the bottom edge of the source/drain regions is located near the surface of the silicon substrate by a regrowth process concurrently to the formation of the upper polysilicon layer of the polysilicon gate structure of multilayer construction and by doping the re-grown source/drain regions thus formed to the desired conductivity type by an ion implantation process. Thereby, it becomes possible to suppress the short channel effect effectively.
Number | Date | Country | Kind |
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2004-367691 | Dec 2004 | JP | national |
The present invention is a continuation application filed under 35 U.S.C. 111(a) claiming benefit under 35 U.S.C. 120 and 365(c) of Japanese patent application 2004-367691 filed on Dec. 20, 2004 and PCT application JP2005/23055 filed on Dec. 15, 2005, the entire contents of each are incorporated herein as reference.
Number | Date | Country | |
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Parent | PCT/JP05/23055 | Dec 2005 | US |
Child | 11812516 | US |