This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2021-043775, filed on Mar. 17, 2021, the entire contents of which are incorporated herein by reference.
The embodiments of the present invention relate to a semiconductor device and manufacturing method thereof.
Some of semiconductor storage devices such as a NAND flash memory include a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. The number of stacked word lines in such a three-dimensional memory cell array has increased in recent years. Therefore, formation of a contact plug connected to each word line requires a contact hole with a high aspect ratio.
Such a contact hole with a high aspect ratio is formed in a tapered shape in which its upper portion is wider because an inner wall of the upper portion is etched to some extent, and the diameter is reduced toward the bottom portion. Therefore, the upper portion of the contact hole may come into contact with another structure unintentionally. This contact causes a failure such as short circuit between wires.
Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. In the embodiments, “an upper direction” or “a lower direction” refers to a relative direction when a direction perpendicular to a surface of a semiconductor substrate on which semiconductor elements are provided is assumed as “an upper direction”. Therefore, the term “upper direction” or “lower direction” occasionally differs from an upper direction or a lower direction based on a gravitational acceleration direction. In the present specification and the drawings, elements identical to those described in the foregoing drawings are denoted by like reference characters and detailed explanations thereof are omitted as appropriate.
A semiconductor device according to the present embodiment comprises a first electrode film. An interlayer dielectric film is provided on the first electrode film. A contact plug is provided in a contact hole that penetrates through the interlayer dielectric film and reaches the first electrode film. The contact plug includes a first metal film and a first conductive film configured to cover an inner wall of an upper portion of the contact hole. The contact plug includes a second metal film configured to cover the first conductive film on the inner wall of the upper portion of the contact hole and cover an inner wall of a lower portion of the contact hole. The contact plug includes a second conductive film configured to be filled inside the second metal film in the contact hole.
As illustrated in
The semiconductor storage device 100a includes a base portion 1, the stack 2, a deep slit ST (a plate-shaped portion 3), a shallow slit SHE (a plate-shaped portion 4), and a plurality of column portions CL.
The base portion 1 includes a substrate 10, an interlayer dielectric film 11, a conductive layer 12, and a semiconductor portion 13. The interlayer dielectric film 11 is provided on the substrate 10. The conductive layer 12 is provided on the interlayer dielectric film 11. The semiconductor portion 13 is provided on the conductive layer 12.
The substrate 10 is a semiconductor substrate, for example, a silicon substrate. The conductivity type of silicon (Si) is, for example, a p-type. An element isolation region 10i, for example, is provided in a surface region of the substrate 10. The element isolation region 10i is an insulating region that contains silicon oxide (SiO2), for example, and defines an active area AA in the surface region of the substrate 10. A source region and a drain region of a transistor Tr are provided in the active area AA. The transistor Tr forms a peripheral circuit (a CMOS (Complementary Metal Oxide Semiconductor) circuit) of the non-volatile memory. The CMOS circuit is provided below a built-in source layer BSL and on the substrate 10. The interlayer dielectric film 11 contains, for example, silicon oxide and insulates the transistor Tr. A wire 11a is provided in the interlayer dielectric film 11. A portion of the wire 11a is electrically connected to the transistor Tr. The conductive layer 12 contains conductive metal, for example, tungsten (W). The semiconductor portion 13 contains, for example, silicon. The conductivity type of silicon is, for example, an n-type. The semiconductor portion 13 may be formed by a plurality of layers, and a portion thereof may contain undoped silicon. Further, either the conductive layer 12 or the semiconductor portion 13 may be omitted.
The conductive layer 12 and the semiconductor portion 13 serve as a common source line of a memory cell array (2m in
The stack 2 is provided above the substrate 10 and is located in the Z-direction with respect to the conductive layer 12 and the semiconductor portion 13 (the built-in source layer BSL). The stack 2 is configured by a plurality of electrode films 21 and a plurality of insulation layers 22 alternately stacked along the Z-direction. The electrode films 21 contain conductive metal, for example, tungsten. The insulation layers 22 contain silicon oxide, for example. The insulation layers 22 insulate the electrode films 21 from each other. The number of each of the stacked electrode films 21 and the stacked insulation layers 22 may be any number. The insulation layer 22 may be an air gap, for example. An insulation film 2g, for example, is provided between the stack 2 and the semiconductor portion 13. The insulation film 2g contains silicon oxide, for example. The insulation film 2g may contain a high dielectric material having a higher relative permittivity than silicon oxide. The high dielectric material may be metal oxide, for example.
The electrode films 21 include at least one source-side selection gate SGS, a plurality of word lines WL, and at least one drain-side selection gate SGD. The source-side selection gate SGS is a gate electrode of a source-side selection transistor STS. The word lines WL serve as gate electrodes of memory cells MC. The drain-side selection gate SGD is a gate electrode of a drain-side selection transistor STD. The source-side selection gate SGS is provided in a lower region of the stack 2. The drain-side selection gate SGD is provided in an upper region of the stack 2. The lower region is a region of the stack 2 closer to the base portion 1, and the upper region is a region of the stack 2 farther from the base portion 1. The word lines WL are provided between the source-side selection gate SGS and the drain-side selection gate SGD.
The thickness in the Z-direction of one of the insulation layers 22 which insulates the source-side selection gate SGS and the word line WL from each other may be larger than the thickness in the Z-direction of the insulation layer 22 that insulates the word lines WL from each other, for example. Further, a cover insulation film (not illustrated) may be provided on the uppermost insulation layer 22 that is the farthest from the base portion 1. The cover insulation film contains silicon oxide, for example.
The semiconductor storage device 100a includes the memory cells MC connected in series between the source-side selection transistor STS and the drain-side selection transistor STD. The configuration in which the source-side selection transistor STS, the memory cells MC, and the drain-side selection transistor STD are connected in series is called “memory string” or “NAND string”. The memory string is connected to bit lines BL, for example, via contacts Cb. The bit lines BL are provided above the stack 2 and extend in the Y-direction.
The deep slits ST and the shallow slits SHE are provided in the stack 2. The deep slits ST extend in the X-direction, and are provided in the stack 2 while penetrating through the stack 2 from an upper end of the stack 2 to the base portion 1. The plate-shaped portion 3 is a wire provided in the deep slit ST (
As illustrated in
A portion of the stack 2 sandwiched between the two plate-shaped portions 3 illustrated in
As illustrated in
As illustrated in
The shape of the semiconductor body 210 is tubular with a bottom, for example. The semiconductor body 210 contains silicon, for example. This silicon is polysilicon obtained by crystallizing amorphous silicon, for example. The semiconductor body 210 is made of, for example, undoped silicon. Also, the semiconductor body 210 may be made of, for example, p-type silicon. The semiconductor body 210 serves as a channel of each of the drain-side selection transistor STD, the memory cell MC, and the source-side selection transistor STS.
A portion of the memory film 220, other than the block insulation film 21a, is provided between an inner wall of the memory hole MH and the semiconductor body 210. The shape of the memory film 220 is tubular, for example. The memory cells MC each include a storage region between the semiconductor body 210 and the electrode film 21 that serves as the word line WL, and are stacked in the Z-direction. The memory film 220 includes a cover insulation film 221, a charge trapping film 222, and a tunnel insulation film 223, for example. The semiconductor body 210, the charge trapping film 222, and the tunnel insulation film 223 extend in the Z-direction.
The cover insulation film 221 is provided between the insulation layer 22 and the charge trapping film 222. The cover insulation film 221 contains silicon oxide, for example. The cover insulation film 221 protects the charge trapping film 222 from being etched when a sacrifice film (not illustrated) is replaced with the electrode film 21 (in a replacement process). The cover insulation film 221 may be removed from between the electrode film 21 and the memory film 220 in the replacement process. In this case, the block insulation film 21a, for example, is provided between the electrode film 21 and the charge trapping film 222, as illustrated in
The charge trapping film 222 is provided between the block insulation film 21a and the cover insulation film 221, and the tunnel insulation film 223. The charge trapping film 222 contains silicon nitride, for example, and includes trap sites therein which trap electric charges. A portion of the charge trapping film 222, sandwiched between the electrode film 21 that serves as the word line WL and the semiconductor body 210, configures a storage region of the memory cell MC as a charge trapping portion. A threshold voltage of the memory cell MC is changed depending on whether any electric charge is present in the charge trapping portion or in accordance with the amount of electric charges trapped in the charge trapping portion. Accordingly, the memory cell MC retains information.
The tunnel insulation film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulation film 223 contains silicon oxide, or contains silicon oxide and silicon nitride, for example. The tunnel insulation film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, electrons and holes each pass (tunnel) through the potential barrier formed by the tunnel insulation film 223, when electrons are injected from the semiconductor body 210 to the charge trapping portion (in a write operation) and when holes are injected from the semiconductor body 210 to the charge trapping portion (in an erase operation).
The core layer 230 is embedded in the space within the tubular semiconductor body 210. The shape of the core layer 230 is columnar, for example. The core layer 230 contains silicon oxide, for example, and is insulative.
Each of the column portions CL is provided in the memory hole MH provided in the stack 2. The memory hole MH penetrates through the stack 2 from the upper end of the stack 2 along a stacking direction of the stack 2 (the Z-direction) and extends in the stack 2 and in the semiconductor portion 13. Each of the column portion portions CL includes the semiconductor body 210 as a semiconductor column, the memory film 220, and the core layer 230 as illustrated in
A tap region Tap and a step region SSA are provided in the step portion 2s other than the memory cell array 2m. The tap region Tap is provided in the block BLK that is adjacent to the step region SSA in the Y-direction with the deep slit ST arranged therebetween. The tap region Tap may be provided between cell regions in the X-direction. The step region SSA may be also provided between the cell regions in the X-direction. The step region SSA is a region where a plurality of contact plugs CC are provided. The step region SSA may include a bridge region electrically connecting the word lines WL in the blocks BLK that are adjacent to each other in the X-direction with the step region SSA arranged therebetween. The tap region Tap is a region where contact plugs C4 are provided. The contact plugs CC and C4 extend in the Z-direction, for example. Each contact plug CC is electrically connected to, for example, the electrode film 21 (that is, the word line WL). The contact plug C4 is electrically connected to, for example, the wire 11a for power supply to the transistor Tr or the like. Low-resistance metal such as copper or tungsten is used for the contact plugs CC and C4. The shallow slits SHE extend in the memory cell array 2m in the X-direction and electrically isolate the drain-side selection gate SGD in every finger.
A plurality of insulator columns HR are provided around the contact plug CC. Each insulator column HR is provided in a hole provided in the stack 2. The insulator column HR penetrates through the stack 2 from the upper end of the stack 2 along the Z-direction and is provided in the stack 2 and in the semiconductor portion 13. An insulator such as a silicon oxide film is used for the insulator column HR. Each insulator column HR may have the same configuration as the column portion CL. The insulator columns HR are provided in the tap region Tap and the step region SSA, for example. The insulator columns HR serve as support members for keeping gaps formed in the step region and the tap region when a sacrifice film (not illustrated) is replaced with the electrode film 21 (in a replacement process). The insulator column HR has a larger diameter (the width in the X-direction or the Y-direction) than the column portion CL.
The contact plug CC penetrates through the interlayer dielectric film 24 from its top surface to its bottom surface and is electrically connected to a first electrode film 21 (the word line WL). The interlayer dielectric film 24 is provided on the electrode film 21 (the word line WL) in the step portion 2s and electrically insulates the electrode film 21 and a wiring layer (for example, the bit line BL) on the interlayer dielectric film 24 from each other.
The contact plug CC is provided in the contact hole CH that penetrates through the interlayer dielectric film 24 and reaches the electrode film 21. The contact plug CC includes a barrier metal BM1 as a first metal film, a contact material CM1 as a first conductive film, a barrier metal BM2 as a second metal film, and a contact material CM2 as a second conductive film.
The barrier metal BM1 covers the inner wall of the upper portion of the contact hole CH, but does not cover the inner wall of the lower portion of the contact hole CH. That is, the barrier metal BM1 ends between the inner wall of the upper portion and the inner wall of the lower portion of the contact hole CH, and does not continue to the lower portion of the contact hole CH. A metal material containing at least one of titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), and tungsten (W), for example, is used for the barrier metal BM1. The barrier metal BM1 is deposited under a poor-coverage condition by plasma CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or the like, in which a process gas is reduced. By this deposition, the barrier metal BM1 is formed only on the inner wall of the upper portion of the contact hole CH which is close to an opening end (an upper end), and is hardly formed below that portion. The barrier metal BM1 covers the inner wall of the upper portion of the contact hole CH over the entire inner circumference.
The contact material CM1 covers the barrier metal BM1 on the inner wall of the upper portion of the contact hole CH, but does not cover the inner wall of the lower portion of the contact hole CH. That is, the contact material CM1 also ends between the inner wall of the upper portion and the inner wall of the lower portion of the contact hole CH, and does not continue to the lower portion of the contact hole CH. A metal material containing at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), and titanium (Ti), for example, is used for the contact material CM1. The contact material CM1 is a film formed by selective growth on the barrier metal BM1. Accordingly, the contact material CM1 is selectively formed on the barrier metal BM1. The contact material CM1 is formed on the inner wall of the upper portion of the contact hole CH close to the opening end (the upper end), and is hardly formed below that portion, that is, on the inner wall of the lower portion of the contact hole CH close to a lower end, as with the barrier metal BM1. The contact material CM1 covers the inner wall of the upper portion of the contact hole CH over the entire inner circumference.
The barrier metal BM2 covers the contact material CM1 on the inner wall of the upper portion of the contact hole CH, and also covers the inner wall of the lower portion of the contact hole CH. That is, the barrier metal BM2 continues from the inner wall of the upper portion to the inner wall of the lower portion of the contact hole CH, and covers the entire inner wall of the contact hole CH. A metal material containing at least one of titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), and tungsten (W), for example, is used for the barrier metal BM2, as with the barrier metal BM1. The barrier metals BM1 and BM2 may be made of the same material as each other or different materials from each other. The barrier metal BM2 is deposited under a superior-coverage condition by CVD or the like in which the flow rate of a process gas is sufficient. By this deposition, the barrier metal BM2 is formed from the opening end (the upper end) of the contact hole CH to the lower end. The barrier metal BM2 covers the entire inner wall of the contact hole CH over the entire inner circumference.
The contact material CM2 is filled inside the barrier metal BM2 in the contact hole CH. The contact material CM2 continues from the inner wall of the upper portion to the inner wall of the lower portion of the contact hole CH. A metal material containing at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), and titanium (Ti), for example, is used for the contact material CM2, as with the contact material CM1. The contact materials CM1 and CM2 may be made of the same material as each other or different materials from each other. The contact material CM2 is formed by selective growth on the barrier metal BM2. Since the barrier metal BM2 is formed on the entire inner wall from the opening end (the upper end) to the lower end of the contact hole CH, the contact material CM2 is embedded in the entire inner wall of the contact hole CH from the opening end (the upper end) to the lower end, as with the barrier metal BM2.
As illustrated in
According to the present embodiment, the upper portion of the contact hole CH is formed, and thereafter the inner wall of the upper portion of the contact hole CH is protected by the barrier metal BM1 and the contact material CM1. Accordingly, it is possible to deepen the lower portion of the contact hole CH thereafter, without increasing the width of the upper portion of the contact hole CH. That is, the barrier metal BM1 and the contact material CM1 serve as mask for the inner wall of the upper portion of the contact hole CH, thereby preventing the upper portion of the contact hole CH from being widened more than necessary. Accordingly, the contact hole CH can penetrate through the interlayer dielectric film 24 without coming into contact with the insulator column HR illustrated in
The insulator column HR is filled with insulator as illustrated in
Meanwhile, according to the present embodiment, due to the barrier metal BM1 and the contact material CM1, it is possible to prevent excessive widening of the upper portion of the contact hole CH and to prevent contact of the contact hole CH with the insulator column HR. Accordingly, it is possible to prevent electrical short circuit between the electrode films 21 (that is, the word lines WL) adjacent to each other in the Z-direction.
Next, a manufacturing method of a semiconductor device according to the present embodiment is described.
Next, as illustrated in
Next, the barrier metal BM1 (for example, TiN) is deposited on an inner wall of the upper portion CH_U of the contact hole CH by CVD or the like, as illustrated in
The length in the Z-direction of the barrier metal BM1 in the contact hole CH can be controlled by the deposition condition of the barrier metal BM1. It is preferable that the barrier metal BM1 is provided to such a depth that the inner diameter of the contact hole CH formed without providing the barrier metal BM1 and the contact material CM1 is the maximum.
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, the contact material CM2 (for example, tungsten) is caused to selectively grow on the barrier metal BM2 in the contact hole CH. Since the barrier metal BM2 is provided on the entire inner wall of the contact hole CH, the contact material CM2 is embedded inside the contact hole CH entirely.
Next, as illustrated in
Thereafter, another interlayer dielectric film, a wiring layer (not illustrated), and the like are formed on the interlayer dielectric film 24 so that a semiconductor device according to the present embodiment is completed.
According to the present embodiment, in a process of forming the contact hole CH, it is possible to make the contact hole CH to penetrate through the interlayer dielectric film 24 to the electrode film 21, while the contact material CM1 and the barrier metal BM1 protect the inner wall of the upper portion CH_U, as illustrated in
In a case where the contact material CM1 and the barrier metal BM1 are not provided and the contact hole CH is formed using the mask member 26 as mask, the inner wall of the upper portion of the contact hole CH is etched to some extent by an etching gas of RIE, as illustrated in
Meanwhile, according to the present embodiment, the contact hole CH is formed while the contact material CM1 and the barrier metal BM1 protect the inner wall of the upper portion CH_U. It is thus possible to form a contact plug with a high aspect ratio while the width (the inner diameter) of the upper portion CH_U is maintained. In a case where this contact plug is applied to the contact plug CC, a distance can be ensured between the contact plug CC and the insulator column HR as illustrated in
In a case where the contact materials CM1 and CM2 are, for example, tungsten, it is likely that fluorine from the contact material CM1 or CM2 is diffused to a memory cell or a CMOS circuit because tungsten contains a lot of fluorine. However, in the present embodiment, fluorine is hardly diffused because the barrier metals BM1 and BM2 cover the outer circumferences of the contact materials CM1 and CM2 in the contact hole CH. In particular, the barrier metals BM1 and BM2 double cover the contact material CM2 in the upper portion CH_U of the contact hole CH. This configuration can more effectively prevent diffusion of fluorine from the contact material CM2 in the upper portion CH_U of the contact hole CH.
For example, a contact plug CCa is connected to an electrode film 21a. A contact plug CCb is connected to an electrode film 21b. A contact plug CCc is connected to an electrode film 21c. The electrode films 21a, 21b, and 21c are provided at levels (positions in the Z-direction) different from one another and, in accordance with this arrangement, the depths of the contact plugs CCa, CCb, and CCc are different from one another. The contact plug CCc is formed to be the deepest among the contact plugs CC in order to be connected to the lowermost electrode film 21c. By applying the contact plug according to the present embodiment to such a contact plug CCc having a high aspect ratio, the contact plug CCc can be connected to the electrode film 21c without coming into contact with the insulator column HR. Naturally, identical effects can be obtained also in a case where the contact plug according to the present embodiment is applied to the contact plug CCa or CCb.
In
For example, the memory cell array 2m is formed in the following manner.
First, plural insulation layers 22 and plural sacrifice films are alternately stacked in the Z-direction to form the stack 2. Next, the memory hole MH is formed to extend in the stack 2 in the Z-direction, and the column portion CL is formed in the memory hole MH. Next, the sacrifice films are removed, thereby forming spaces between the insulation layers 22 adjacent to each other in the Z-direction. At this time, the insulator columns HR support the insulation layers 22 to prevent the insulation layers 22 from bending in the Z-direction and prevent the spaces from being crushed. Next, a material for the electrode film 21 is embedded in the spaces between the insulation layers 22 to form the electrode films 21 (the word lines WL) between the insulation layers 22. Accordingly, the memory cells MC are provided to correspond to respective intersections between the column portions CL and the stack 2. Next, the interlayer dielectric film 24 is formed above or on the side of the stack. After the step portion 2s is formed, the contact plugs CC are formed to extend in the interlayer dielectric film 24 in the Z-direction, and are connected to the respective electrode films 21. The memory cell array 2m is formed in this manner.
Further, the contact plug C4 connects a wiring layer (not illustrated) above the memory cell array 2m and the wire 11a of a CMOS circuit below the memory cell array 2m to each other. The contact plug according to the present embodiment may be applied to this contact plug C4. Accordingly, the contact plug C4 can be connected to the wire 11a without coming into contact with another structure adjacent thereto.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2021-043775 | Mar 2021 | JP | national |