SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

In a method for manufacturing a semiconductor device, an insulating film is formed on an entire surface of a substrate having a device isolation region and a first and a second conductive region. Then, a semiconductor device structure having a gate electrode forming region is formed on each of the conductive regions, the insulating film being disposed between the gate electrode forming region and each of the conductive regions. A gate electrode groove is formed in the gate electrode forming region of the semiconductor device structure, the insulating film being removed in the gate electrode groove. Thereafter, a gate insulating film and a film of metal gate electrode material are deposited on a bottom surface and a side surface of the gate electrode groove and an alloy is formed by alloying the film of metal gate electrode material deposited in a gate electrode groove of the first conductive region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments, given in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross sectional view to explain a method in accordance with a first embodiment of the present invention;

FIG. 2 shows a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 3 provides a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 4 illustrates a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 5 describes a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 6 depicts a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 7 presents a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 8 represents a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 9 offers a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 10 shows a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 11 depicts a cross sectional view to explain the method in accordance with the first embodiment of the present invention;

FIG. 12 is a diagram of comparing CV characteristics of metal gate electrodes between the cases of forming the metal gate electrodes earlier and later;

FIG. 13 illustrates a cross sectional view to explain a method in accordance with a second embodiment of the present invention;

FIG. 14 presents a cross sectional view to explain the method in accordance with the second embodiment of the present invention;

FIG. 15 represents a cross sectional view to explain the method in accordance with the second embodiment of the present invention;

FIG. 16 provides a cross sectional view to explain the method in accordance with the second embodiment of the present invention;

FIG. 17 offers a cross sectional view to explain the method in accordance with the second embodiment of the present invention;

FIG. 18 describes a cross sectional view to explain a method in accordance with a third embodiment of the present invention;

FIG. 19 shows a cross sectional view to explain the method in accordance with the third embodiment of the present invention;

FIG. 20 depicts a cross sectional view to explain the method in accordance with the third embodiment of the present invention;

FIG. 21 illustrates a cross sectional view to explain the method in accordance with the third embodiment of the present invention;

FIG. 22 provides a cross sectional view to explain the method in accordance with the third embodiment of the present invention; and

FIG. 23 is a cross sectional view to explain the method in accordance with the third embodiment of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: forming an insulating film on an entire surface of a substrate having a device isolation region and a first and a second conductive region;forming a semiconductor device structure having a gate electrode forming region on each of the conductive regions, the insulating film being disposed between the gate electrode forming region and each of the conductive regions;forming a gate electrode groove in the gate electrode forming region of the semiconductor device structure, wherein the insulating film is removed in the gate electrode groove;depositing a gate insulating film and a film of metal gate electrode material on a bottom surface and a side surface of the gate electrode groove; andforming an alloy by alloying the film of metal gate electrode material deposited in a gate electrode groove of the first conductive region.

2. The method of claim 1, wherein the step of forming the alloy includes the steps of: depositing a reaction prevention film on the film of metal gate electrode material;removing the reaction prevention film of the first conductive region by etching; and thenforming the alloy by depositing an alloy forming material film and then performing a heat treatment.

3. The method of claim 2, the reaction prevention film is a silicon oxide film.

4. The method of claim 1 wherein the step of forming the alloy includes the steps of: depositing an alloy forming material film on the film of metal gate electrode material at a temperature at which the alloy forming material film is substantially unreacted with the film of metal gate electrode material;removing the alloy forming material film of the second conductive region by etching; and thenforming the alloy by performing a heat treatment.

5. A method for manufacturing a semiconductor device, comprising the steps of: forming an insulating film on an entire surface of a substrate having a device isolation region and a first and a second conductive region;forming a semiconductor device structure having a gate electrode forming region on each of the conductive regions, the insulating film being disposed between the gate electrode forming region and each of the conductive regions;forming a gate electrode groove in the gate electrode forming region of the semiconductor device structure, wherein the insulating film is removed in the gate electrode groove;depositing a gate insulating film and a film of metal gate electrode material on a bottom surface and a side surface of the gate electrode groove;forming a first alloy by alloying the film of metal gate electrode material disposed in a gate electrode groove of the first conductive region; andforming a second alloy different from the first alloy by alloying the film of metal gate electrode material disposed in a gate electrode groove of the second conductive region.

6. The method of claim 5, wherein the step of forming the first alloy includes the steps of: depositing a reaction prevention film on the film of metal gate electrode material;removing the reaction prevention film of the first conductive region by etching; and thenforming the first alloy by depositing a first alloy forming material film and then performing a heat treatment.

7. The method of claim 6, wherein the reaction prevention film is a silicon oxide film.

8. The method of claim 5, wherein the step of forming the first alloy includes the steps of: depositing a first alloy forming material film on the film of metal gate electrode material at a temperature at which the first alloy forming material film is substantially unreacted with the film of metal gate electrode material;removing the first alloy forming material film of the second conductive region by etching; andforming the first alloy by performing a heat treatment

9. The method of claim 5, wherein the step of forming the second alloy includes the steps of: depositing, after the step of forming the first alloy, a reaction prevention film on the entire surface;removing the reaction prevention film of the second conductive region by etching; andforming the second alloy by depositing a second alloy forming material film and then performing a heat treatment.

10. The method of claim 5, wherein the step of forming the second alloy includes the steps of: depositing, after the step of forming the first alloy, a second alloy forming material film at a temperature at which the second alloy forming material film is substantially unreacted with the film of metal gate electrode material;removing the second alloy forming material film of the first conductive region by etching; andforming the second alloy by performing a heat treatment.

11. The method of claim 5, wherein the second alloy is a germanide or a carbide.

12. The method of claim 5, wherein the first alloy is silicide.

13. The method of claim 1, wherein the first conductive region is an n-type MISFET region.

14. The method of claim 1, wherein the gate insulating film is formed of an oxide containing any one of Hf, Zr, Y and Ln.

15. The method of claim 1, wherein the metal gate electrode material is a transition metal of the group VIII of the periodic table or has a Fermi level close to a lowest conduction band off the center of a Si forbidden band.

16. The method of claim 1, wherein the gate electrode forming region corresponds to a dummy gate electrode formed on each of the conductive regions during the step of forming the semiconductor device structure and the gate electrode groove is formed by removing the dummy gate electrode and the insulating film thereunder after forming a source/drain region.

17. A CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) semiconductor device comprising: an n-type and a p-type MISFET region formed at a main surface region of a semiconductor substrate, wherein a gate electrode of the p-type MISFET region includes a germanide or a carbide, and a gate electrode of the n-type MISFET region includes a silicide.

18. The semiconductor device of claim 17, wherein the gate electrodes of the p-type and the n-type MISFET region include a transition metal of the group VIII of the periodic table.