Patent Application
20230290846
The present application claims priority to Korean Patent Application No. 10-2022-0029233, filed on Mar. 8, 2022, which is incorporated herein by reference in its entirety.
The present invention relates to a semiconductor device and method for fabricating the same, and more particularly, to a semiconductor device having a buried gate and a method for fabricating the same.
In order to improve the degree of integration of semiconductor devices, semiconductor devices having a structure in which word lines are buried in a substrate are under research.
An embodiment of the present invention provides a method of fabricating a semiconductor device capable of relieving a dangling bond formed at an interface between a substrate and a gate insulating layer.
According to an embodiment of the present invention, a semiconductor device comprises: a device isolation layer defining a plurality of active regions in a substrate, the device isolation layer including a first region where the active regions are spaced apart from each other at a first interval along a first direction and a second region where the active regions are spaced apart from each other at a second interval along the first direction, the second interval being wider than the first interval; a gate trench extending in the first direction to cross the active regions and the device isolation layer; and a buried gate structure gap-filling the gate trench, wherein the second region of the device isolation layer includes an air gap in a lower portion.
According to an embodiment of the present invention, a semiconductor device comprises: a substrate including an active region defined by device isolation layers; a gate trench formed both in the active region and the device isolation layer; and a buried gate structure gap-filling the gate trench, wherein the device isolation layer includes an air gap disposed at a lower level than the buried gate structure.
According to an embodiment of the present invention, a method of fabricating a semiconductor device comprises: forming a device isolation layer defining a plurality of active regions in a substrate, the device isolation layer including a first region where the active regions are spaced apart from each other at a first interval along a first direction and a second region where the active regions are spaced apart from each other at a second interval along the first direction, the second interval being wider than the first interval; forming a gate trench extending in the first direction to cross the active regions and the device isolation layer; and forming a buried gate structure gap-filling the gate trench, wherein the second region of the device isolation layer includes an air gap in a lower portion.
The present technology has the effect of improving the reliability of the semiconductor device by increasing the hydrogen passivation efficiency.
The present technology can form an asymmetric fin to increase the gate channel length and reduce the passing gate area to reduce interference between neighboring cells.
These and other features and advantages of the present invention will become apparent from the following description of detailed embodiments of the invention.
Various embodiments described herein will be described with reference to cross-sectional views, plan views and block diagrams, which are ideal schematic views of the present invention. Therefore, the structures of the drawings may be modified due to fabricating technology and/or tolerances. Accordingly, various embodiments of the present invention are not limited to the specific structures shown in the drawings, but include any changes in the structures that may be produced according to the fabricating process. Therefore, any regions and shapes of regions illustrated in the drawings have schematic views, are intended to illustrate specific examples of structures of regions of the various elements, and are not intended to limit the scope of the invention. Sizes and relative sizes of components shown in the drawings may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout, and “and/or” includes each and every combination of one or more of the recited items.
Reference to an element or layer “on” or “over” another element or layer includes not only the case where an element or layer is directly on the other element or layer, but also the case where an element or layer intervenes with other layers or elements. The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless otherwise specified in the phrase.
As shown in
The substrate 101 may be a semiconductor substrate. The substrate 101 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 101 may include a memory cell array region in which memory cells are formed and a peripheral circuit region in which peripheral circuits for operating the memory cells are formed.
The active regions 103 may have a major axis and a minor axis, and may be disposed to be spaced apart from each other in the major axis direction and the minor axis direction. For example, the active region 103 may have a bar shape having a length longer than a width, and may be arranged in an island shape.
The device isolation layer ISO may be formed in the substrate 101. The device isolation layer ISO may define a plurality of active regions 103. The device isolation layer ISO may include isolation trench 102 formed in the substrate 101 and at least one insulating material gap-filled in the isolation trench 102. The device isolation layer ISO may include a first region R1 in which the active regions 103 are spaced apart at a first interval along the first direction D1 and a second region R2 in which the active regions 103 are spaced apart at a second interval along the first direction D1. The second interval may be wider than the first interval.
In an embodiment, the device isolation layer ISO may include a first and a second insulating material. The first insulating material may be for gap-filling the first region R1 and the second insulating material may be for gap-filling the second region R2. The first region R1 of the device isolation layer ISO may include a liner oxide layer 104 covering the sidewalls and bottom surfaces of the isolation trench 102 and a gap fill oxide layer 107 gap-filling the isolation trench 102. The second region R2 of the device isolation layer ISO may include a liner oxide layer 104 covering the sidewalls and bottom surfaces of the isolation trench 102, a gap-fill oxide layer 107 gap-filling a portion of the isolation trench 102, an air gap 108 formed between a bottom surface of the isolation trench 102 and the gap-fill oxide layer 107, and an isolation capping layer 109 that gap-fills the remainder of the isolation trench over the gap-fill oxide layer 107. For example, the isolation capping layer 109 may include silicon nitride.
In particular, in this embodiment, the air gap 108 may function as a hydrogen pocket. Hydrogen in the air gap 108 can increase the efficiency of a hydrogen passivation process by supplying hydrogen to the surface of the substrate 101. Specifically, hydrogen from the air gap 108 diffuses toward the substrate 101 during the hydrogen passivation process, and the diffused hydrogen may cure a dangling bond at the interface between the substrate 101 and the gate insulating layer 114.
Word lines WL1 and WL2 (or WL) may extend in a first direction D1 crossing the active regions 103, and the bit lines BL may extend in a second direction D2 crossing the first direction D1. The first direction D1 and the second direction D2 may cross vertically.
The active regions 103 are arranged to be tilted at a predetermined angle with respect to the word lines WL and the bit lines BL, so that one active region 103 may be formed to cross with two word lines WL and one bit line BL as is illustrated in
According to the 6F2 cell structure, the word line WL and the bit line BL cross each other vertically, and the active regions 103 is tilted in a diagonal direction with respect to the word line WL and the bit line BL are tilted. This structure is advantageous because it reduces the cell area. The semiconductor device according to an embodiment of the present invention is not limited to the described 6F2 cell structure only, but includes any cell structure falling within the scope of the present invention which decreases the cell area and improves the degree of integration of the semiconductor device.
The gate structures BG include gate trenches 113 formed in the substrate 101, gate insulating layers 114 uniformly formed on inner walls of the gate trenches 113, and a gate electrode 115 filling a portion of the gate trenches 113, and a gate capping layer 116 filling the remainder of the gate trenches 113 over the gate electrode 115. In this embodiment, the gate electrode 115 indicates a cross-section of the word line WL, and the gate electrode 115 and the word line WL indicate the same area.
Since the word line WL is formed of buried gate lines, a buried channel transistor may be implemented. The buried channel transistor may reduce a unit cell area and increase an effective channel length compared to a planar transistor. In the buried channel transistor, the capacitance between the word line WL and the bit line BL and the total capacitance of the bit line BL can be lowered to reduce parasitic capacitance since the word line WL is buried in the substrate 101.
The gate trench 113 may extend in the first direction D1. The gate trench 113 may cross the active region 103 and the device isolation layer ISO in the first direction D1. The device isolation layer ISO positioned under the gate trench 113 may have different heights in the first region R1 and the second region R2. The device isolation layer ISO under the gate trench 113 may have a height h1 in the first region R1 which is smaller than a height h2 in the second region R2. The upper surface of the first region R1 of the device isolation layer ISO under the gate trench 113 may be located at a level lower than the upper surface of the active region 103 under the gate trench 113. The upper surface of the second region R2 of the device isolation layer ISO under the gate trench 113 may be located at the same level as the upper surface of the active region 103 under the gate trench 113.
In another embodiment, an upper surface of the second region R2 of the device isolation layer ISO under the gate trench 113 may be located at a higher level than the upper surface of the active region 103 under the gate trench 113. In another embodiment, an upper surface of the second region R2 of the device isolation layer ISO under the gate trench 113 may be located at a lower level than an upper surface of the active region 103 under the gate trench 113.
The active region 103 protruding between the isolation layers ISO disposed in the direction in which the gate trench 113 extends, that is, in the first direction, may be referred to as a ‘fin 103F’. See
The lower surface of the gate electrode 115 may be lower in the first region R1 of the device isolation layer ISO than in the active region 103 and the second region R2 of the device isolation layer ISO. That is, in the first region R1 of the device isolation layer ISO in which word line interference between neighboring cells does not occur, the channel length may be sufficiently secured by a fin 103F as the bottom surface of the gate electrode 115 is positioned at a lower level than in the active region 103. Accordingly, the driving current of the transistor may be increased and the operating characteristics may be improved. In addition, in the second region R2 of the device isolation layer ISO, the area of the passing gate decreases as much as the height of the device isolation layer ISO, thereby preventing word line interference between neighboring cells (Row Hammer). Here, the passing gate refers to a word line WL formed in the device isolation layer ISO between adjacent active regions 103 spaced apart from each other in the long axis direction.
A first impurity region 117 and a second impurity region 118 serving as a source and a drain of the transistor may be formed in the active region 103 on both sides of the gate structure BG. The first impurity region 117 may be electrically connected to the bit line BL, and the second impurity region 118 may be electrically connected to the capacitor CAP. The bit line BL and the first impurity region 117 may be electrically connected to each other by a bit line contact plug BLC. The capacitor CAP and the second impurity region 118 may be electrically connected to each other by a storage contact plug SNC.
As shown in
The substrate 101 may be a material suitable for semiconductor processing. The substrate 101 may include a semiconductor substrate. The substrate 101 may be made of a material containing silicon. The substrate 101 may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon doped silicon, combinations thereof, or multiple layers thereof. The substrate 101 may include other semiconductor materials such as germanium. The substrate 101 may include a III/V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 101 may include a silicon on insulator (SOI) substrate.
The active region 103 defined by the isolation trench 102 may be formed to have a long axis and a short axis. The active region 103 may be two-dimensionally arranged along the long axis direction and the short axis direction. For example, the active region 103 may have a bar shape having a length longer than a width, and may be arranged in an island shape.
The isolation trench 102 may include a first region R1 in which the active regions 103 are spaced apart at a first interval along the first direction D1 and a second region R2 in which the active regions 103 are spaced apart at a second interval, which is greater than the first interval, in the first direction D1.
As shown in
As shown in
Hydrogen supplied through the process of forming the first hydrogen supply layer 105 may diffuse into the interface between the substrate 101 and the liner oxide layer 104 or into the substrate 101. Hydrogen supplied through the process of forming the first hydrogen supply layer 105 may eliminate the dangling bonds by forming Si—H or Si—OH bonds at the surface of the substrate 101 (e.g., the interface between the substrate 101 and the liner oxide layer 104). Accordingly, it is possible to reduce a trap charge due to a dangling bond.
Next, the first hydrogen supply layer 105 may be removed.
As shown in
As the first forming gas annealing 106 is performed, hydrogen is diffused into the interface between the substrate 101 and the liner oxide layer 104 or into the substrate 101. Hydrogen supplied through the first forming gas annealing 106 can eliminate dangling bonds by forming Si—H or Si—OH bonds at a surface of the substrate 101 (e.g., the interface between the substrate 101 and the liner oxide layer 104). Accordingly, it is possible to reduce a trap charge due to a dangling bond.
As shown in
The first region R1 of the isolation trench 102 may be fully gap-filled with the gap-fill oxide layer 107. An air gap 108 may be formed under the second region R2 of the isolation trench 102 by the step coverage of the gap fill oxide layer 107.
As shown in
First, the gap-fill oxide layer 107 may be recessed to a predetermined thickness in the second region R2 of the isolation trench 102. The recess process may be performed under a condition that only the gap-fill oxide layer 107 gap-filled in the second region R2 is selectively recessed. Next, an insulating material may be formed on the gap-fill oxide layer 107 of the second region R2 to gap-fill the remainder of the isolation trench 102, and a planarization process may be performed to form the isolation capping layer 109. For example, the isolation capping layer 109 may include silicon nitride.
Accordingly, the device isolation layer ISO including the gap-fill oxide layer 107 may be formed in the first region R1 of the isolation trench 102, and the device isolation layer ISO having a stacked structure of the air gap 108, a gap-fill oxide layer 107, and an isolation capping layer 109 may be formed from the bottom of the isolation trench 102 in the second region of the isolation trench 102.
As shown in
Hydrogen supplied through the second forming gas annealing 110 process may diffuse to the interface between the substrate 101 and the liner oxide layer 104 or may be trapped in the air gap 108. That is, as the hydrogen supplied through the second forming gas annealing 110 process diffuses into the substrate 101, it moves into the air gap 108 having a relatively large amount of space and is trapped therein. Thus, the air gap 108 may function as a hydrogen pocket storing hydrogen.
As shown in
The hydrogen which is supplied through the process of forming the first hydrogen supply layer 105 is trapped at the interface between the substrate 101 and the liner oxide layer 104 or in the air gap 108.
Subsequently, the second hydrogen supply layer 111 is removed.
As shown in
Subsequently, the substrate 101 may be etched to form the gate trench 113. The gate trench 113 may have a line shape crossing the active regions 103 and the device isolation layer ISO.
As shown in
The active region 103 is protruding between the device isolation layers ISO which are disposed in the first direction D1 in which the gate trench 113 extends, that is, in the first direction, and the protrusion is referred to as ‘fin 103F’. The fin 103F may be formed in the active region 103 in contact with the first region R1 of the device isolation layer ISO. The fin 103F may not be formed in the active region 103 in contact with the second region R2 of the device isolation layer ISO. That is, the fin 103F is not formed in the second region R2 of the device isolation layer ISO positioned at the same level as the active region 103 under the gate trench 113, and may have an asymmetric shape that is locally formed only in the first region R1 of the device isolation layer ISO which is positioned at a level lower than the upper surface of the active region 103 under the gate trench 113.
As shown in
The buried gate structure BG may include a gate insulating layer 114 covering the surface of the gate trench 113 including the fin 103F, a gate electrode 115 gap-filling a portion of the gate trench 113 on the gate insulating layer 114, and a gate capping layer 116 gap-filling the remainder of the gate trench 113 on the gate electrode 115.
The gate insulating layer 114 may be formed by thermal oxidation. For example, the gate insulating layer 114 may be formed by oxidizing the bottom and sidewalls of the gate trench 113.
In another embodiment, the gate insulating layer 114 may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate insulating layer 114 may include a high-k material, oxide, nitride, oxynitride, or a combination thereof. The high-k material may include hafnium oxide. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In another embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and combinations thereof. In another embodiment, the gate insulating layer 114 may be formed by depositing liner polysilicon and then radically oxidizing the liner polysilicon layer. In another embodiment, the gate insulating layer 114 may be formed by radically oxidizing the liner silicon nitride layer after forming the liner silicon nitride layer.
The gate electrode 115 may include a conductive material. To form the gate electrode 115, a recessing process may be performed after a conductive layer is formed to fill the gate trench 113. The recessing process may be performed as an etchback process, or a chemical mechanical polishing (CMP) process and an etchback process may be sequentially performed. The gate electrode 115 may have a recessed shape that partially fills the gate trench 113. That is, the upper surface of the gate electrode 115 may be at a lower level than the upper surface of the substrate 101. The gate electrode 115 may include a metal, a metal nitride, or a combination thereof. For example, the gate electrode 115 may be formed of a titanium nitride (TiN), tungsten (W), or a titanium nitride/tungsten (TiN/W) stack. The titanium nitride/tungsten (TiN/W) stack may include titanium nitride which is first conformally formed in the gate trench 113 and then the tungsten is partially filled in the gate trench 113. In an embodiment, the gate electrode 115 is formed solely from titanium nitride, and this embodiment is referred to hereinafter as a “TiN only” gate electrode structure. In another embodiment, the gate electrode 115 includes a double gate structure of a titanium nitride/tungsten (TiN/W) stack and a polysilicon layer.
The gate capping layer 116 includes an insulating material. For example, the gate capping layer 116 may include silicon nitride. In another example, the gate capping layer 116 may include silicon oxide. In yet another example, the gate capping layer 116 may have a nitride-oxide-nitride (NON) structure.
Subsequently, first and second impurity regions 117 and 118 may serve as a source and a drain of the transistor and may be formed in the active region 103 on both sides of the gate structure BG. For example, the first and second impurity regions 117 and 118 may be formed by a doping process such as implantation. The first and second impurity regions 117 and 118 are also referred to as ‘source/drain regions’.
The first impurity region 117 is electrically connected to the bit line BL. The second impurity region 118 is electrically connected to the capacitor CAP. The bit line BL and the first impurity region 117 are electrically connected to each other via, for example, a bit line contact plug BLC. The capacitor CAP and the second impurity region 118 may be electrically connected to each other by a storage contact plug SNC.
A metal wiring process may be performed on the capacitor CAP for forming a metal wire and a hydrogen supply layer may be formed on the metal wire.
Subsequently, a hydrogen passivation process 119 may be performed. The hydrogen passivation process 119 supplies hydrogen to the surface of the substrate 101 for repairing surface defects such as dangling bonds.
Generally, during a manufacturing process of a semiconductor device, defects may be generated in a unit element of the semiconductor device. For example, defects in a unit element may appear during an oxidation process, a plasma etching process, and like processes. These defects alter the electrical characteristics of the semiconductor device. For example, generally, dangling bonds may form at the interface between the silicon oxide layer and the silicon substrate of a unit element and between the gate insulating layer and the substrate, which increase leakage current and deteriorate the electrical characteristics of the semiconductor device. In the case of a dynamic random-access memory (DRAM) semiconductor device, it is necessary to re-store the existing data at regular intervals by using a refresh method for storing new data. In this case, the predetermined period is referred to as a refresh period or a data retention time. In order to reduce the power consumption of the DRAM and increase the operation speed, it is required to increase the data retention time. However, due to a structural defect in the silicon crystal such as a dangling bond, a leakage current may increase in the transistors and a data retention time may also be reduced.
In this embodiment, during the hydrogen passivation process, hydrogen stored in the air gap 108 in the device isolation layer ISO diffuses to the interface between the substrate 101 and the gate insulating layer 114, and dangling bonds may be eliminated by forming Si—H or Si—OH bonds at an interface between the substrate 101 and the gate insulating layer 114. Therefore, the efficiency of the hydrogen passivation process may be maximized compared to when the hydrogen passivation process is performed by using only the hydrogen supply layer above the metal wiring.
Various embodiments of the present invention have been described which fall within the scope of the present invention and solve the aforementioned problems associated with the prior art, however, the present invention is not limited to these embodiments only. It should be apparent to those skilled in the art that various other changes and modifications could be made within the technical scope and spirit of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0029233 | Mar 2022 | KR | national |
