This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-126811, filed on May 26, 2009 the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device including a readily reducible structure, such as an electrically conductive oxide film, and a method for making a semiconductor device.
With the advancement of digital technologies, the need for high-speed processing a large-volume data has increased unprecedentedly in recent years. New memory devices are being proposed to meet this need.
For example, dynamic random access memories (DRAMs) have been widely used as high-speed semiconductor memories. Now attempts are being made to use metal oxides, which form high-dielectric-constant elements or ferroelectric elements, in memory capacitors instead of existing silicon oxide films or silicon nitride films. This is to comply with the decrease in capacitor area resulting from size reduction.
In recent years, nonvolatile, high-speed semiconductor memories that include ferroelectric capacitors using ferroelectric films as capacitor insulating films have been put to practical use. Such memories are called ferroelectric random access memories (FeRAMs). FeRAMs are voltage-driven devices that store information by utilizing hysteresis characteristics of ferroelectric films. Unlike flash memories, FeRAMs do not need injection of charges into floating gates and operate at high speed and low power consumption.
Ferroelectric films that have been used in FeRAMs heretofore include films composed of perovskite-type metal oxides, such as lead zirconate titanate (PZT), formed by a sol-gel method, a sputtering method, or a metalorganic chemical vapor deposition method (MOCVD method), and films composed of bismuth layered compounds such as SrBi2Ta2O9 (SBT; Y1), SrBi2(Na,Nb)2O9 (SBTN; YZ), Bi4Ti3O9, (Bi,La)4Ti3O12, and BiFeO3.
Presently, studies are being conducted on magnetic random access memories (MRAMs) that use magnetic tunneling junctions (MTJs) for storing information.
According to conventional semiconductor devices that include ferroelectric films, metal oxide films that constitute the ferroelectric films may become readily reduced by hydrogen and lose the expected hysteresis characteristics. In order to avoid this problem, special care must be taken in forming upper electrodes after forming the ferroelectric films. After forming ferroelectric capacitors, it is essential to conduct a heat treatment in an oxygen atmosphere to compensate for the oxygen deficiencies in the ferroelectric films; however, when a noble metal stable in oxidative atmosphere such as platinum (Pt) is used in the upper electrodes, hydrogen, which is used to bury the ferroelectric capacitors with interlayer insulating films and to form wiring in the later process, may be activated by a catalytic effect of the noble metal such as platinum and may reduce the ferroelectric films.
For this reason, electrically conductive oxides such as iridium oxide (IrO2) and ruthenium oxide (RuO2) that are stable for processes conducted in oxidative atmosphere and generate no such catalytic effect have been used in the upper electrodes of ferroelectric capacitors. In order to block penetration of a hydrogen atmosphere and improve the interface characteristics between the ferroelectric films (PZT films) and upper electrodes, Japanese Patent No. 3661850 proposes that the upper electrode have a two-layer structure in which an iridium oxide film having a nonstoichiometric composition IrOx (x<2) as well as including oxygen deficiencies is used in the lower layer portion and an iridium oxide film having a higher degree of oxidation and a stoichiometric composition or a composition close to the stoichiometric, IrO2, is used in the upper layer portion. However, electrically conductive oxide films such as iridium oxide films also become readily reduced once exposed to a hydrogen atmosphere and it is difficult to control the degree of oxidation to a desired level.
In sum, it is desirable for semiconductor devices including ferroelectric capacitors not to expose the ferroelectric films forming the ferroelectric capacitors and the electrically conductive oxide films forming the upper electrodes to a hydrogen atmosphere after the ferroelectric capacitors are formed.
In recent years, a stringent requirement for size reduction has also been imposed upon FeRAMs including the ferroelectric capacitors. Desirably, the diameter of contact holes formed in the interlayer insulating films should be reduced to correspond with the upper electrodes of the ferroelectric capacitors, and the aspect ratio (or b/a ratio) of the contact holes should be increased.
It has been common practice to fill such fine contact holes with tungsten (W) plugs formed by a CVD process. In this tungsten CVD process, it is common practice to reduce the tungsten source gas with hydrogen to achieve a high step coverage. However, when hydrogen is used, the electrically conductive oxides forming the upper electrodes and the ferroelectric films are reduced by hydrogen and the electrical characteristics of the ferroelectric capacitors deteriorate significantly during formation of the tungsten plugs. In order to avoid this problem, Japanese Laid-open Patent Publication No. Hei03-003332 describes a technique of forming tungsten plugs by reducing a source gas composed of tungsten hexafluoride (WF6) with a silane (SiH4) gas.
According to one aspect of the invention, a semiconductor device includes a functional element including an upper electrode composed of an electrically conductive metal oxide and being configured to store information; an interlayer insulating film covering the functional element; a contact hole formed in the interlayer insulating film, the contact hole including a side wall surface and a bottom and exposing the upper electrode at the bottom; an electrically conductive barrier film covering the bottom and the side wall surface of the contact hole; and a tungsten film formed on the electrically conductive barrier film, the tungsten film filling at least part of the contact hole, wherein a layer in which silicon atoms are concentrated is formed at the interface between the tungsten film and the electrically conductive barrier film.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
Regarding the technique of forming tungsten plugs by reducing a source gas composed of tungsten hexafluoride (WF6) with a silane (SiH4) gas, the inventors of the present invention have noticed two tendencies: (1) When the WF6 source gas is reduced with a hydrogen gas, deposition of tungsten mainly occurs at the interfaces of the contact holes and thus a relatively high step coverage is achieved whereas when the WF6 source gas is reduced with a silane gas, the reduction reaction occurs in a vapor phase, resulting in formation of tungsten particles which creep into contact holes and thereby cause failures; (2) The WF6 molecules that have reached the contact holes become decomposed starting from inhomogeneous portions on the contact hole surfaces and form precipitates of tungsten, thereby tending to form tungsten overhangs at contact hole openings and degrading the step coverage. In addition to the problem of particle generation described above, tungsten may not sufficiently fill the contact holes. Embodiments effective for addressing these challenges are described below.
Referring to
The capacitor structure 12 is also covered with an interlayer insulating film 14, such as a tetraethoxysilane (TEOS) oxide film, having a low water content. A contact hole 14A that exposes the upper electrode 12C of the capacitor structure 12 is formed in the interlayer insulating film 14.
In the state illustrated in
The structure illustrated in
The thickness of the silicon-rich layer 16 thus formed increases by extending the duration of the initialization step illustrated in
In the initialization step illustrated in
The silicon-rich layer 16 formed in the initialization step does not have to be a continuous silicon film and may be a non-continuous film constituted by silicon atoms concentrating in defect portions of the barrier metal film 15.
Next, as illustrated in
After the step illustrated in
For example, the step illustrated in
In
In general, reduction of WF6 with hydrogen selectively occurs at the solid/gas interface and thus the tungsten burying layer 18 is sequentially deposited on the initial tungsten film 17 and fills the contact hole 14A with good step coverage. Although the tungsten raw material is reduced with hydrogen in the step illustrated in
The structure of
The graph in
Referring to
When the pressure inside the processing apparatus reaches the particular value, feeding of a silane gas is started at a flow rate of 10 scan and thus the initialization step illustrated in
After the initialization step, the flow rate of the argon carrier gas is increased to 800 sccm, the flow rate of the nitrogen carrier gas is decreased to 100 sccm, the flow rate of the silane gas is decreased to 4 sccm, and the feeding of the WF6 gas serving as the tungsten raw material is started at a flow rate of 15 sccm. This marks the start of the step of forming the initial tungsten film 17 illustrated in
After the step of forming the initial tungsten film, a tungsten filling step illustrated in
In general, in forming a tungsten film, a seeding step of delivering the tungsten source gas at a high flow rate is frequently conducted in advance to form seeds. In this embodiment also, a recipe illustrated in
The method for forming the tungsten contact plug according to this embodiment is applicable to those electronic apparatuses in general which include metal oxide films susceptible to losing their characteristics by reduction with hydrogen. Examples of such electronic apparatuses include ferroelectric memories (FeRAMs) and magnetic random access memories (MRAMs) described below.
In the step illustrated in
In this embodiment, the initial tungsten film 17 is formed using silane as a reductant in the step illustrated in
What is concerned about forming the initial tungsten film 17 by reduction with silane in the step illustrated in
When the contact hole has a high aspect ratio, e.g., an aspect ratio of 10 or more, the step coverage of the initial tungsten film 17 may deteriorate. However, in such a case, formation of the initial tungsten film 17 may be divided over plural steps. For example, a process of depositing a thin layer, milling the thin layer by CMP or etching back, and reducing the thin layer with silane again may be repeated several times to form the initial tungsten film 17 with high step coverage.
In this embodiment, the upper electrode 12C may be formed of a ruthenium oxide film, a strontium ruthenium oxide film, a strontium titanate film, or the like instead of the iridium oxide film.
The first embodiment described above may be summarized as follows. When the initialization step of exposing the side wall surface and bottom surface of the contact hole to a silane gas is conducted immediately before a tungsten film is formed to fill the contact hole exposing the upper electrode composed of an electrically conductive oxide, the side wall surface and bottom surface of the contact hole are at least covered with silicon atoms forming a monoatomic layer. As a result, the step coverage of the tungsten film formed on the silicon monoatomic layer is improved. When the initialization step is performed in an atmosphere containing no hydrogen or very little hydrogen at a flow rate twice the flow rate of the silane gas or less, reduction of the electrically conductive oxide constituting the upper electrode or the ferroelectric film formed under the upper electrode may be suppressed. In particular, when the initial tungsten deposition step of reducing the tungsten source gas with a silane gas is provided after the initialization step, the side wall surface and bottom surface of the contact hole are covered with a tungsten film without using hydrogen or while suppressing the hydrogen flow rate to a minimum level. Thus, in the subsequent tungsten filling step involving reduction with hydrogen, the problem that the hydrogen in the atmosphere reaches the upper electrode and reduces the electrically conductive oxide does not occur. In general, a tungsten film formed by reducing the raw material of tungsten with a silane gas tends to be poor in terms of step coverage. However, in this embodiment, since the side wall surface and bottom surface of the contact hole are covered with silicon atoms by conducting the initialization step beforehand, the tungsten film is formed with high step coverage in the initial tungsten deposition step.
A method for making a ferroelectric memory (FeRAM) according to a second embodiment of the present invention will now be described with reference to
Referring first to
A p-well 21PW containing a p-type impurity is formed in the active region 21A of a silicon substrate 21. A thermal oxide film that serves as a gate insulating film is formed on the surface of the p-well 21PW.
A gate electrode 23GA and a gate electrode 23GB are formed by patterning an amorphous or polycrystalline silicon film on the silicon substrate 21. Gate insulating films 22A and 22B are respectively formed under the gate electrode 23GA and the gate electrode 23GA by patterning the thermal oxide film. The gate electrodes 23GA and 23GB are disposed on the p-well 21PW in parallel with each other with a space therebetween to respectively form part of word lines. Channel regions respectively corresponding to the gate electrode 23GA and the gate electrode 23GB are formed directly under the gate electrode 23GA and the gate electrode 23GB, the channel regions being formed in the p-well 21PW in the active region 21A.
In the silicon substrate 21, an n-type source extension region 21a and an n-type drain extension region 21b are respectively formed in regions adjacent to the gate electrode 23GA by injecting ions of an n-type impurity using the gate electrodes 23GA and 23GB as masks. At the same time, in the silicon substrate 21, an n-type source extension region 21c and an n-type drain extension region 21d are respectively formed in regions adjacent to the gate electrode 23GB. The drain extension regions 21b and 21c are actually formed as one impurity-diffused region.
An insulating side wall 23WA is formed on side wall surface of the gate electrode 23GA by depositing an insulating film on the entire upper surface of the silicon substrate 21 and then etching back the insulating film. A similar insulating side wall 23WB is formed on the side wall surface of the gate electrode 23GB. The insulating side walls may be formed by, for example, depositing a silicon oxide film by a CVD method.
An n-type source region 21e and an n-type drain region 21f are formed in the silicon substrate 21 in regions outside the insulating side wall 23WA of the gate electrode 23GA by injecting ions of an n-type impurity into the silicon substrate 21 again while using the insulating side wall 23WA, the gate electrode 23GA, and the insulating side wall 23WB as masks. In the silicon substrate 21, an n-type source region 21g and an n-type drain region 21h are formed in regions outside the insulating side wall 23WB of the gate electrode 23GB in a similar manner. The n-type drain region 21f and the n-type source region 21g are formed as one impurity-diffused region.
As a result, the active region 21A of the silicon substrate 21 includes a first metal oxide semiconductor (MOS) transistor MOSA having the gate electrode 23GA, and a second metal oxide semiconductor (MOS) transistor MOSB having the gate electrode 23GB.
The exposed surfaces of the n-type source region 21e, the n-type drain region 21f, the n-type source region 21g, and the n-type drain region 21h are provided with a refractory metal silicide layer (not illustrated in the drawing) formed by sputter-depositing a refractory metal layer such as a cobalt layer on the entire surface of the silicon substrate 21 and then heating the refractory metal layer to cause a reaction between the refractory metal layer and silicon. Similar refractory metal silicide layers are also formed on the surface portions of the gate electrodes 23GA and 23GB and respectively serve as a silicide layer 23SA and a silicide layer 23SB that reduce the wiring resistance of the gate electrodes 23GA and 23GB.
According to the structure illustrated in
The upper surface of the first interlayer insulating film 25 is planarized by chemical mechanical polishing (CMP). As a result of the CMP, the first interlayer insulating film 25 has a thickness of about 700 nm on the flat portion of the silicon substrate 21.
Contact holes that penetrate the oxygen barrier film 24, expose the n-type source region 21e and the n-type drain region 21f of the transistor MOSA and the n-type source region 21g of the transistor MOSB, and have a diameter of 0.25 μm, for example, are formed in the first interlayer insulating film 25. Similarly, a contact hole that penetrates the oxygen barrier film 24, exposes the n-type drain region 21h of the transistor MOSB, and has a diameter of 0.25 μm, for example, is formed in the first interlayer insulating film 25. Tungsten plugs 25A, 25B, and 25C that make electrical contact with the impurity-diffused regions 21e to 21f are formed in these contact holes by a CVD technique. Adhesive films (glue films) 25a to 25c each having a multilayer structure constituted by a 30 nm-thick Ti film and a 20 nm-thick TiN film are interposed between the tungsten plugs 25A to 25C and the impurity-diffused regions 21e to 21f.
A first anti-oxidation film 26 composed of SiON having a thickness of, for example, 100 nm is formed by a CVD method on the first interlayer insulating film 25 in which the tungsten plugs 25A to 25C are formed. A second interlayer insulating film 27 formed of a silicon oxide film by a plasma-enhanced CVD method using TEOS as the raw material is formed on the first anti-oxidation film 26. The thickness of the second interlayer insulating film 27 is, for example, 130 nm.
A first ferroelectric capacitor 28A and a second ferroelectric capacitor 28B that respectively correspond to the transistor MOSA and the transistor MOSB are formed on the second interlayer insulating film 27. The first ferroelectric capacitor 28A and the second ferroelectric capacitor 28B are each prepared by sequentially stacking a lower electrode 28a which is composed of platinum (Pt) and has the (111) orientation, a first capacitor insulating film 28b which is a PZT film prepared by a sputtering method, a sol-gel method, a CVD method, or the like and has the (111) orientation, a second capacitor insulating film 28c which is also a PZT film and has the (111) orientation, a first upper electrode film 28d which is formed of an electrically conductive metal oxide film such as IrOx and has a non-stoichiometric composition (x<2), and a second upper electrode film 28e having a stoichiometric composition, such as IrO2, or a composition close to stoichiometric.
The ferroelectric capacitors 28A and 28B are formed on a thin aluminum oxide (Al2O3) film 28f having a thickness of about 20 nm on the second interlayer insulating film 27. In this manner, the crystal orientation of the platinum film constituting the lower electrode 28a is effectively regulated to the desired (111) orientation.
To be more specific, the platinum film constituting the lower electrode 28a is formed to a thickness of about 100 nm, for example, in an argon atmosphere at a substrate temperature of 350° C. and a 0.2 kW sputtering power. However, the platinum film formed as such is further subjected to a rapid heat treatment at 650° C. to 750° C. for 60 seconds in an inert gas (e.g., Ar) atmosphere and has good crystallinity and (111) orientation. Alternatively, the lower electrode 28a may be composed of iridium (Ir) or an electrically conductive oxide such as platinum oxide (PtO), iridium oxide, or strontium ruthenium oxide (SrRuO3) instead of platinum.
The PZT film constituting the first capacitor insulating film 28b is, for example, formed to a thickness of 50 nm to 100 nm under a pressure of 0.5 to 1.0 Pa at a substrate temperature of room temperature to 200° C. and a sputter power of 0.1 kW to 1 kW in an argon-oxygen mixed atmosphere with an argon gas flow rate of 1500 sccm and an oxygen gas flow rate of 30 sccm. The PZT film is then continuously subjected to a heat treatment at a temperature of 500° C. to 800° C. in an oxygen atmosphere to be crystallized and have oxygen deficiencies compensated. As a result, the desired (111) orientation and good electrical characteristics are achieved.
The PZT film constituting the second capacitor insulating film 28c is, for example, formed to a thickness of 25 nm under a pressure of 0.5 Pa at a substrate temperature of 200° C. or less and a sputter power of 0.5 kW in an argon-oxygen mixed atmosphere with an argon gas flow rate of 1500 sccm and an oxygen gas flow rate of 30 sccm but is not immediately subjected to a heat treatment in an oxidizing atmosphere. After formation of the PZT film constituting the second capacitor insulating film 28c, the first upper electrode film 28d composed of iridium oxide having a non-stoichiometric composition is formed on the PZT film (second capacitor insulating film 28c) to a thickness of 50 nm under a pressure of 0.8 Pa at a substrate temperature of 300° C. and a sputter power of 1 kW to 2 kW in an argon-oxygen mixed atmosphere with an argon flow rate of 140 sccm and an oxygen gas flow rate of 60 sccm. Then the first upper electrode film 28d and the second capacitor insulating film 28c are simultaneously heated at 725° C. for 60 seconds in an oxygen atmosphere, e.g., a mixed atmosphere of argon and oxygen. As a result, the second capacitor insulating film 28c is crystallized while achieving the desired (111) orientation and, at the same time, the oxygen deficiencies are compensated. When an iridium oxide film having a non-stoichiometric composition is directly formed on the sputter-deposited PZT film and then a heat treatment is performed in an oxygen atmosphere, a flat stable interface is obtained between the PZT film constituting the second capacitor insulating film 28c having the (111) orientation and the iridium oxide film constituting the first upper electrode film 28d. When this heat treatment is conducted, damage caused by sputter-depositing the iridium oxide film on the second capacitor insulating film 28c (PZT film) is recovered.
The iridium oxide film having the stoichiometric composition and constituting the second upper electrode film 28e is formed to a thickness of 50 nm to 150 nm by performing sputter deposition in an argon atmosphere under a pressure of 0.8 Pa at a 1.0 kW sputter power for 45 seconds. During the sputter-deposition, in order to suppress abnormal growth of iridium oxide, the substrate temperature is controlled to 100° C. or less. The iridium oxide thus formed has a composition close to a stoichiometric composition, i.e., IrO2.
A layered structure constituted by the layers 28a to 28e thus formed is patterned into the first ferroelectric capacitor 28A and the second ferroelectric capacitor 28B by dry-etching the layered structure by using a hard mask pattern (not illustrated) formed on the iridium oxide film constituting the second upper electrode film 28e. This hard mask pattern is composed of, for example, titanium nitride (TiN) and formed to correspond the transistors MOSA and MOSB. Then the hard mask pattern is removed by wet-etching from the first ferroelectric capacitor 28A and the second ferroelectric capacitor 28B obtained thereby and an oxygen deficiency-compensating process involving a heat treatment is performed in an oxygen atmosphere. The side wall surfaces and the top surfaces of the first and second ferroelectric capacitors 28A and 28B are covered with a first aluminum oxide film that has a thickness of about 50 nm and serves as a first hydrogen barrier film 28g and a second aluminum oxide film that has a thickness of about 20 nm and serves as a second hydrogen barrier film 28h. According to the structure of this embodiment, since the iridium oxide film constituting the second upper electrode film 28e has a stoichiometric composition or a composition close to the stoichiometric composition, the contact between the second upper electrode film 28e and the hydrogen gas does not cause the hydrogen catalytic effect. Thus, the problem of reduction of the first capacitor insulating film 28b and the second capacitor insulating film 28c with hydrogen radicals is suppressed and the hydrogen resistance of the capacitors is improved.
In this embodiment, strontium ruthenium oxide (SrRuO3) films having a thickness of 50 nm to 150 nm may be used as the first upper electrode film 28d and the second upper electrode film 28e instead of the iridium oxide films.
The first ferroelectric capacitor 28A and the second ferroelectric capacitor 28B formed as such are heated, for example, at 550° C. to 700° C. for 60 minutes in an oxygen-containing atmosphere to recover the damage on the first capacitor insulating film 28b and the second capacitor insulating film 28c composed of PZT.
According to the structure illustrated in
Next, as illustrated in
Another interlayer insulating film 31 is formed on the entire surface of the barrier film 30 by plasma-enhanced CVD using, for example, TEOS as the raw material as illustrated in
Referring to
In this state, for example, a heat treatment at 450° C. is performed for 60 minutes in an oxygen atmosphere to release the water in the interlayer insulating films 29 and 31 through the contact holes 31A and 31B. Such removal of water through contact holes is called “stack effect”. Although not illustrated in the drawing, in the step illustrated in
Since the heat treatment in the step illustrated in
When the heat treatment temperature after formation of the contact holes 31A and 31B is high, the lower electrically conductive oxide film of the upper electrode, i.e., the iridium oxide film having a non-stoichiometric composition IrOx or the strontium oxide film having a non-stoichiometric composition, tends to undergo abnormal growth. Thus, the heat treatment temperature in the step illustrated in
In the step illustrated in
Next, as illustrated in
Referring now to
Instead of the TiN film, a TaN film may be formed as the barrier metal film 32. However, when a tungsten film is formed on TaN by CVD, reliability problems such as corrosion may arise. Thus, in forming a TaN film as the barrier metal film 32, a TiN film is preferably formed on the TaN film so that the barrier metal film 32 has a two-layer structure including a first barrier metal film 32a and a second barrier metal film 32b illustrated in
Next, in the step illustrated in
In the step illustrated in
In the steps illustrated in
In the step illustrated in
As described earlier, a hydrogen gas is used as the reductant gas in the step of
Next, referring to
Referring to
Then additional interlayer insulating films and contact plugs are formed as needed to form a desired multilevel wiring structure.
In this embodiment also, the steps illustrated in
In this embodiment, ruthenium oxide films, strontium ruthenium oxide films, strontium titanate films, etc., may be used as the first upper electrode film 28d and the second upper electrode film 28e instead of the iridium oxide films.
The previous embodiments are directed to FeRAMs; however, the technology disclosed in this application may be widely applied to other types of semiconductor and electronic apparatuses.
A third embodiment will now be described with reference to
Referring to
The gate electrode 43 as well as the side wall insulating film is covered with a first interlayer insulating film 44. Via plugs 44A and 44B composed of tungsten or the like are formed in the first interlayer insulating film 44 to respectively contact the source diffusion region 41a and the drain diffusion region 41b.
A second interlayer insulating film 45 is formed on the first interlayer insulating film 44. In the state illustrated in
In the step illustrated in
In the step illustrated in
Referring now to
A magnesium oxide (MgO) film, for example, 1.16 nm in thickness is formed on the second pinned layer 48d also by sputtering or the like, and serves as a tunneling insulating film 48e. A CoFeB film having magnetization that changes in response to the external magnetic field is formed on the magnesium oxide (MgO) film 48e. The CoFeB film has a thickness of, for example, 1.5 nm, is deposited by, for example, sputtering, and serves as a free layer 48f.
A ruthenium (Ru) film 49a, for example, 10 nm in thickness and a ruthenium oxide (RuOx) film 49b, for example, 30 nm in thickness that constitute an upper electrode 49 are sequentially deposited on the free layer 48f by sputtering. Instead of the ruthenium oxide (RuOx) film 49b, an iridium oxide (IrOx) film, a strontium titanate (SrTiO3) film, a strontium ruthenium oxide (SrRuO3) film, or the like may be used.
Referring now to
Next, as illustrated in
In the step illustrated in
In the step illustrated in
In the step illustrated in
In the step illustrated in
In the step illustrated in
In the step illustrated in
Next, in the step illustrated in
In the step illustrated in
In the step illustrated in
Although the detailed description is omitted here, a multilayer wiring structure is formed on the structure illustrated in
The steps illustrated in
In this embodiment also, an iridium oxide film, a strontium ruthenium oxide film, a strontium titanate film, or the like may be used instead of the ruthenium oxide (RuOx) film 49b included in the upper electrode 49.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment(s) of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Number | Date | Country | Kind |
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2009-126811 | May 2009 | JP | national |