Patent Application
20160086956
The present invention relates to a semiconductor device and to a method for manufacturing a semiconductor device.
Miniaturization of semiconductor devices such as dynamic random access memories (DRAMs) has progressed in recent years. There are problems when the gate length of a transistor employed in a DRAM is reduced in that the short channel effect of the transistor becomes pronounced and there is a reduction in the threshold voltage. Furthermore, there is an increase in the junction leakage current when the impurity concentration of a semiconductor substrate is increased in order to limit a reduction in the threshold voltage of the transistor. When a DRAM memory cell is miniaturized, deterioration of the refresh characteristics is therefore a serious problem.
A trench-gate transistor in which a gate electrode is embedded in a trench formed in the surface side of a semiconductor substrate is known as a structure for avoiding problems such as those mentioned above. By using a trench-gate transistor, it is possible to ensure that the gate length of a transistor employed in a DRAM is sufficiently large in physical terms. Furthermore, it is possible to realize a DRAM having miniaturized memory cells with a minimum processing dimension of no greater than 60 nm.
However, as semiconductor devices become even smaller, a new problem has become evident in that, when contact plugs are formed in order to provide conduction between the gate electrodes of a trench-gate transistor and a capacitor or upper electrode etc., short circuiting is likely to occur between the gate electrodes and the contact plugs as a result of part of an embedded insulating film formed beforehand in the trench being excessively etched.
Various semiconductor devices and methods for manufacturing said semiconductor devices are being investigated in order to solve new problems such as that mentioned above. For example, Patent Document 1 describes a semiconductor device and a method for manufacturing a semiconductor device, the method comprising the following steps: a step in which an embedded insulating film comprising borophosphosilicate glass is formed on a gate electrode (buried word line) within a gate electrode-formation trench (referred to below simply as a “trench”); a step in which an interlayer insulating film is formed on the embedded insulating film and a semiconductor substrate; and a step in which a contact opening reaching the embedded insulating film and the surface of the adjacent semiconductor substrate is formed in the interlayer insulating film by means of etching.
Specifically, as shown in FIG. 9-FIG. 11 of Patent Document 1, an embedded insulating film 72 comprising borophosphosilicate glass (BPSG) is deposited by means of CVD on a liner film 71 formed in a trench groove 65. After this, a silicon nitride mask film and part of the embedded insulating film 72 and liner film 71 are removed by means of an etching and planarization step employing CMP, and the embedded insulating film 72 is formed in such a way that the surface thereof is at a comparable height with the silicon surface of a semiconductor substrate 50. Patent Document 1 indicates that the boron (B) concentration of the BPSG is preferably in the range of 10.5-11.0 mol %, and the ratio of the boron (B) concentration and the phosphorus (P) concentration is preferably 2.34-2.76, from the point of view of improving etching resistance.
During the manufacture of a semiconductor device such as a DRAM having a trench-gate transistor, the embedded insulating film is formed on the gate electrode, after which a capacitance contact opening is formed using photolithography and dry etching in such a way as to adjoin the embedded insulating film and the semiconductor substrate. Here, the capacitance contact opening and the surrounding area are washed by means of wet etching employing a chemical solution such as hydrofluoric acid. The BPSG described in Patent Document 1 has a certain degree of resistance to wet etching, but it may be considerably removed during the abovementioned washing process. When the embedded insulating film on the gate electrode is removed, the gate electrode short circuits with a capacitance contact plug which is subsequently formed. Although it is possible to reduce the thickness of the gate electrode with respect to the thickness of the trench in order to maintain a margin of insulation in the gate electrode, this leads to the problem of an increase in the electrical resistance of the gate electrode.
In this regard, it was thought feasible to reliably avoid short circuiting between the gate electrode and the capacitance contact plug by employing, as the embedded insulating film, an insulating film formed by means of a high-density plasma (HDP) method, which has excellent properties such as high resistance to hydrofluoric acid etching. When an insulating film formed by means of an HDP method is used however, the edge portions at the upper end of the gate electrode-formation trench (referred to below simply as the “trench”) which has a high aspect ratio are removed by the sputtering effect. There is thus a problem in that it is impossible to ensure an adequate margin of insulation in the gate electrode, due to the fact that the insulating film cannot be readily embedded in the trench.
A semiconductor device according to the present invention comprises: a trench formed in one surface of a semiconductor substrate; a gate electrode formed in a lower part of the trench with a gate insulating film interposed; a side wall insulating film comprising a nitride film formed on an inner wall of the trench on the gate electrode; and an embedded insulating film which is formed within the trench enclosed by the side wall insulating film on the gate electrode, wherein the side wall insulating film has a shape which increases in width toward a bottom part of the trench.
A method for manufacturing a semiconductor device according to the present invention comprises the following steps: a trench formation step in which a trench is formed in one surface of a semiconductor substrate; a gate insulating film formation step in which a gate insulating film is formed at a lower part of an inner wall of the trench; a gate electrode formation step in which a gate electrode is formed at a lower part of the trench with the gate insulating film interposed; a side wall insulating film formation step in which a side wall insulating film comprising a nitride film which increases in width toward a bottom part of the trench is formed on an inner wall of the trench on the buried word line; and an embedded insulating film formation step in which an embedded insulating film is formed within the trench enclosed by the side wall insulating film on the gate electrode.
According to the present invention, the interior angle formed by one surface of a semiconductor substrate at an upper end of a trench and an inner wall of a side wall insulating film is an obtuse angle, so a mortar-shaped space is formed within the trench on the gate electrode. As a result, it is possible to use, as an embedded insulating film, an insulating film which has outstanding etching characteristics even though it cannot be readily embedded in the trench, and said film may be embedded in the space inside the trench on the gate electrode. The etching resistance of the embedded insulating film is therefore improved, and there is no removal of the embedded insulating film when contact plugs and wiring adjoining the embedded insulating film and semiconductor substrate are formed, even if wet etching or chemical washing etc. is performed, so it is possible to maintain the insulating properties of the gate electrodes while also being able to reliably avoid short circuiting of the contact plugs or wiring.
A method for manufacturing a semiconductor in accordance with the present invention will be described in detail below with reference to
The DRAM (semiconductor device) 101 shown in
The DRAM 101 is provided with a plurality of memory cell arrays. In
It should be noted that
As shown in
The gate insulating film 107 is formed in such a way as to cover a lower part of an inner wall of two trenches 106 provided in each active region K. The inner surface layer 108 is formed on the inside of the gate insulating film 107. A silicon dioxide film and a titanium nitride film may be used as the gate insulating film 107 and the inner surface layer 108, respectively, for example.
The gate electrode 109 functions as a word line in the trench-gate transistor and is formed by an upper portion 109B and a lower portion 109A. The lower portion 109A is formed in such a way as to fill the inside of the trench 106 enclosed by the gate insulating film 107 and the inner surface layer 108. The upper portion 109B is formed in such a way as to fill the inside of the trench 106 enclosed at a lower part of a side wall insulating film 110 to be described later. Tungsten may be used as the material of the upper portion 109B and the lower portion 109A, for example. The height of the gate electrode 109 is set in accordance with the refresh characteristics of the DRAM 101 and the height of the trench 106, among other things.
The side wall insulating film 110 is formed above the gate electrode 109 in such a way as to cover an upper part of the inner wall of the trench 106. A nitride film formed by means of atomic layer deposition (ALD) may be used as the material of the side wall insulating film 110 of the DRAM 101. Furthermore, the side wall insulating film 110 increases in width toward a bottom part of the trench 106 and has a quasi-tapered shape. The quasi-tapered shape of the side wall insulating film 110 is set to take account of the refresh characteristics of the DRAM 101 and the width of the trench 106, among other things.
A lower part of the side wall insulating film 110 is interposed between the upper portion 109B of the gate electrode 109 and the semiconductor substrate 105. By virtue of this arrangement, the depth of the gate electrode 109 can be adequately maintained and insulating properties are ensured, while an increase in the electrical resistance of the gate electrode 109 is also suppressed. It should be noted that the electrical resistance of the gate electrode 109 may be reduced if the lower portion 109A is sufficiently deep. In this case, the gate electrode 109 may comprise only the lower portion 109A.
The embedded insulating film 111 is formed above the gate electrode 109 in a mortar-shaped internal space of the trench 106 enclosed by the upper part of the side wall insulating film 110. A silicon dioxide film which is formed using an HDP method may be used as the embedded insulating film 111. A silicon dioxide film formed by means of an HDP method has extremely good resistance to wet etching which is used in the process of manufacturing the DRAM 101, such as removal of a silicon nitride mask film which is formed beforehand on the semiconductor substrate 105, formation of contact plugs or wiring, and surface washing. The embedded insulating film 111 of the DRAM 101 therefore has higher resistance to wet etching than a conventional film.
The semiconductor substrate 105 lying between the two gate electrodes 109, i.e. the central part of the active region K, forms a source/drain region of the trench-gate transistor, and the bit line 115 is connected thereto. Meanwhile, the semiconductor substrate 105 on the opposite side to the side on which the bit line 115 is connected with respect to the gate electrode 109 forms a source/drain region of the trench-gate transistor, the capacitance contact plug 119 is connected thereto, and the capacitor 147 is connected thereabove. An impurity diffusion region is preferably provided in the semiconductor substrate 105 where the source/drain regions of the trench-gate transistor are formed. When a p-type silicon substrate is used as the semiconductor substrate 105, the impurity diffusion region is formed by means of ion implantation of an n-type impurity dopant such as arsenic or phosphorus, for example.
The bit line 115 adjoins a surface 105a of the semiconductor substrate 105 and the upper surface of the embedded insulating film 111, and is formed in such a way as to extend in the X-direction. The bit line 115 has a two-layer structure comprising a bottom conductive film 130 made of polysilicon and a metallic film 131 made of a high-boiling-point metal such as tungsten, for example, but this is not limiting. An upper insulating film 32 such as a silicon nitride film is formed on the bit line 115. An insulating film 133 comprising a silicon nitride film or the like is formed on both sides in the width direction of the bit line 115. It should be noted that a bit line contact plug may be disposed between the bit line 115 and the semiconductor substrate 105.
The capacitance contact plug 119, which has a rectangular shape in plan view, adjoins the surface 105a of the semiconductor substrate 105 which is not in contact with the bit line 115, and adjoins the upper surface of the embedded insulating film 111. The capacitance contact plug 119 has a three-layer structure comprising a bottom conductive film 140 made of polysilicon or the like, a silicide layer 141 comprising CoSi or the like, and a metallic film 142 such as tungsten, for example, but this is not limiting. An insulating film 137 comprising a silicon nitride film or the like is formed on both sides in the width direction of the capacitance contact plug 119.
An interlayer insulating film 143 comprising a silicon dioxide film or the like is formed between the bit line 115 and the capacitance contact plug 119. The upper surfaces of the bit line 115, capacitance contact plug 119 and interlayer insulating film 143 are formed in such a way as to lie at the same height. The upper part of the bit line 115 and the capacitance contact plug 119 constitutes a capacitor formation region of the DRAM 101, and capacitance contact pads 118 having a circular shape in plan view are formed in a staggered manner on the capacitance contact plugs 119 in such a way as to be partially overlapping. A stopper film 121 is formed on both sides in the width direction of each capacitance contact pad 118. An interlayer insulating film 146 comprising a silicon dioxide film or the like is formed on the stopper film 121. The capacitor 147 is formed within the interlayer insulating film 146 in such a way as to be positioned above the capacitance contact pad 118.
The capacitor 147 comprises a lower electrode 148, a capacitance insulating film 149 and an upper electrode 150. The lower electrode 148 is a cylindrical electrode portion formed on the capacitance contact pad 118. The capacitance insulating film 149 is formed in such a way as to extend from the inner surface of the lower electrode 148 over the interlayer insulating film 146. The upper electrode 150 is formed in such a way as to fill the inside of the lower electrode 148 while also extending to the upper surface of the capacitance insulating film 149. It should be noted that the structure of the capacitor 147 described is merely an example and there is no particular limitation; another capacitor structure which is conventionally used in a semiconductor device, such as a crown shape, may equally be employed.
An interlayer insulating film 151 comprising a silicon dioxide film or the like is provided on the upper electrode 150. Furthermore, upper metal wiring 152 comprising aluminum or copper, and an interlayer insulating film 154 comprising a silicon dioxide film or the like are provided on the interlayer insulating film 151.
It should be noted that a peripheral circuit region (not depicted) may be disposed around the memory cell array described above of the DRAM 101.
A method for manufacturing the DRAM 101 will be described next with reference to
A semiconductor substrate 105 comprising a p-type silicon substrate is first of all prepared, and a silicon dioxide film 103 and a silicon nitride mask film 104 are stacked in succession on a surface 105a of the semiconductor substrate 105. It should be noted that the semiconductor substrate 105 which is used may be a semiconductor substrate in which P-type wells are provided beforehand by means of ion implantation in a region in which a trench-gate transistor is formed.
The silicon dioxide film 103, silicon nitride film 104 and semiconductor substrate 105 are then patterned using photolithography and dry etching, and element isolation trenches (not depicted) for defining active regions K are formed in the surface 105a of the semiconductor substrate 105. As shown in
Element isolation regions 113 for isolating the strip-like active regions K in a direction parallel to gate electrodes 109, i.e. the Y-direction, are formed by means of the same process, as shown in
After this, a low-concentration n-type impurity dopant such as arsenic or phosphorus is preferably ion-implanted in the surface 105a of the semiconductor substrate 105 in the active regions K, and a low-concentration impurity diffusion layer (not depicted) functioning as a source/drain region of the trench-gate transistor is preferably formed. It should be noted that the step in which the low-concentration impurity diffusion layer is formed may be omitted.
The silicon dioxide film 103, silicon nitride film 104 and semiconductor substrate 105 are then etched using photolithography and dry etching in order to form trenches 106 for forming buried gate electrodes, as shown in
A gate insulating film 107 comprising a silicon dioxide film or the like is then formed on an inner wall of the trench 106 using thermal oxidation. After this, an inner surface layer 108 comprising titanium nitride is formed on the inside of the gate insulating film 107 and a tungsten layer (not depicted) is embedded. The thickness of the gate insulating film 107 and the inner surface layer 108 may be set at 5 nm in both cases, for example.
The tungsten layer which is not depicted, the inner surface layer 108 and the gate insulating film 107 are then etched so as to remain in the lower part of the trench 106. A lower portion 109A of a gate electrode 109 comprising tungsten is formed as a result, as shown in
A liner film 161 comprising a silicon nitride film or the like is then formed over the lower portion 109A in such a way as to cover an exposed upper part of the inner wall of the trench 106, as shown in
As shown in
As shown in
An upper part of the antireflection film 172 and the tungsten layer 170 is then etched back until a bottom part upper surface 170a of the tungsten layer 170 in the trench 106 is exposed. As a result, the gate electrode 109 is formed by joining of the lower portion 109A which is enclosed by the laminated film comprising the gate insulating film 107 and the inner surface layer 108, except on the upper surface thereof, and an upper portion 109B which is enclosed at the side surface by a bottom part of the side wall insulating film 110, as shown in
A mortar-shaped internal space in the trench 106 enclosed by a portion above the bottom part of the side wall insulating film 110 is then filled with a silicon dioxide film (not depicted) using an HDP method. After this, the upper surface of the silicon dioxide film is planarized to form an embedded insulating film 111, as shown in
The silicon nitride film 104 is then removed using wet etching to expose the upper surface of the silicon dioxide film 103, as shown in
The upper part of the side wall insulating film 110 and the silicon dioxide film 103 are then removed by means of CMP, as shown in
An interlayer insulating film 143 is then formed from a silicon dioxide film or the like in such a way as to cover the semiconductor substrate 105. It should be noted that the interlayer insulating film 143 may be a composite film formed by stacking a plurality of materials. After this, part of the interlayer insulating film 143 is removed by means of photolithography and dry etching, as shown in
An insulating film 133 is then formed from a silicon nitride film on an inner wall of the bit line opening 176. After this, n-type impurity dopant may be ion-implanted in the surface 105a of the semiconductor substrate 105 exposed at a bottom surface of the bit line opening 176, and a high-concentration impurity diffusion layer (not depicted) may be formed in the region of the surface 105a of the semiconductor substrate 105.
A laminated film comprising a bottom conductive film 130 made of polysilicon or the like and a metallic film 131 made of a high-boiling-point metal such as tungsten is then embedded inside the bit line opening 176 to form a bit line 115. The bit line 115 is formed in a pattern extending in a direction intersecting the gate electrodes 109, i.e. the X-direction shown in
Part of the interlayer insulating film 143 is then removed using photolithography and dry etching, and capacitance contact openings 187 are formed. The positions in which the capacitance contact openings 187 are formed is set in such a way as to be adjacent to each trench 106 and adjoining the surface 105a of the semiconductor substrate 105 on the side not in contact with the bit line 115. That is to say, positions corresponding to capacitance contact plug formation regions 117 in the case of the structure previously described in relation to
An insulating film 137 comprising a silicon nitride film is then formed on an inner wall of the capacitance contact opening 187. After this, the surface 105a of the semiconductor substrate 105 exposed on a bottom surface of the capacitance contact opening 187 may be subjected to ion implantation in order to form an n-type impurity high-concentration diffusion layer (not depicted) in the region of the surface 105a of the semiconductor substrate 105.
A phosphorus-containing polysilicon film is then deposited in the capacitance contact opening 187, after which etch-back is performed and the polysilicon film is allowed to remain at the bottom part of the capacitance contact opening 187 in order to form a bottom conductive film 140. After this, a silicide layer 141 such as cobalt silicide (CoSi) is formed on the surface of the bottom conductive film 140, and a metallic film 142 such as tungsten is deposited in such a way as to fill the capacitance contact opening 187. Surface planarization is performed by means of CMP until the surfaces of the silicon nitride film 180 and the interlayer insulating film 143 are exposed, and the metallic film 142 is left only inside the capacitance contact opening 187. A capacitance contact plug 119 having a three-layer structure comprising the bottom conductive film 140, silicide layer 141, and metallic film 142 is formed in this way, as shown in
After this, capacitance contact pads 118 and a stopper film 121 are formed on the structure shown in
A capacitor 147, interlayer insulating films 146, 151, 154, and upper metal wiring 152 are then formed on the capacitance contact pads 118 and stopper film 121 using means which are well known in conventional methods for manufacturing a DRAM. It should be noted that there is no particular limitation as to the type or shape of the capacitor 147.
The DRAM 101 is completed by means of the steps described above.
The DRAM 101 according to this mode of embodiment has a shape in which the width of the side wall insulating film 110 increases toward the bottom of the trench, i.e. a quasi-tapered shape, so the interior angle θ1 formed by the surface 105a of the semiconductor substrate 105 in the region of the upper end of the trench 106 and the inner wall of the side wall insulating film 110 is an obtuse angle, and a mortar-shaped space is formed within the trench 106 on the gate electrode 109. As a result, it is possible to improve the ease with which the embedded insulating film formed on the gate electrode is embedded in said space. Accordingly, it is possible to use, as an embedded insulating film, an insulating film which has outstanding etching resistance even though it cannot be readily embedded due to the sputtering effect etc., such as a silicon nitride film employing an HDP method. Furthermore, it is possible to reliably maintain the insulating properties of the gate electrodes 109 while also being able to avoid short circuiting between the gate electrodes 109 and the capacitance contact plugs 119 or the bit lines 115. In addition, a field limiting effect is produced in the DRAM 101 by means of the side wall insulating film 110, and the refresh characteristics are improved.
Furthermore, by virtue of the method for manufacturing the DRAM 101 according to this mode of embodiment, a mortar-shaped space enclosed by the side wall insulating film 110 is formed inside the trench 106 on the gate electrode 109, as described above. As a result, it is possible to use an HDP method in order to embed the embedded insulating film 111, which has excellent etching resistance, inside the trench 106 on the gate electrode 109, without removing the upper end of the trench 106 due to the sputtering effect. This means that it is possible to form the bit line opening 176 and capacitance contact openings 187 by means of wet etching or treatment using a chemical solution or the like, without removing the embedded insulating film 111 when the bit lines 115 and the capacitance contact plug 119 are formed after the embedded insulating film 111 has been formed. It is thus possible to manufacture a DRAM 101 which reliably maintains the insulating properties of the gate electrodes and demonstrates the abovementioned advantages.
In addition, with the DRAM 101 and the method for manufacturing same according to this mode of embodiment, the etching removal resistance of the embedded insulating film 111 is improved, and as a result the upper portion 109B of the gate electrode 109 can extend inside the trench 106 enclosed by the bottom part of the side wall insulating film 110. That is to say, it is possible to increase the thickness of the gate electrode 109 while maintaining the insulating properties of the gate electrode 109. This makes it possible to reduce the electrical resistance without increasing the word line capacitance of the DRAM 101.
A DRAM (semiconductor device) 201 will be described as an example of a semiconductor device according to the second mode of embodiment.
The structure of the DRAM 201 according to the second mode of embodiment is the same as that of the DRAM 101 according to the first mode of embodiment. A description of the structure of the DRAM 201 will therefore not be given.
The difference between this mode of embodiment and the DRAM according to the first mode of embodiment lies in the process for forming the upper portion 109B of the gate electrode 109. This difference will be described in detail in a method for manufacturing the DRAM 201 (see below).
The method for manufacturing the DRAM 201 will be described below with the aid of
The same steps as in the method for manufacturing the DRAM 101, from preparation of the semiconductor substrate 105 until the side wall insulating film formation step, are carried out first of all.
A tungsten layer 175 is formed using CVD in such a way as to fill the mortar-shaped space enclosed by the side wall insulating film 110 on the lower portion 109A of the gate electrode 109 and in such a way as to extend over the silicon nitride film 104, as shown in
The upper part of the tungsten layer 175 is then etched back in such a way as to remain at a predetermined thickness on the bottom part of a mortar-shaped space enclosed by the lower portion 109A and the upper portion 109B of the gate electrode 109. As a result, the gate electrode 109 is formed by joining of the lower portion 109A which is enclosed by the laminated film comprising the gate insulating film 107 and the inner surface layer 108, except on the upper surface thereof, and the upper portion 109B which is enclosed at the side surface by a bottom part of the side wall insulating film 110, as shown in
A mortar-shaped internal space in the trench 106 enclosed by an exposed portion of the upper portion 109B of the gate electrode 109 and the side wall insulating film 110 is then filled with the embedded insulating film 111 comprising a silicon dioxide film using an HDP method. Here, the interior angle θ2 formed by the surface 105a of the semiconductor substrate 105 in the region of the upper end of the trench 106 and the inner wall of the side wall insulating film 110 is an obtuse angle, and therefore there is no risk of the upper end of the side wall insulating film 110 being removed by the sputtering effect produced by the HDP method. Furthermore, it is possible to improve the ease of embedding the embedded insulating film 111 in the mortar-shaped internal space in the trench 106 enclosed by the exposed portion of the upper portion 109B of the gate electrode 109 and the side wall insulating film 110. It should be noted that the height of the upper surface of the embedded insulating film 111 can be aligned with the height of the surface 105a of the semiconductor substrate 105 using etch-back or the like, in the same way as in the DRAM 101.
Following this, the same steps as in the method for manufacturing the DRAM 101 are performed for the bit line formation step and subsequent steps. The DRAM 201 is completed as a result.
The DRAM 201 and method for manufacturing same according to this mode of embodiment achieve the same advantages as the DRAM 101 and method for manufacturing same. It is therefore possible to reliably maintain the insulating properties of the gate electrodes 109 of the DRAM 201 and to avoid short circuiting between the gate electrodes 109 and the capacitance contact plugs 119 or bit lines 115. Furthermore, a field limiting effect can be produced in the DRAM 201 by means of the side wall insulating film 110, and the refresh characteristics can be improved. In addition, the gate electrodes 109 comprise the lower portion 109A and the upper portion 109B, and it is possible to reduce the electrical resistance without increasing the word line capacitance of the DRAM 201.
Preferred modes of embodiment of the present invention have been described above but the present invention is not limited to these specific modes of embodiment and a number of variations and modifications may be made within the essential scope of the present invention as set forth in the claims.
65 . . . Trench groove; 101, 201 . . . DRAM (semiconductor device); 103 . . . Silicon dioxide film; 104, 180 . . . Silicon nitride film; 50, 105 . . . Semiconductor substrate; 105a . . . Surface; 106 . . . Trench; 107 . . . Gate insulating film; 108 . . . Inner surface layer; 109 . . . Gate electrode; 109A . . . Lower portion; 109B . . . Upper portion; 110 . . . Side wall insulating film; 72, 111 . . . Embedded insulating film; 113, 158 . . . Element isolation region; 115 . . . Bit line; 118 . . . Capacitance contact pad: 121 . . . Stopper film; 130, 140 . . . Bottom conductive film; 131, 142 . . . Metallic film; 133, 137 . . . Insulating film; 141 . . . Silicide layer; 143, 146, 151, 154 . . . Interlayer insulating film; 147 . . . Capacitor; 148 . . . Lower electrode; 149 . . . Capacitance insulating film; 150 . . . Upper electrode; 152 . . . Upper metal wiring; 71, 161 . . . Liner film; 170, 175 . . . Tungsten layer; 172 . . . Antireflection film; 176 . . . Bit line opening; 187 . . . Capacitance contact opening; K . . . Active region; θ1, θ2 . . . Interior angle
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-095862 | Apr 2013 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2014/061586 | 4/16/2014 | WO | 00 |
