Patent Application
20070298573
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
As shown in
In the step 100, the gate dielectric layer can be, for example but not limited to, selected from a group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, material with a dielectric constant higher than that of silicon dioxide or the combination thereof. Furthermore, the gate dielectric layer can be, for example, made of material with high a dielectric constant such as ZrO2, Si3N4 or HfSiNO.
In the step 102, by using the patterned cap layer as a mask, the polysilicon layer is patterned to form a polysilicon gate. The method for patterning the polysilicon layer can be, for example, a dry etching process in which the surface of the device is bombarded by plasma to perform the so-called ion bombardment to remove a portion of the polysilicon exposed by the patterned cap layer.
In the step 104, several lightly doped drain (LDD) regions are formed in the substrate adjacent to the polysilicon gate so as to form a channel region in the substrate between the LDD regions. Because of the formation of the LDD regions, the hot electron effect on the short channel metal-oxide semiconductor device can be alleviated. The material of the channel region can be, for example, selected from a group consisting of monocrystalline silicon, epitaxial silicon, germanium, germanium silicon, carbon silicon or the combination thereof.
The purpose of the step 106 is to form a spacer on the sidewall of the polysilicon gate. It should be noticed that when the materials of the spacer and the cap layer are the same, the spacer can be removed at the time the cap layer is removed. On the other hand, if the spacer is made of a material different from the material of the cap layer, the spacer and the cap layer should be removed in different steps.
Thereafter, in the step 108, a source/drain region is formed in the substrate adjacent to the spacer. There are two ways to form the source/drain region. One is an ion implantation process and the other is a selective epitaxial deposition process. In the selective epitaxial deposition process, a portion of the substrate aside the spacer and the polysilicon gate is removed to form a recession and then an epitaxy layer is formed in the recession to be the source/drain region. Further, this epitaxial deposition process includes a vapor phase epitaxy process. Besides, before the spacer is formed, a thin liner layer can be formed on the sidewall of the gate. After the source/drain region is formed, a thermal annealing process or an epitaxial annealing process is performed.
Then, in the step 110, a cap layer is removed. Thereafter, in the step 112, the spacer is removed. As mentioned above, when the cap layer is made of a material different from the material of the spacer, the step 110 and the step 112 should be performed individually. On the other hand, when the cap layer and the spacer are made of the same material, the step 110 and the step 112 can performed together.
In the step 114, a metal silicidation process is performed for completely transforming the polysilicon gate into a metal silicide gate and forming a metal silicide layer on the surface of the source/drain region. In this metal silicidation process, a metal layer, such as a nickel layer, a titanium layer or a cobalt layer, is formed over the surface of the device and then a thermal process is performed on the metal layer to initialize a silicidation on a portion of the silicon in contact with the metal so as to form the metal silicide layer. The material of this metal silicide layer can be nickel silicide, titanium silicide or cobalt silicide. Then, the rest portion of the metal layer which is not reacted with the silicon is removed.
After the step 114, a contact etching stopper layer is formed over the substrate to adjust the stress of the semiconductor device.
In the first embodiment, the semiconductor device possesses the gate made of metal silicide so that the poly-depletion effect and the boron penetration happening in the conventional device with the polysilicon gate can be avoided. Moreover, the chemical mechanical polish process is not involved with the manufacturing process according to the present invention so that the uniformity of the wafer can be improved and the efficiency and the simplification of the manufacturing process can be well improved as well.
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As shown in 3I, after the second metal silicidation process, a contact etching stopper layer 316 can be selectively formed to cover the substrate 300 to adjust the stress of the semiconductor device.
The second embodiment uses two-step metal silicidation process which is different from the first embodiment. When the metals used in the two metal silicidation processes are the same, the source/drain region is metal silicidized at the time the polysilicon gate is metal silicidized. It should be noticed that the silicidation depth of the source/drain region is proportional to the silicidation depth of the polysilicon gate. Since the thickness of the polysilicon gate is about 60˜120 nanometers which is much thicker than the source/drain region, the metal silicidizing the polysilicon gate and the source/drain region at the same time leads to over metal silicidation phenomenon of the source/drain region.
In the second embodiment, by using two-step metal silicidation process and properly removing the patterned cap layer, the aforementioned over metal silicidation phenomenon can be avoided. Furthermore, by using the selective epitaxial deposition process, the growing-upward source/drain with a relatively large thickness can be obtained. The advantage of this kind of structure is that the thick source/drain region can be used to balance the over metal silicidation during one-step metal silicidation process is performed. Therefore, the efficiency and the simplification of the manufacturing process can be well improved.
As shown in 4, the material of the substrate 400 can be, for example, selected from a group consisting of monocrystalline silicon, epitaxial silicon, germanium, germanium silicon, carbon silicon or the combination thereof. Furthermore, the substrate 400 can be also a bulk substrate or silicon-on-insulator substrate. Moreover, the material of the gate dielectric layer 402 can be, for example, selected from a group consisting of silicon oxide, silicon nitride, silicon oxy-nitride, a material with a dielectric constant higher than the silicon dioxide and the combination thereof. Additionally, the gate dielectric layer 402 can be, for example, made of material with high a dielectric constant such as ZrO2, Si3N4 or HfSiNO. The material of the channel region 408 can be, for example, selected from a group consisting of monocrystalline silicon, epitaxial silicon, germanium, germanium silicon, carbon silicon or the combination thereof.
As for the formation of the source/drain region 406, the selective epitaxial deposition process is used to form the source/drain region 406 in this embodiment. In the selective epitaxial deposition process, a portion of the substrate 400 aside the LDD region 407 is removed to form a recession and then an epitaxy layer with a certain thickness is formed in the recession to complete the so-called recess epitaxy process. Alternatively, the selective epitaxial deposition for forming the source/drain region 406 comprises directly depositing the epitaxy layer on the surface of the substrate 300 to complete the so-called planner epitaxy process without forming any recession. Moreover, when the epitaxial deposition process is used to form the source/drain region 406, the thickness of the source/drain region 406 should be slightly larger than that of the metal silicide gate 412 to prevent the source/drain region 406 from being over metal silicidized during the metal silicidation process. In this embodiment, the material of the metal silicide gate 412 can be either as same as or different from the material of the metal silicide layer 414. Additionally, a contact etching stopper layer can be also formed to cover the substrate 400 to adjust the stress of the semiconductor device. In addition, outside of the source/drain region 406 further comprises an isolation structure 416 formed on the substrate 400. Moreover, the structure shown in
Altogether, in the method of the present invention, the gate is transforming into the metal silicide gate by using the metal silicidation process so that the problems of applying the polysilicon gate and metal gate onto the small size semiconductor device can be overcome. In addition, by using two-step metal silicidation process, the patterned cap layer and the spacer can be properly removed to overcome the problem of simultaneously metal silicidation of the gate and the source/drain region and the problem of over metal silicidation of the source/drain region. Furthermore, when the patterned cap layer is made of a material as same as the material of the spacer, the patterned cap layer and the spacer can be removed in the same step so as to simplify the manufacturing process.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.
