Semiconductor device and method of fabricating the same

Abstract

A semiconductor device according to one embodiment of the present invention includes: a fin including a buffer layer made of SiGe and formed on a Si layer, and a SiGe layer formed on the buffer layer, the SiGe layer having a Ge concentration corresponding to a Ge concentration of the buffer layer in an interface between the buffer layer and the SiGe layer; a gate electrode formed on a side face of the fin through a gate insulating film; a channel region formed in a region within the fin facing the gate electrode through the gate insulating film, the channel region being selectively provided within the SiGe layer of the buffer layer and the SiGe layer included in the fin; and a source region and a drain region formed within the fin, the channel region being formed between the source region and the drain region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a p-channel FinFET as a semiconductor device according to a first embodiment of the present invention;

FIGS. 2A to 2P are respectively perspective views showing processes for fabricating the p-channel FinFET according to the first embodiment of the present invention;

FIGS. 3A to 3C are respectively perspective views showing processes for fabricating a p-channel FinFET according to a second embodiment of the present invention;

FIGS. 4A to 4K are respectively cross sectional views showing processes for fabricating an n-channel FinFET and a p-channel FinFET according to a third embodiment of the present invention;

FIG. 5 is a cross sectional view showing a substrate in which different layers are epitaxially grown in a p-channel FinFET region and an n-channel FinFET region on a Si layer according to a fourth embodiment of the present invention; and

FIGS. 6A to 6P are respectively cross sectional views showing processes for fabricating a FinFET and a planar type FET according to a fifth embodiment of the present invention.

Claims

1. A semiconductor device, comprising: a fin including a buffer layer made of SiGe and formed on a Si layer, and a SiGe layer formed on the buffer layer, the SiGe layer having a Ge concentration corresponding to a Ge concentration of the buffer layer in an interface between the buffer layer and the SiGe layer;a gate electrode formed on a side face of the fin through a gate insulating film;a channel region formed in a region within the fin facing the gate electrode through the gate insulating film, the channel region being selectively provided within the SiGe layer of the buffer layer and the SiGe layer included in the fin; anda source region and a drain region formed within the fin, the channel region being formed between the source region and the drain region.

2. A semiconductor device according to claim 1, further comprising an isolation layer for isolating a semiconductor element region comprising the fin, the channel region, and the source region and the drain region formed therein from any of other semiconductor element regions, a surface of the isolation layer being located in a position higher than that of the interface between the buffer layer and the SiGe layer.

3. A semiconductor device according to claim 1, wherein the Ge concentration of the buffer layer increases substantially along a height direction.

4. A semiconductor device according to claim 1, wherein the SiGe layer has the Ge concentration substantially equal to the Ge concentration of the buffer layer in the interface between the SiGe layer and the buffer layer.

5. A semiconductor device according to claim 1, wherein the Ge concentration in an inner central portion of the SiGe layer is smaller than that in a surface of the SiGe layer.

6. A semiconductor device according to claim 1, wherein the fin has a high impurity concentration in its portion located below with respect to the channel region.

7. A semiconductor device according to claim 1, further comprising a transistor including a fin made of a Si crystal containing therein no Ge, the transistor being formed on the Si layer.

8. A semiconductor device according to claim 1, further comprising a transistor having a planar structure, the transistor being formed on the Si layer.

9. A semiconductor device, comprising: a p-channel transistor having a first fin including a first buffer layer made of SiGe and formed on a Si layer, and a first SiGe layer formed on the first buffer layer, the first SiGe layer having a Ge concentration corresponding to a Ge concentration of the first buffer layer in an interface between the first buffer layer and the first SiGe layer, a first gate electrode formed on a side face of the first fin through a first gate insulating film, a first channel region formed in a region within the first fin facing the first gate electrode through the first gate insulating film, the first channel region being selectively provided within the first SiGe layer of the first buffer layer and the first SiGe layer included in the first fin, and a first source region and a first drain region formed within the first fin, the first channel region being formed between the first source region and the first drain region; andan n-channel transistor having a second fin formed on the Si layer, a second gate electrode formed on a side face of the second fin through a second gate insulating film, a second channel region formed in a region within the second fin facing the second gate electrode through the second gate insulating film, the second channel region having a Ge concentration smaller than that of the first channel region, and a second source region and a second drain region formed within the second fin, the second channel region being formed between the second source region and the second drain region.

10. A semiconductor device according to claim 9, further comprising an isolation layer for isolating the p-channel transistor and the n-channel transistor from each other, a surface of the isolation layer being located in a position higher than that of the interface between the first buffer layer and the first SiGe layer.

11. A semiconductor device according to claim 9, wherein the Ge concentration of the first buffer layer increases substantially along a height direction.

12. A semiconductor device according to claim 9, wherein the second fin is made of a Si crystal containing therein no Ge.

13. A semiconductor device according to claim 9, wherein the second fin comprises a second buffer layer made of SiGe and formed on the Si layer, and a second SiGe layer formed on the second buffer layer, the second SiGe layer having a Ge concentration corresponding to a Ge concentration of the second buffer layer in an interface between the second buffer layer and the second SiGe layer.

14. A semiconductor device according to claim 13, wherein the first SiGe layer has the Ge concentration substantially equal to that of the first buffer layer in the interface between the first SiGe layer and the first buffer layer, and the second SiGe layer has the Ge concentration substantially equal to that of the second buffer layer in the interface between the second SiGe layer and the second buffer layer.

15. A semiconductor device according to claim 13, wherein the Ge concentration in an inner central portion of the first SiGe layer is smaller than that in a surface of the first SiGe layer.

16. A semiconductor device according to claim 15, wherein the second SiGe layer has an approximately uniform Ge concentration.

17. A method of fabricating a semiconductor device, comprising: patterning a substrate formed by laminating a Si layer, a buffer layer made of SiGe, and a SiGe layer having a Ge concentration corresponding to a Ge concentration of the buffer layer in an interface between the buffer layer and the SiGe layer in predetermined shape to form a fin;oxidizing surfaces of the buffer layer and the SiGe layer of the fin to form an oxide layer in order to increase the Ge concentration of the fin;removing the oxide layer by performing etching;forming a gate insulating film on a side face of the fin from which the oxide layer is removed by performing the etching;forming a gate electrode on the side face of the fin through the gate insulating film; andimplanting ions into the fin by using the gate electrode as a mask to form a source region and a drain region.

18. A method of fabricating a semiconductor device according to claim 17, wherein the buffer layer is formed by utilizing an epitaxial method so that its Ge Concentration increase substantially in a height direction.

19. A method of fabricating a semiconductor device according to claim 17, wherein the SiGe layer is formed so as to have the Ge concentration substantially equal to that of the buffer layer in the interface between the SiGe layer and the buffer layer.

20. A method of fabricating a semiconductor device according to claim 17, wherein when the Ge concentration of the fin is increased, the oxide layer is formed by performing low-temperature oxidation so that the Ge concentration in an inner central portion of the fin becomes smaller than that in a surface of the fin.