Patent Application
20080197429
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-037393, filed on Feb. 19, 2007; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device using a metal silicate insulating film as a gate insulating film and a method of manufacturing the same.
2. Background Art
Downscaling large-scale integrated circuits requires thinning of the gate insulating film. In a silicon oxide film or a silicon oxynitride film used conventionally, increasing a leak current caused from film thinning limits the film thinning. Hence, it is proposed that degradation in current driving capability in a transistor is suppressed while suppressing the leak current by using a metal silicate film or its nitride film with a dielectric constant higher than that of the silicon oxide film or silicon oxynitride film for the gate insulating film to increase a physical film thickness. Among metal silicate films, a hafnium silicate film is superior to other materials in high thermal stability and high carrier mobility, and is under development. For example, Japanese Patent Application Disclosure JP-A 2005-217272 (Kokai) discloses the gate insulating film based on a HfSiON film.
However, when the HfSiON film is used as the gate insulating film and polycrystalline silicon is used as the gate electrode, hafnium reacts with silicon, thereby resulting in silicidization of the gate electrode. Such silicidization may cause variation of a threshold value voltage.
Furthermore, with downscaling, adoption of a nickel silicide gate electrode producing no gate depletion layer instead of polycrystalline silicon is also proposed. However, when the nickel silicide gate electrode containing boron as an impurity is combined with the hafnium silicate insulating film, nickel contained in the gate electrode penetrates the gate insulating film and diffuses into the silicon substrate, thereby causing the increase of the gate leak current.
According to an aspect of the invention, there is provided a semiconductor device including: a silicon oxide film; a metal silicate insulating film provided on the silicon oxide film and having a higher dielectric constant than the silicon oxide film; and a gate electrode provided on the metal silicate insulating film, a composition ratio of a metal element in the metal silicate insulating film on a side closer to the gate electrode being lower than a composition ratio of the metal element in the metal silicate insulating film on a side closer to the silicon oxide film.
According to another aspect of the invention, there is provided a semiconductor device including: a metal silicate insulating film; a silicon nitride film provided on the metal silicate insulating film; and a nickel silicide gate electrode provided on the silicon nitride film, at least a part of the nickel silicide gate electrode containing boron.
According to a still another aspect of the invention, there is provided a method of manufacturing a semiconductor device, including: depositing a metal silicate insulating film on a silicon oxide film by supplying a metal source gas, a silicon source gas and an oxygen source gas to a surface of the silicon oxide film, the metal silicate insulating film having a higher dielectric constant than the silicon oxide film, and forming a gate electrode on the metal silicate insulating film, the depositing including reducing the supplying amount of the metal source gas during deposition of the metal silicate insulating film.
Embodiments of the invention will now be described with reference to the drawings.
The semiconductor device according to the embodiment has the MIS (Metal Insulator Semiconductor) structure provided with a gate electrode 8 via gate insulating films 5 through 7 on a silicon layer (silicon substrate) 1.
In the superficial portion of the silicon layer 1, a deep impurity diffusion region 2a and a shallow impurity diffusion region 2b with an opposite conductivity type to the superficial portion are formed selectively. These impurity diffusion regions 2a and 2b are formed in a self-aligning way by an ion implantation process using the MIS structure portion as a mask and a following thermal diffusion process. The impurity diffusion region 2a functions as a source/drain region, and its surface has a metal silicon compound region 3 formed thereon for decreasing the resistance.
The superficial portion of the silicon layer 1 between impurity diffusion regions 2b functions as a channel formation region and the gate electrode 8 is provided via the gate insulating films 5 through 7 on this channel formation region. A side wall insulating film 9 illustratively made of oxidized silicon is provided on side walls of the gate electrode 8 and the gate insulating films 5 through 7.
In this embodiment, a silicon oxide film and a metal silicate insulating film (including nitride) as a so-called high-k film having a higher dielectric constant than the silicon oxide film are used for the gate insulating film. The metal silicate insulating film is, for example, a hafnium silicate insulating film, for further details a HfSiON film containing nitrogen.
A silicon oxide film 5 illustratively formed by a thermal oxidation method is formed on the surface of the channel formation region. The HfSiON film 6 having a Hf/(Hf+Si) ratio of illustratively 50% or more is formed on the silicon oxide film 5, and the HfSiON film 7 having a Hf/(Hf+Si) ratio less than that of the HfSiON film 6 is formed on the HfSiON film 6. The gate electrode 8 illustratively made of polycrystalline silicon is formed on the HfSiON film 7.
The HfSiON films 6, 7 are obtained by nitridation treatment of the HfSiON film after formation of the HfSiON film by a MOCVD (Metal Organic Chemical Vapor Deposition) method, for example.
For example, a silicon wafer (the silicon oxide film 5 is formed on its surface) heated to 650° C. is placed on a susceptor, the HfSiON film having a high Hf composition ratio is formed at first by supplying, for example, tetradiethylaminohafnium as hafnium source gas, for example, diethylsilane as silicon source gas, and oxygen onto the surface, and then the HfSiON film having a lower Hf composition ratio than the HfSiON film having the high Hf composition ratio is formed continuously on the HfSiON film having the high Hf composition ratio by reducing the amount supplied of the hafnium source gas during the formation of HfSiON films.
In this process, the HfSiON film having the low Hf composition ratio can be formed on the HfSiON film having the high Hf composition ratio by only varying the amount of supply of the hafnium source gas, and the HfSiON film having the high Hf composition ratio formed in advance is not damaged. It is noted that the HfSiON film is not limited to the MOCVD method to be formed, but may be formed by an ALD (Atomic Layer Deposition) method and a sputtering method or the like.
The formation of the HfSiON films is followed by the nitridation treatment. Nitrogen is introduced into the HfSiON films by a plasma nitridation method or an ammonia nitridation method supplying ammonia gas onto the surface of the heated wafer, for example, hereafter anneal treatment is performed in nitrogen gas containing oxygen gas in a ratio of 0.1 percent, for example. Then the HfSiON films 6, 7 are obtained.
Hafnium atom diffusion from the HfSiON film 6 having the high Hf composition ratio to the silicon oxide film 5 and the HfSiON film 7 having the low Hf composition ratio is not observed and a three layers structure having relatively clear boundaries between the silicon oxide film 5, the HfSiON film 6 and the HfSiON film 7 can be confirmed.
The horizontal axis represents a depth (nm) along the substrate direction in assuming the boundary level between the gate electrode 8 and the HfSiON film 7 having the low Hf composition ratio as a reference (zero), and the vertical axis represents an atomic percent of each atom, Si, O, Hf and N. Moreover, in
In this embodiment, the HfSiON films 6, 7 having a higher dielectric constant than the silicon oxide film 5 are provided on the silicon oxide film 5, thus degradation of current driving capability can be suppressed by realizing a film thickness electrically equivalent to a thin oxide film while an insulating film thickness (physical film thickness) being thick in order to suppress a leak current. From this viewpoint, it is preferable that the Hf/(Hf+Si) ratio in the HfSiON film 6 having the high Hf composition ratio on the side in contact with the silicon oxide film 5 is greater than or equal to 50 percent.
Furthermore, in this embodiment, a reaction between hafnium and polycrystalline silicon (polysilicon) as a gate electrode material can be suppressed by reducing the Hf composition ratio in the HfSiON film 7 on the side in contact with the gate electrode 8 less than the Hf composition ratio in the HfSiON film 6 on the side in contact with the silicon oxide film 5. Consequently variation (increase) of threshold value voltage due to silicidization of the gate electrode 8 can be suppressed.
The inventors found, as a consequence of diligent discussion, that an effect enough to suppress the variation of the threshold value voltage is obtained for the Hf/(Hf+Si) ratio in the HfSiON film 7 being less than or equal to 6 percent. Moreover, it is also found that decreasing the Hf/(Hf+Si) ratio less than or equal to 1 percent causes increase of the leak current. Therefore, it is preferable that the Hf/(Hf+Si) ratio in the HfSiON film 7 on the side in contact with the gate electrode 8 is from 1 percent to 6 percent inclusive.
As described previously, while the HfSiON films 6, 7 are formed by the nitridation of the HfSiON film after the formation of the HfSiON film of two layers having different Hf composition ratios in advance, nitrogen is likely to form a bond to silicon, thus the structure is obtained, which much nitrogen piles up in the HfSiON film 7 containing more content of silicon and being in contact with the gate electrode 8 of polysilicon. That is, nitrogen can be located away from the channel formation region, and carrier mobility in the channel can be improved.
As shown in
It is shown that providing the HfSiON film (Low-Hf layer) 7 having the low Hf composition ratio on the side in contact with the gate electrode suppresses a reaction of hafnium between polycrystalline silicon of the gate electrode, causes a shift of the threshold value voltage of the p-type MIS structure to a positive direction, and the pinning of the Fermi energy is suppressed.
These
It is noted that the gate electrode 8 may be based on, for example, tungsten (W), ruthenium (Ru), tantalum carbide (TaC), titanium nitride (TiC), tantalum nitride (TiN), rhenium (Re) or the like other than polycrystalline silicon.
The semiconductor device according to the embodiment has the MIS structure provided with a gate electrode 38 via gate insulating films 26, 27 on a silicon layer (silicon substrate) 21.
In the superficial portion of the silicon layer 21, a deep impurity diffusion region 22 and a shallow impurity diffusion region 20 with an opposite conductivity type to the superficial portion are formed selectively. These impurity diffusion regions 22 and 20 are formed in a self-aligning way by an ion implantation process using the MIS structure portion as a mask and a following thermal diffusion process. The impurity diffusion region 22 functions as a source/drain region, and its surface has a metal silicon compound region 23 formed thereon for decreasing the resistance.
In the n-type MIS structure 40a, the conductivity type of the superficial portion of the silicon layer 21 is p-type, and the n-type impurity diffusion region (source/drain region) 22 is formed on its surface. In the p-type MIS structure 40b, the conductivity type of the superficial portion of the silicon layer 21 is n-type, and the p-type impurity diffusion region (source/drain region) 22 is formed on its surface.
The superficial portion of the silicon layer 21 between the impurity diffusion regions 20 functions as the channel formation region and the gate electrode 38 is provided via the gate insulating films 26, 27 on this channel formation region. A side wall insulating film 29 illustratively made of oxidized silicon is provided on the side wall of the gate electrode 38 and the gate insulating films 26, 27, and an interlayer insulating film 30 is provided so as to cover the side wall insulating film 29.
In this embodiment, a metal silicate insulating film (including nitride) as a so-called high-k film having a higher dielectric constant than the silicon oxide film is used for the gate insulating film. The metal silicate insulating film is, for example, a hafnium silicate insulating film, for further details a HfSiON film containing nitrogen.
A silicon oxide film 25 illustratively formed by the thermal oxidation method is formed on the surface of the channel formation region as shown in
The gate electrode 38 is formed on the HfSiON film 27. The gate electrode 38 is a nickel silicide gate electrode obtained by a silicidization reaction of nickel diffused from an upper portion, after deposition and fabrication of polycrystalline silicon.
First an element isolation region 24 is formed in a superficial portion of a silicon layer (silicon substrate) 21. This is formed as follows.
A silicon nitride film serving as a mask is formed via a buffer film on a surface of the silicon layer 21. Next the silicon nitride film, the buffer film and the silicon layer 21 are etched selectively to a specified depth using a patterned resist. After the resist is removed and a silicon oxide film is deposited over the entire surface, its surface is planarized by a CMP (Chemical Mechanical Polishing) method, for example. Hereafter the element isolation region 24 with a STI (Shallow Trench Isolation) structure is obtained by removing the silicon nitride mask.
Next, after pretreatment using dilute hydrofluoric acid, an interface layer of a silicon oxide film is formed by slightly oxidizing the substrate surface. Then a hafnium silicate (HfSiON) film with a thickness of about 3 (nm) having a Hf/(Hf+Si) ratio greater than or equal to 50 percent is illustratively deposited by the MOCVD method. As necessary, the film property of the deposited hafnium silicate film is improved by heat treatment such as annealing including oxygen and nitridation treatment, and a HfSiON film 26 is formed. After that, a hafnium silicate film with a thickness of about 1 (nm) having a Hf/(Hf+Si) ratio of about 10 percent is deposited on the HfSiON film 26 using the same film formation method, and the film property is improved by the heat treatment and the like as required, then a HfSiON film 27 is formed.
Next, a polycrystalline silicon film 28 is deposited on the entire surface of the HfSiON film 27. The thickness of the polycrystalline silicon film 28 is, for example, 100 (nm). It is noted that amorphous silicon may be used instead of polycrystalline silicon.
Next, as shown in
Next, after ion implantation is used for an extension region (LDD: Light Doped Drain region), a side wall insulating film 29 (
Then, annealing is performed for recovery of damage caused by the ion implantation and activation of impurities. Thus a shallow impurity diffusion region (extension region) 20 and a deep impurity diffusion region (source/drain region) 22 are formed as shown in
Next, a thin silicon nitride film liner is deposited on the entire surface and furthermore, an insulating film 30 (
When polycrystalline silicon with diffused nickel is silicidized for adopting the hafnium silicate insulating film as the gate insulating film, boron illustratively contained in the gate electrode of the p-type MIS structure segregates to the gate insulating film interface and boron concentration in the vicinity of the interface increases. This causes a problem where nickel in the gate electrode penetrates the gate insulating film to diffuse into the silicon substrate as shown by a TEM image of
However, in this embodiment, the HfSiON film 27 having the low Hf composition ratio (the Hf/(Hf+Si) ratio is less than or equal to 30 percent) is provided on the side of the gate insulating film in contact with the gate electrode. Therefore, it can be suppressed that nickel contained in the gate electrode penetrates the gate insulating film and diffuses into the silicon substrate, thus producing no trouble such as a gate leak. As a result, the gate structure of which films are thinned while assuring a low leak current can be formed with a high yield.
In this embodiment, on formation of the hafnium silicate film, first the silicon substrate surface is exposed and the interface oxide film is formed, and subsequently the hafnium silicate film is deposited. At this time, controlling (decreasing gradually) the flow amount supplied of the hafnium source gas allows the hafnium silicate film to be formed, the film having the reduced composition ratio of Hf on the surface side serving as the interface between the gate electrode. The Hf composition ratio on the surface side of the hafnium silicate film is low, but its film thickness is thick. Therefore, the heat treatment for improving the film property allows the hafnium silicate film to have performance equivalent to the hafnium silicate insulating film with constant Hf concentration by illustratively controlling the heat treatment time and nitridation time.
Moreover, the Hf composition ratio in the hafnium silicate film is varied only by controlling the amount supplied of the hafnium source gas, therefore, film damage can be suppressed.
Also in this embodiment, the Hf composition ratio on the side of the gate insulating film in contact with the gate electrode is low. Therefore, it can be suppressed that nickel contained in the gate electrode penetrates the gate insulating film and diffuses into the silicon substrate, thus producing no trouble such as the gate leak.
In this embodiment, a metal silicate insulating film (including nitride) and a silicon nitride film as a so-called high-k film having a higher dielectric constant than the silicon oxide film are used for the gate insulating film.
The silicon oxide film 25 illustratively formed by the thermal oxidation method is formed on the surface of the channel formation region as shown in
The gate electrode 38 is formed on the silicon nitride film 37. The gate electrode 38 is the nickel silicide gate electrode obtained by causing the silicidization reaction of nickel diffused from the upper portion after deposition and processing of polycrystalline silicon.
According to this embodiment, the silicon nitride film containing no Hf is provided on the side of the gate insulating film in contact with the gate electrode. Therefore, it can be suppressed that nickel contained in the gate electrode penetrates the gate insulating film and diffuses into the silicon substrate, thus producing no trouble such as the gate leak. Moreover, the silicon nitride film has an advantage in its capability to be formed at a low temperature so as to keep a channel profile of a transistor steep.
The inventors measured leak currents for each structure, the structure (the second, third embodiments) provided with the HfSiON film (Low-Hf layer) 27 having the low composition ratio of Hf on the side of the gate insulating film in contact with the gate electrode, the structure (the fourth embodiment) provided with the silicon nitride film 37 on the side of the gate insulating film in contact with the gate electrode, and the structure (comparative example) not provided with the HfSiON film 27 having the low composition ratio of Hf in the gate insulating film of the second embodiment.
This result indicates that providing the HfSiON film (Low-Hf layer) 27 having the low composition ratio of Hf and the silicon nitride film 37 on the side of the gate insulating film in contact with the gate electrode makes it possible to reduce the leak current significantly compared with not providing these films (comparative example).
In the second through third embodiments previously described, a method for silicidization of the gate electrode is not limited in particular. For example, the thermal process for silicidization may be performed in a plurality of separate steps as well as one step annealing. In this case, the necessary amount of nickel and silicon may be different from the amount in one step annealing. Moreover, the necessary amount of nickel varies with a relationship between the formed silicide composition and polycrystalline silicon, but has no dependence specifically. Furthermore, all portions of the gate electrode are not needed to be completely silicidized (full silicidization), and a structure with nickel in contact with a part of the substrate surface and boron existing therein may be approved. In that case, the structure may not always serve as the gate electrode of a transistor.
In the planarization process of the interlayer insulating film (oxide film) 30 shown in
An SOI (Silicon On Insulator) substrate having a silicon activated layer formed on the insulating film as well as a normal silicon substrate can be used for the substrate. Surface orientation of the substrate is not limited, and a substrate where silicon is grown using the silicon substrate as a seed may be used.
Moreover, the invention can be applied to a transistor having a multilevel structure in the channel gate electrode portion such as a Fin-type as well as a planar transistor.
Furthermore, in the invention, Aluminum (Al), Yttrium (Y), Zirconium (Zr), Tantalum (Ta) or the like can be also used for a metal in the metal silicate insulating film other than Hafnium (Hf). It is supposed that even if those metal silicate insulating films is used, the same effect as that obtained for using the hafnium silicate insulating film described above is obtained.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-037393 | Feb 2007 | JP | national |
