This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-052403, filed Mar. 16, 2015, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a method of manufacturing the same.
As semiconductor devices are miniaturized, interconnects are similarly miniaturized. When the width or height of an interconnect becomes closer to the mean free path of electrons, an increase in the resistance rate caused by the interface inelastic scattering of electrons becomes a serious problem.
In order to solve the above-described problem, interconnects using graphene have been proposed. In the case of using an interconnect made of graphene, it is possible to further reduce resistance by introducing dopant such as a halogen compound into graphene.
However, there is a problem that the dopant the graphene interconnect is doped with is likely to escape from the end face of the graphene interconnect.
Therefore, there is demand for a structure and a method of manufacturing the same which do not allow dopant to escape from a graphene interconnect easily.
Further, a graphene film is generally formed on a layer of a catalytic metal such as cobalt or nickel. However, there is a problem that dopant such as a halogen compound corrodes or etches the catalytic metal.
Therefore, there is demand for a structure which can prevent an undesirable influence of dopant on a catalytic layer.
In general, according to one embodiment, a method of manufacturing a semiconductor device, the method includes: forming a graphene film on a catalytic layer; removing a part of the graphene film to form an exposed side surface of the graphene film; introducing dopant into the graphene film from the exposed side surface; and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.
Embodiments will be described hereinafter with reference to the accompanying drawings.
First, as shown in
Next, on the region in which the interlayer insulating film 11 and the contact 12 are formed, an underlying conductive layer 13 is formed by physical vapor deposition (PVD). The underlying conductive layer 13 is made of titanium (Ti), tantalum (Ta), ruthenium (Ru) or tungsten (W), or a metal nitride or a metal oxide thereof.
On the underlying conductive layer 13, a catalytic layer 14 is then formed by PVD. The catalytic layer 14 contains a metal element selected from cobalt (Co), nickel (Ni), iron (Fe), ruthenium (Ru) and copper (Cu). More specifically, the catalytic layer 14 is formed of a cobalt layer, a nickel layer, an iron layer, a ruthenium layer or a copper layer. The catalytic layer 14 functions as a catalyst for forming a graphene film. In order to form an even graphene film, the catalytic layer 14 is preferably a continuous film having a thickness of 0.5 nm or more.
On the catalytic layer 14, a graphene film 15 is then formed by chemical vapor deposition (CVD). More specifically, the graphene film 15 is formed by plasma CVD or thermal CVD at a temperature of 450° C. or more. As the source gas for CVD, methanol, ethanol, acetylene or the like is used. For the graphene film 15, multilayer graphene formed of a plurality of stacked graphite layers is used.
On the graphene film 15, a hard mask 16 is then formed. The hard mask 16 is made of a silicon oxide film or a silicon nitride film.
Next, as shown in
Next, as shown in
Next, as shown in
In introducing the dopant into the graphene film 15, the catalytic layer 14 is protected from the dopant since the compound layer 18 is formed on the side surface of the catalytic layer 14. Therefore, even in the case of using halogen dopant having high reactivity, it is still possible to prevent the catalytic layer 14 from being corroded or etched by the dopant.
Next, as shown in
Then, as shown in
Subsequently, as shown in
As described above, according to the present embodiment, dopant is introduced into the graphene film 15 from the side surface of the trench (step) 17 formed in the graphene film 15 and the like, and then the graphene film 15a into which the dopant is introduced is patterned to form a graphene interconnect. If the dopant is introduced into the graphene film after the graphene film is patterned, most of the dopant escapes from the graphene film, and thus a graphene interconnect having low resistance cannot be obtained. In the present embodiment, since the dopant is introduced into the graphene film before the graphene film is patterned, most of the dopant remains in the graphene film without escaping therefrom. Therefore, it is possible in the present embodiment to prevent the escape of the dopant from the graphene film and to obtain a graphene interconnect having low resistance.
Further, the trench (step) 17 is formed in a region of the graphene film 15 not used as an interconnect. In the portion in which the trench (step) 17 is formed, the dopant may escape from the exposed side surface of the graphene film 15. However, there is no problem even if the dopant escapes from the exposed side surface because the portion in which the trench (step) 17 is formed is not used as an interconnect.
Still further, in the present embodiment, predetermined processing is applied to the exposed portion (side surface) of catalytic layer 14 to form the compound layer 18 made of a compound of the main element contained in the catalytic layer 14. The compound layer 18 is selectively formed on a predetermined surface of the catalytic layer 14 (side surface of the catalytic layer 14 in the present embodiment) which is not covered with the graphene film 15. Therefore, in introducing the dopant into the graphene film 15, the corrosion or the etching of the catalytic layer 14 by the dopant can be effectively prevented.
Next, modified examples of the present embodiment will be described.
As shown in
Also in the method of the present modified example, the corrosion or the etching of the catalytic layer 14 by the dopant can be prevented in a manner similar to that of the above-described embodiment.
Note that, in etching the graphene film 15 in the present modified example, the upper portion of the catalytic layer 14 is also etched to some extent. If the upper portion of the catalytic layer 14 is not etched, there is a possibility that the side surface of the graphene film 15 is partly covered with the compound layer 18. As a result, there is a possibility of decreasing the efficiency of introducing the dopant into the graphene film 15. By etching the upper portion of the catalytic layer 14, this problem can be prevented.
First, through processes similar to those of
Next, as shown in
Then, a first protective film 23 which covers the graphene interconnect 15a and the like is formed. For the first protective insulating film 23, a silicon nitride film, a silicon oxide film, a silicon oxynitride film or the like can be used. The first protective insulating film 23 is formed without exposing the graphene interconnect 15a to the air after the graphene interconnect 15a is formed by patterning the graphene film 15a into which the dopant is introduced. By forming the first protective insulating film 23 immediately after forming the graphene interconnect 15a in this way, the escape of the dopant from the graphene interconnect 15a can be effectively prevented. Further, since the dopant in the graphene interconnect 15a does not react with oxygen or water in the air, it is possible to retain the dopant in the graphene interconnect 15a more effectively.
Subsequently, as shown in
Next, as shown in
Also in the present embodiment, the basic structure and the basic manufacturing method are similar to those of the first embodiment, and therefore an effect similar to that produced by the first embodiment can be achieved.
Further, in the present embodiment, the side surface of the graphene interconnect 15a is covered with the first protective insulating film 23 as well as the second protective insulating film 21 which covers the first protective insulating film 23. The first protective insulating film 23 is provided on the side surface of the graphene interconnect 15a and is not provided on the side surface of the catalytic layer 14. Therefore, the portion of the protective insulating film provided on the side surface of the graphene interconnect 15a is thicker than the portion of the protective insulating film provided on the side surface of the catalytic layer 14. In the present embodiment, since the side surface of the graphene interconnect 15a is covered with a thick protective insulating film (protective insulating films 21 and 23), the escape of the dopant from the graphene interconnect 15a can be prevented effectively.
Still further, by using different insulating films for the first protective insulating film 23 and the second protective film 21, it is possible to realize a more effective protective function for the graphene interconnect 15a. For example, with the first protective insulating film 23 formed of a silicon nitride film, the oxidation of the graphene interconnect 15a can be prevented effectively. Further, with the second protective insulating film formed of a silicon oxide film, the escape of the dopant from the graphene interconnect 15a can be prevented effectively.
Note that, although the trench 17 is provided to introduce dopant into the graphene film in the above-described first and second embodiments, it is also possible to adopt any structure other than the trench 17 as long as the structure includes a step to expose the side surface of the graphene film.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2015-052403 | Mar 2015 | JP | national |