semiconductor device and process for producing the same

Abstract

A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of the basic structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention in which stressing films overlap.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention in which stressing films are apart from each other.

FIGS. 4 and 5 are schematic cross-sectional and plan views of an essential portion of a CMOS structure according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of the basic structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention in which stressing films overlap.

FIG. 8 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention in which stressing films are apart from each other.

FIGS. 9 and 10 are schematic cross-sectional and plan views of an essential portion of a CMOS structure according to the second embodiment of the present invention.

FIGS. 11 to 13 are schematic cross-sectional views of the basic structures of semiconductor devices according to a third embodiment of the present invention in which a portion of the etching stopper films is dispensed with.

FIG. 14 is a schematic cross-sectional view of the basic structure of a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 15 to 16 are schematic cross-sectional views of essential layers formed in intermediate steps in a process for producing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 17 is an electron micrograph of a cross section of a structure in which stressing films and a resist layer are formed, and isotropic etching is performed by use of the resist layer as a mask.

FIGS. 18A to 18F are schematic cross-sectional views of examples of a first type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 19A to 19F are schematic cross-sectional views of examples of a second type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 20A to 20F are schematic cross-sectional views of examples of a third type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 21A to 21F are schematic cross-sectional views of examples of a fourth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 22A to 22F are schematic cross-sectional views of examples of a fifth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 23A to 23F are schematic cross-sectional views of examples of a sixth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 24A to 24F are schematic cross-sectional views of examples of a seventh type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 25A to 25F are schematic cross-sectional views of examples of an eighth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching without use of isotropic etching.

FIGS. 26A to 26F are schematic cross-sectional views of examples of a ninth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIGS. 27A to 27F are schematic cross-sectional views of examples of a tenth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIGS. 28A to 28F are schematic cross-sectional views of examples of an eleventh type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIGS. 29A to 29F are schematic cross-sectional views of examples of a twelfth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIGS. 30A to 30F are schematic cross-sectional views of examples of a thirteenth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIGS. 31A to 31F are schematic cross-sectional views of examples of a fourteenth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIGS. 32A to 32F are schematic cross-sectional views of examples of a fifteenth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIGS. 33A to 33F are schematic cross-sectional views of examples of a sixteenth type of arrangement of stressing films and a contact-hole formation region in the stage before formation of a contact hole, where the stressing films are dividedly formed by use of anisotropic etching and isotropic etching.

FIG. 34 is a graph indicating a relationship between the arrangement of stressing films and the yield rate.

FIG. 35 is a schematic cross-sectional view of an essential portion of a CMOS structure in a stage before formation of stressing films.

FIG. 36 is a schematic cross-sectional view of the essential portion of the CMOS structure in a stage in which a first etching stopper film is formed.

FIG. 37 is a schematic cross-sectional view of the essential portion of the CMOS structure in a stage in which a first stressing film and a second etching stopper film are formed.

FIG. 38 is a schematic cross-sectional view of the essential portion of the CMOS structure in a first etching stage.

FIG. 39 is a schematic cross-sectional view of the essential portion of the CMOS structure in a stage in which a second stressing film and a third etching stopper film are formed.

FIG. 40 is a schematic cross-sectional view of the essential portion of the CMOS structure in a second etching stage.

FIG. 41 is a schematic cross-sectional view of the essential portion of the CMOS structure in which an interlayer insulation film is formed.

FIGS. 42 and 43 are schematic cross-sectional and plan views of a first example of the essential portion of the CMOS structure including a contact-hole formation region.

FIG. 44 is a schematic cross-sectional view of a second example of the essential portion of the CMOS structure including a contact-hole formation region.

FIG. 45 is a schematic cross-sectional view of a third example of the essential portion of the CMOS structure including a contact-hole formation region.

Claims

1. A semiconductor device having a contact structure, comprising: a conductive region;a first film and a second film which are formed over said conductive region to realize a layer; anda contact electrode which extends through said layer to said conductive region, and is formed so as to replace a portion of said layer with a portion of the contact electrode, where the portion of the layer is constituted by only said first film, only said second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

2. The semiconductor device according to claim 1, wherein said portion of the layer has a first cross-sectional area, and said portion of the first film has a second cross-sectional area which is equal to or greater than half of the first cross-sectional area.

3. The semiconductor device according to claim 1, further comprising an etching stopper film formed over at least one of said first film and said second film for use in etching of layers formed over the first film and the second film.

4. The semiconductor device according to claim 3, wherein said etching stopper film is formed over only said second film, and said contact electrode is formed through the first film or both of said portion of the first film and said portion of the second film.

5. The semiconductor device according to claim 1, wherein said conductive region is a gate electrode common to a first transistor and a second transistor, and said first film and said second film are arranged to cover the first transistor and the second transistor, respectively.

6. The semiconductor device according to claim 5, wherein said first film and said second film are stressing films which apply stress to said first transistor and said second transistor, respectively.

7. The semiconductor device according to claim 5, wherein a boundary region between said first film and said second film is placed out of a boundary between said first transistor and said second transistor to one of the first transistor and the second transistor.

8. The semiconductor device according to claim 5, wherein a position at which said contact electrode is formed is placed out of a boundary between said first transistor and said second transistor to one of the first transistor and the second transistor.

9. The semiconductor device according to claim 5, wherein a boundary region between said first film and said second film is placed out of a boundary between said first transistor and said second transistor to one of the first transistor and the second transistor, and a position at which said contact electrode is formed is placed out of the boundary between said first transistor and said second transistor to the other of the first transistor and the second transistor.

10. A process for producing a semiconductor device having a contact structure, comprising the steps of: (a) forming a conductive region;(b) forming a first film and a second film over said conductive region to realize a layer;(c) forming a contact hole extending to said conductive region through said layer so as to remove a portion of said layer, where the portion of the layer is constituted by only said first film, only said second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer; and(d) forming a contact electrode in said contact hole.

11. The process according to claim 10, wherein said portion of the layer has a first cross-sectional area, and said portion of the first film has a second cross-sectional area which is equal to or greater than half of the first cross-sectional area.

12. The process according to claim 10, wherein said step (b) includes the substeps of, (b1) forming said first film over a structure containing said conductive region,(b2) removing a first part of said first film by etching so as to leave a second part of the first film,(b3) forming said second film over said structure after said steps (b1) and (b2) are performed, and(b4) removing a first part of said second film by etching so as to leave a second part of the second film, where the first part of said second film is located over said second part of the first film, andsaid step (c) includes the substeps of,(c1) determining a region in which said contact hole is to be formed, in consideration of misalignment occurring in a boundary region between said first film and said second film, and(c2) forming said contact hole in said region determined in said substep (c1).

13. The process according to claim 10, wherein said step (b) includes the substeps of, (b1) forming said first film over a structure containing said conductive region,(b2) forming an etching stopper film on said first film,(b3) removing a first part of said etching stopper film on a first part of said first film and the first part of the first film by etching so as to leave a second part of the etching stopper film and a second part of the first film,(b4) forming said second film over said structure after said steps (b1) to (b3) are performed, and(b5) removing a first part of said second film formed over said second part of the etching stopper film by etching so as to leave a second part of the second film.

14. The process according to claim 10, wherein said conductive region is a gate electrode common to a first transistor and a second transistor, and said first film and said second film are arranged so as to cover the first transistor and the second transistor, respectively.

15. A process for producing a semiconductor device having a contact structure, comprising the steps of: (a) forming a conductive region over a semiconductor structure;(b) forming a first film over said conductive region to form a layer;(c) removing a first part of said first film so as to leave a second part of the first film;(d) forming a second film over said semiconductor structure after said steps (a) to (c) are performed;(e) depositing resist over a first part of said second film so that a second part of the second film is exposed;(f) performing isotropic etching by using said resist as a mask so as to remove said second part of said second film;(g) forming a contact hole which extends to said conductive region; and(h) forming a contact electrode in said contact hole.

16. The process according to claim 15, wherein said contact hole is formed by removing a region containing a boundary region between said first film and said second film after said isotropic etching is performed in said step (f).

17. The process according to claim 15, wherein in said step (e), said resist is deposited so that said first part of said second film overlies on a portion of said second part of the first film having a width smaller than a thickness of said second part of the second film.

18. The process according to claim 15, wherein said conductive region is a gate electrode common to a first transistor and a second transistor, and said first film and said second film are arranged so as to cover the first transistor and the second transistor, respectively.