This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to and the benefit of Korean Patent Application No. 10-2017-0178361, filed on Dec. 22, 2017, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.
Inventive concepts relate to a semiconductor device having a structure in which an insulating layer is formed under a metal interconnection, the metal interconnection formed on a via plug structure.
A 3-dimensional (3D) package technique in which a plurality of semiconductor chips are mounted in one package such as a multi-chip stacked package or a system in package is used.
A via plug structure vertically passing through a substrate (e.g. a die) is applied to implement a high-density, low-power, and high-speed thin-film 3D package.
Some example embodiments are directed to providing a semiconductor device having a structure in which an insulating layer is formed under an interconnection on a via plug structure for improving electrical characteristics and reliability of the semiconductor device.
A semiconductor device according to some example embodiments includes comprising a via plug on a substrate, and a metal layer at an end of the via plug, the metal layer connected to an interconnection layer. An insulating structure is under the metal layer, and the insulating structure has a different layered structure according to a positional relationship with the metal layer.
A semiconductor device according to some example embodiments includes semiconductor structure, a via plug formed to pass through at least partially the semiconductor structure, and a metal layer at an end of the via plug. A bottom surface adjacent to a side surface of the metal layer has a different depth according to a distance from the side surface.
A semiconductor device according to some example embodiments includes a substrate on which a photodiode is formed, an insulating layer on the substrate, a via plug passing through at least a portion of the substrate, and a metal layer formed on the via plug. An insulating structure comprising one or more layered structures is under the metal layer for interconnection.
The above and other objects, features and advantages of example embodiments will become more apparent to those of ordinary skill in the art by describing example embodiments thereof in detail with reference to the accompanying drawings, in which:
Referring to
The semiconductor structure according to some example embodiments may include unit devices 121 and a contact 122 on a front surface 110a of the substrate 110. A lower interlayer insulating film 120 may be on the front surface 110a of the substrate 110. An upper interlayer insulating film 150 may be on the lower interlayer insulating film 120. A package substrate 180 and a re-distribution layer 181 may be on a rear surface 110c of the substrate 110. The front surface 110a may be an active surface, and the rear surface 110c may be an inactive surface.
The substrate 110 may include a semiconductor substrate, for example, a silicon substrate. The front surface 110a of the substrate 110, on which the unit devices 121 and the contact 122 are formed, may be covered by the lower interlayer insulating film 120. The lower interlayer insulating film 120 may include silicon oxide (SiO2) and/or silicon nitride (SiN), and may be formed as a single layer or a multilayer.
The unit devices 121 may be formed on the front surface 110a of the substrate 110 by a front-end-of-line (FEOL) process. The unit devices 121 may be individual devices, and may include a metal-oxide-semiconductor field effect transistor (MOSFET), a system large scale integration (LSI) device, a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, and/or the like. The unit devices 121 may be electrically separated from each other by the lower interlayer insulating film 120 covering the unit devices 121.
The contact 122 may vertically pass through the lower interlayer insulating film 120 to transmit electrical signals to upper and lower structures of the lower interlayer insulating film 120. The contact 122 may include tungsten (W), aluminum (Al), and/or copper (Cu).
An etch stop layer 141 (see
The via hole 131 may be a trench formed by fully or partially etching the etch stop layer 141, the lower interlayer insulating film 120, and the substrate 110. The via hole 131 may be formed by applying a photoresist (PR) film on the etch stop layer 141, exposing the PR film using a mask pattern, and then etching the via hole 131 according to a shape of a photoresist. The via hole 131 may be formed using an anisotropic etching process, e.g. a Bosch process, or a laser drilling technique.
A buffer portion 132 and a conductive barrier film 133 may be sequentially formed on an inner surface of the via hole 131. The remaining space of the via hole 131 may be filled with a metal by electroplating and/or other deposition methods to form a via electrode 134 on the conductive barrier film 133. The via electrode 134 and a portion of an upper surface of the etch stop layer 141 may be polished by a chemical mechanical polishing (CMP) process. An additional insulating layer may be formed on the polished surface to form the insulating structure 140.
The upper interlayer insulating film 150 may be formed on the insulating structure 140, and an interconnection pattern may be formed by a back-end-of-line (BEOL) process.
The upper interlayer insulating film 150 may include silicon oxide (SiO2) or silicon nitride (SiN), and may be formed as a single layer or a multilayer. The interconnection pattern may be formed as a plurality of interconnection structures for connecting the unit devices 121 formed by an FEOL process to other interconnections on the substrate 110. For example, the interconnection structure may include a metal layer 153 for interconnection, a contact plug 154, and a metal interconnection layer 155.
Each of the metal layer 153 for interconnection, the contact plug 154, and the metal interconnection layer 155 may include at least one metal selected from among tungsten (W), aluminum (Al), and copper (Cu).
The metal layer 153 for interconnection may be formed by plating an interconnection hole 151 with a metal. The interconnection hole 151 may be formed by etching the insulating structure 140, the contact 122 at a lower end of the insulating structure 140, and a portion of the via plug 130.
An upper insulating film 160 may be formed at an upper end of the upper interlayer insulating film 150. The upper insulating film 160 may be a passivation layer including silicon nitride (SiN) and/or polyimide. Upper connection terminals 170, which are connected to front pads 156 at an uppermost end of the interconnection pattern through connection holes 161, may be on the upper insulating film 160.
A portion of a lower end of the via plug 130 may be removed from a rear surface 110b (see
The package substrate 180 including the re-distribution layer 181 may be connected to the rear surface 110c of the substrate 110, which is exposed by the CMP process. The exposed surface of the lower end of the via plug 130 may be connected to a connection terminal 182 by the re-distribution layer 181. The semiconductor device 100 according to example embodiments are not limited to the configuration described above with reference to
Among processes of manufacturing the semiconductor device 100 according to some example embodiments, processes from after the FEOL process to the process of forming the via plug 130 will be described below.
After an FEOL structure is formed on the front surface 110a of the substrate 110, the lower interlayer insulating film 120 may be on the front surface 110a of the substrate 110. The lower interlayer insulating film 120 may include silicon oxide (SiO2). The etch stop layer 141 may be formed on the surface of the lower interlayer insulating film 120. The etch stop layer 141 may be an insulating layer including silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), and/or the like.
After the etch stop layer 141 is formed, the etch stop layer 141, the lower interlayer insulating film 120, and a portion of the substrate 110 may be etched so as to pass therethrough to form a trench-shaped via hole 131. The buffer portion 132 and the conductive barrier film 133 may be formed, e.g. conformally formed, inside the via hole 131. The remaining space of the via hole 131 may be filled with a metal film to form the via electrode 134 on the conductive barrier film 133. The via plug 130 including the via electrode 134, the conductive barrier film 133, and the buffer portion 132 may be formed.
The buffer portion 132 may serve as a buffer for relieving stress, e.g. thermal stress, due to thermal expansion or the like of the via electrode 134. The buffer portion 132 may include an insulating material such as silicon oxide (SiO2) and silicon nitride (SiN). For example, the buffer portion 132 may be formed of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. The buffer portion 132 may be formed by a CVD process.
The conductive barrier film 133 may prevent a metal contained in the via electrode 134 from diffusing into the substrate 110. The conductive barrier film 133 may be formed as a conductive layer including a relatively low interconnection resistance. For example, the conductive barrier film 133 may include titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), ruthenium (Ru), cobalt (Co), manganese (Mn), nickel (Ni), and/or the like. The conductive barrier film 133 may be formed as a single layer or a multiplayer. The conductive barrier film 133 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and/or an atomic layer deposition (ALD) process.
The metal film constituting the via electrode 134 may be formed by electroplating a metal such as silver (Ag), gold (Au), copper (Cu), aluminum (Al), tungsten (W), indium (In), or the like. For example, the metal film may be made of copper (Cu), a copper-based alloy (Cu—Sn, Cu—Mg, Cu—Ni, Cu—Zn, Cu—Pd, Cu—Au, Cu—Re, or Cu—W), tungsten (W), or a tungsten-based alloy.
Although not illustrated, a metal seed layer may be formed on the conductive barrier film 133. The metal film may be grown from the metal seed layer by the electroplating to fill the via hole 131. The metal seed layer may be made of copper (Cu), a copper-based alloy (Cu—Co or Cu—Ru), cobalt (Co), nickel (Ni), or ruthenium (Ru).
Referring to
In the CMP process, the etch stop layer 141 may serve an etch stopper, and may have a relatively low etch rate, e.g. an etch rate lower than other films. The etch stop layer 141 may be an insulating layer made of a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, a silicon carbide (SiC) film, a silicon carbon nitride (SiCN) film, a silicon oxide (SiO2) film, and/or the like, which is formed by a CVD process. Since the insulating layer used as the etch stop layer 141 is removed by an etch-back process later, a cost may be reduced by using a low-cost material for the insulating layer. For example, a silicon nitride (SiN) film including a dielectric constant (k) greater than that of an oxide-based material may be used as the etch stop layer 141. The etch stop layer 141 and the via plug 130 may be exposed by cleaning residues formed by the CMP process.
Referring to
The first insulating layer 142 may be formed by depositing a silicon carbon nitride (SiCN) film, a silicon oxynitride (SiON) film, and/or the like, by a CVD and/or PVD method. As illustrated above, the upper end of the via electrode 134, which is a metal film, may protrude more than the etch stop layer 141 even after the CMP process. The first insulating layer 142 may also be formed at a higher position above the via electrode 134 than a position above the lower interlayer insulating film 120.
Referring to
Referring to
The first insulating layer 142 and the etch stop layer 141 on which the protective film 190 is not present may be removed by the etch-back process. The first insulating layer 142 and the etch stop layer 141 which are present under the protective film 190 may remain without being removed. Accordingly, there may be a height difference between a portion of the insulating structure 140 in which the protective film 190 is not present and a portion of the insulating structure 140 in which the protective film 190 is present. Referring to
Referring to
The insulating structure 140 may have a different layered structure according to a positional relationship with the via plug 130. As illustrated above, the insulating structure 140 may include the first insulating layer 142 and the second insulating layer 143 at the upper end of the via plug 130. The insulating structure 140 may include only the second insulating layer 143 in a portion in which the via plug 130 is not formed. The insulating structure 140 may include all of the etch stop layer 141, the first insulating layer 142, and the second insulating layer 143 in the vicinity of the via plug 130.
For example, the insulating structure 140 at the upper end of the via plug 130 may be formed to be thicker than the insulating structure 140 at an upper end of the portion in which the via plug 130 is not formed. Further, the insulating structure 140 formed in the vicinity of the via plug 130 may be thicker than the insulating structure 140 formed at the upper end of the via plug 130. The insulating structure 140 at the upper end of the via plug 130 may be formed at a higher position than the insulating structure 140 in the other portion.
Referring to
Referring to
The interconnection holes 151 may have different etch depths according to a thickness of the insulating structure 140. As illustrated above, the interconnection hole 151 may be formed on the contact 122 by patterning. The insulating structure 140 on the contact 122 before forming the interconnection hole 151 may include only the second insulating layer 143. The interconnection hole 151 formed on the contact 122 may be formed by the second insulating layer 143 and a portion of the lower interlayer insulating film 120 being etched thereto.
When the insulating structure 140 includes the first insulating layer 142 and the etch stop layer 141 in addition to the second insulating layer 143, the interconnection hole 151 including a multi-layer structure having steps with different etch depths may be formed by an etch-back process.
Referring again to
The insulating structure 140 including the etch stop layer 141, the first insulating layer 142, and the second insulating layer 143 may be formed in the vicinity of the upper surface of the via plug 130. In the case in which the insulating structure 140 includes the etch stop layer 141, a second lower surface 151b including a relatively shallow etch depth may be formed when an etch-back process for forming the interconnection hole 151 is performed. A side surface 151c may be formed when the etch-back process for forming the interconnection hole 151 is performed. The lower surfaces 151a and 151b of the interconnection hole 151 may be formed to have a multi-layer structure with a step, e.g. a step corresponding the side surface 151c, according to position and/or a thickness of the etch stop layer 141. A difference in etch depths between the first lower surface 151a and the second lower surface 151b may vary according to an etch selectivity of a material to be etched.
In the semiconductor structure in which the interconnection hole 151 is formed, the insulating structure 140 formed in the vicinity of via plug 130 may be thicker than the insulating structure 140 formed in a portion in which the via plug 130 is not present. That is, due to the etch stop layer 141 and the first insulating layer 142 remaining after the etch-back process, the insulating structure 140 in the vicinity of the via plug 130 may be formed to be thicker than the insulating structure 140 in the other portion.
Referring to
Referring to
The metal film may be formed by electroplating a metal such as silver (Ag), gold (Au), copper (Cu), aluminum (Al), tungsten (W), indium (In), or the like. For example, the metal film may be made of copper (Cu), a copper-based alloy (Cu—Sn, Cu—Mg, Cu—Ni, Cu—Zn, Cu—Pd, Cu—Au, Cu—Re, or Cu—W), tungsten (W), or a tungsten-based alloy.
Although not illustrated, a metal seed layer may be formed on the interconnection barrier film 152. A metal film for forming the metal layer 153 for interconnection may be grown from the metal seed layer. The metal layer 153 for interconnection may have a first lower surface and a second lower surface corresponding to a shape of the interconnection hole 151 and including a step.
The insulating structure 140 may be on a lower portion and a side portion of the second lower surface of the metal layer 153 for interconnection. As illustrated above, the insulating structure 140 may not be under the circumferential surface of the metal layer 153 for interconnection formed on the contact 122. In contrast, the insulating structure 140 may be on a lower portion and a side portion of the circumferential surface of the metal layer 153 for interconnection formed on the via plug 130. Further, the insulating structure 140 under and around a circumferential surface of the via plug 130 may not have a constant thickness and may have a step.
Referring to
As illustrated above, the second lower surface of the metal layer 153 for interconnection may be formed by a portion of the etch stop layer 141 being etched thereto. The thickness of the insulating structure 140 under the second lower surface of the metal layer 153 for interconnection may be less than the thickness of the etch stop layer 141. That is, the second lower surface of the metal layer 153 for interconnection may correspond to a position at which a portion of the upper surface of the etch stop layer 141 is etched.
The insulating structure 140 including the etch stop layer 141, the first insulating layer 142, and the second insulating layer 143 which remain without being etched may be present on a side portion of the metal layer 153 for interconnection. The side portion of the metal layer 153 for interconnection may be a position corresponding to an outside of the circumferential surface of the via plug 130. The thickness of the insulating structure 140 on the side portion of the metal layer 153 for interconnection may be equal to a sum of the thicknesses of the etch stop layer 141, the first insulating layer 142, and the second insulating layer 143.
Referring to
Referring to
Referring to
Referring to
Referring to
The interconnection structure may transmit an electrical signal in a horizontal direction of the upper interlayer insulating film 150. The interconnection structure may include a conductor such as doped silicon, a metal, a metal silicide, a metal alloy, and/or a metal compound. The interconnection structure may include a front pad. The front pad may include a metal such as copper (Cu), aluminum (Al), or tungsten (W).
The upper insulating film 160, which may be a passivation film, may be formed on the upper interlayer insulating film 150 which surrounds the interconnection structure. The upper insulating film 160 may be made of a silicon oxide (SiO2) film, a silicon nitride (SiN) film, a polymer, or a combination thereof. The connection holes 161 which expose the front pads 156 connected to the interconnection structure may be formed on the upper insulating film 160. The front pad 156 may electrically connect a portion of the interconnection structure at an uppermost portion to the upper connection terminal 170. For example, the front pads 156 may be connected to the upper connection terminals 170 through the connection holes 161.
Referring to
The upper connection terminals 170 and the lower connection terminal 183 are not limited to the illustrated shapes, and may have a shape of a solder ball, a solder bump, a re-distribution structure, or a front pad. In an embodiment, at least one of the upper connection terminals 170 and the lower connection terminal 183 may be omitted.
The semiconductor device 100 according to some example embodiments may be formed as a multi-chip stacked package.
Referring to
The upper device S1 may include photodiodes 13 formed at an upper substrate 11, color filters 14, micro lenses 15, via plugs 12, and an I/O pad 16. The intermediate device S2 may include an intermediate substrate 21, an interconnection structure 22, via plugs 23, a re-distribution structure 24, and an insulating structure 25. The lower device S3 may include a DRAM chip 31, a re-distribution structure 32, a dummy structure 34, and/or a molding portion 35 in a chip form.
The upper device S1 and the intermediate device S2 may be electrically connected by the via plug 12. The via plug 12 may be a backside via stack (BVS). The intermediate device S2 and the lower device S3 may be electrically connected by the respective re-distribution structures 24 and 32 being bonded using a solder bump 33 in a COW manner. The insulating structure 25 of some example embodiments may be applied to a metal layer for interconnection of the re-distribution structure 24 formed at an end of the via plug 23. Further, an insulating structure 28 of some example embodiments may also be applied under a metal layer 27 for interconnection on the substrate 21 in a position between an interlayer insulating film of the intermediate device S2 and the substrate 21. Further, although not illustrated, some example embodiments may also be applied to an end of the via plug 12.
As illustrated above, in the case in which the individual devices S1, S2, and S3 are stacked by a COW manner, the lower device S3 in a chip form may be stacked thereon only when a structure in which the upper device S1 and the intermediate device S2 are stacked is determined to be quality goods, and thus a yield may be improved.
Referring to
The upper device S1′ may include photodiodes 13, color filters 14, micro lenses 15, via plugs 12, and an I/O pad 16 formed at an upper substrate 11. The intermediate device S2′ may include an intermediate substrate 21, an interconnection layer 26, a via plug 23, a metal layer 29 for interconnection, and an insulating structure 25. The lower device S3′ may include a lower substrate 31 and an interconnection layer 36.
The upper device S1′ and the intermediate device S2′ may be electrically connected by the via plug 12, and the intermediate device S2′ and the lower device S3′ may be electrically connected by the via plug 23. Each of the via plugs 12 and 23 may be a TSV. The insulating structure 25 of some example embodiments may be applied to the metal layer 29 for interconnection formed at ends of the via plugs 12 and 23.
According to some example embodiments, defects of a semiconductor device can be reduced by providing a via plug structure and a lower structure of an interconnection for improving electrical characteristics and reliability.
While some example embodiments have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of example embodiments and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.
Number | Date | Country | Kind |
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10-2017-0178361 | Dec 2017 | KR | national |
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