SEMICONDUCTOR DEVICE HAVING SOI STRUCTURE

Abstract

A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor chip common to first to third preferred embodiments of the present invention;

FIG. 2 is a plan view of the semiconductor chip common to the first to third preferred embodiments, schematically showing, in perspective, a guard ring part of the semiconductor chip;

FIG. 3 is a plan view of a variation of the semiconductor chip common to the first to third preferred embodiments;

FIG. 4 is a vertical sectional view of an example of a semiconductor device according to the first preferred embodiment;

FIG. 5 is a vertical sectional view of a semiconductor device according to a variation of the first preferred embodiment;

FIG. 6 is a vertical sectional view of an example of a semiconductor device according to a second preferred embodiment;

FIG. 7 is a vertical sectional view of a semiconductor device according to a variation of the second preferred embodiment;

FIG. 8 is a vertical sectional view of an example of a semiconductor device according to a third preferred embodiment;

FIG. 9 is a vertical sectional view of a semiconductor device according to a variation of the third preferred embodiment;

FIGS. 10A-10C, 11A-11C, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 16A-16C, 17A-17C, 18A-18C and 19A-19C are vertical sectional views showing manufacturing steps of a semiconductor device according to a fourth preferred embodiment;

FIGS. 20-22 are vertical sectional views showing manufacturing steps of a semiconductor device according to a fifth preferred embodiment;

FIGS. 23-28 are vertical sectional views showing manufacturing steps of a semiconductor device according to a sixth preferred embodiment;

FIG. 29 is a vertical sectional view schematically illustrating an embodiment of mounting the semiconductor chip according to any one of the first to third preferred embodiments on a substrate by FC technique; and

FIG. 30 is a vertical sectional view schematically illustrating another embodiment of mounting the semiconductor chip according to any one of the first to third preferred embodiments on a substrate by FC technique.

Claims

1. A semiconductor device comprising a semiconductor supporting substrate, an insulation film layer formed on said semiconductor supporting substrate and a transistor formed on a semiconductor layer formed on said insulation film layer, comprising: an isolation oxide film formed in said semiconductor layer;an interlayer insulation film formed on said semiconductor layer and said isolation oxide film;a wiring layer formed on said interlayer insulation film; anda conductive layer connecting said semiconductor supporting substrate and said wiring layer and fixing a potential of said semiconductor supporting substrate, whereinsaid conductive layer and said wiring layer are formed around a periphery of a region in which said transistor is to be formed.

2. The semiconductor device according to claim 1, comprising: a plurality of said interlayer insulation films and a plurality of said wiring layers; anda conductive layer connecting said semiconductor supporting substrate and an uppermost wiring layer.

3. The semiconductor device according to claim 2, comprising: a plurality of said conductive layers and a plurality of said wiring layers around the periphery of said region in which said transistor is to be formed.

4. The semiconductor device according to claim 1, comprising: a conductive layer and said wiring layer, both surrounding the periphery of said region in which said transistor is to be formed, said conductive layer connecting said semiconductor supporting substrate and an uppermost wiring layer.

5. The semiconductor device according to claim 1, wherein a plurality of said conductive layers and a plurality of said wiring layers connected to said conductive layers are formed to overlap one another.

6. The semiconductor device according to claim 1, comprising: a silicide layer formed on a bottom of a first opening extending through said isolation oxide film, said semiconductor layer and said insulation film layer to reach said semiconductor supporting substrate;a conductive layer filling a second opening extending through a first interlayer insulation film formed on said semiconductor layer and said isolation oxide film to reach said silicide layer; anda wiring layer connected to said conductive layer.

7. The semiconductor device according to claim 6, wherein said conductive layer filling said second opening and said semiconductor layer are connected.

8. The semiconductor device according to claim 7, wherein said first opening has a width smaller than twice a thickness of said fist interlayer insulation film filling said first opening.

9. The semiconductor device according to claim 1, comprising: a highly-doped semiconductor layer formed in said semiconductor supporting substrate under a second opening extending through said isolation oxide film and a first interlayer insulation film formed on said isolation oxide film to reach said semiconductor supporting substrate;a conductive layer filling said second opening; andsaid wiring layer connected to said conductive layer.

10. The semiconductor device according to claim 9, wherein said conductive layer filling said second opening and said semiconductor layer are connected.

11. The semiconductor device according to claim 1, comprising: a silicide layer formed on a bottom of a second opening extending through said isolation oxide film and a first interlayer insulation film formed on said isolation oxide film to reach said semiconductor supporting substrate;a conductive layer filling said second opening; andsaid wiring layer connected said conductive layer.

12. The semiconductor device according to claim 11, wherein said conductive layer filling said second opening and said semiconductor layer are connected.

13. A method of manufacturing a semiconductor device, comprising the steps of: forming an isolation insulation film isolating a semiconductor layer formed on a supporting substrate with an insulation film layer interposed therebetween, around a transistor forming region in which a transistor is to be formed in said semiconductor layer;forming a first opening extending through said insulation film layer directly under said isolation insulation film to reach said supporting substrate;forming a silicide layer on said supporting substrate corresponding to a bottom of said first opening;forming a first interlayer insulation film layer inside and above said first opening;forming a second opening in said first opening, said second opening extending through said first interlayer insulation film layer, with the bottom of said second opening corresponding to a surface of said silicide layer;forming a first conductive layer filling said second opening, to an upper surface of said first interlayer insulation film layer;forming a first wiring layer connected onto said first conductive layer and forming a second interlayer insulation film layer around said first wiring layer; andforming, in one or a plurality of layers, a conductive layer connected onto said first wiring layer, a wiring layer connected onto the conductive layer and an interlayer insulation film layer around said wiring layer, whereinsaid first conductive layer, said first wiring layer, said conductive layer and said wiring layer connected to one another are formed around said transistor forming region.

14. A method of manufacturing a semiconductor device, comprising the steps of: forming an isolation insulation film isolating a semiconductor layer formed on a supporting substrate with an insulation film layer interposed therebetween, around a transistor forming region in which a transistor is to be formed in said semiconductor layer;forming a highly-doped layer in said supporting substrate directly under said insulation film layer directly under said isolation insulation film;forming a first interlayer insulation film layer above said semiconductor layer and said isolation insulation film;forming a second opening extending through said first interlayer insulation film layer and said isolation insulation film to reach said highly-doped layer in said supporting substrate;forming a first conductive layer filling said second opening, to an upper surface of said first interlayer insulation film layer; andforming a first wiring layer connected onto said first conductive layer and forming a second interlayer insulation film layer around said first wiring layer; andforming, in one or a plurality of layers, a conductive layer connected onto said first wiring layer, a wiring layer connected onto the conductive layer and an interlayer insulation film layer around said wiring layer, whereinsaid first conductive layer, said first wiring layer, said conductive layer and said wiring layer connected to one another are formed around said transistor forming region.

15. A method of manufacturing a semiconductor device, comprising the steps of: forming an isolation insulation film isolating a semiconductor layer formed on a supporting substrate with an insulation film layer interposed therebetween, around a transistor forming region in which a transistor is to be formed in said semiconductor layer;forming a first interlayer insulation film layer above said semiconductor layer and said isolation insulation film;forming a second opening extending through said first interlayer insulation film layer and said isolation insulation film to reach said supporting substrate;forming a silicide layer on said supporting substrate corresponding to a bottom of said second opening;forming a first conductive layer filling said second opening, to an upper surface of said first interlayer insulation film layer;forming a first wiring layer connected onto said first conductive layer and forming a second interlayer insulation film layer around said first wiring layer; andforming, in one or a plurality of layers, a conductive layer connected onto said first wiring layer, a wiring layer connected onto the conductive layer and an interlayer insulation film layer around said wiring layer, whereinsaid first conductive layer, said first wiring layer, said conductive layer and said wiring layer connected to one another are formed around said transistor forming region.

16. The semiconductor device according to claim 3, further comprising: a silicide layer located on said semiconductor layer; anda second conductive layer connecting said uppermost wiring layer and said silicide layer, whereinsaid second conductive layer does not reach said semiconductor support substrate, and is formed around a periphery of a region in which said transistor is to be formed.