Claims
- 1. A semiconductor device, comprising:a semiconductor substrate; a semiconductor element formed on said semiconductor substrate by overlaying a plurality of patterned layers; and a position check mark used for overlay of said plurality of layers, wherein said semiconductor element includes: an interlayer insulating film formed on said semiconductor substrate; a contact hole penetrating said interlayer insulating film to reach said semiconductor substrate; a plug that is conductive and fills said contact hole; a barrier metal layer provided to cover said contact hole and to be electrically connected to said plug; and a conductive film formed on said barrier metal layer, and wherein said position check mark includes: a plurality of mark holes formed to penetrate said interlayer insulating film; a plurality of recess plugs that are conductive and provided so that their respective one end portions on a side opposite to said semiconductor substrate are recessed in said plurality of mark holes; and wherein said barrier metal layer is provided to cover said plurality of mark holes and to be electrically connected to said recess plug; and said conductive film is formed on said barrier metal layer.
- 2. The semiconductor device according to claim 1, wherein an opening size of each of said plurality of mark holes ranges from substantially as large as an opening size of said contact hole to substantially twice as large as the opening size of said contact hole.
- 3. The semiconductor device according to claim 1, wherein said plurality of mark holes are formed through a same process as said contact hole.
- 4. A semiconductor device, comprising:a semiconductor substrate; a semiconductor element formed on said semiconductor substrate by overlaying a plurality of patterned layers; and a position check mark used for overlay of said plurality of layers, wherein said semiconductor element includes: an interlayer insulating film formed on said semiconductor substrate; a contact hole penetrating said interlayer insulating film to reach said semiconductor substrate; a plug that is conductive and fills said contact hole; a barrier metal layer provided to cover said contact hole and to be electrically connected to said plug; and a conductive film formed on said barrier metal layer, and wherein said position check mark has a recess region in which a determined region of said interlayer insulating film is recessed; a plurality of mark holes are formed to penetrate said interlayer insulating film in said recess region; a plurality of protrusion plugs that are conductive are provided so that their respective one end portions on a side opposite to said semiconductor substrate protrude from said plurality of mark holes; said barrier metal layer is provided to cover said plurality of mark holes and to be electrically connected to said protrusion plug; and said conductive film is formed on said barrier metal layer.
- 5. The semiconductor device according to claim 4, whereinan opening size of each of said plurality of mark holes ranges from substantially as large as an opening size of said contact hole to substantially twice as large as the opening size of said contact hole.
- 6. The semiconductor device according to claim 4, wherein said plurality of mark holes are formed through a same process as said contact hole.
Priority Claims (1)
Number |
Date |
Country |
Kind |
P11-206305 |
Jul 1999 |
JP |
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Parent Case Info
This application is a continuation of application Ser. No. 09/484,066 filed on Jan. 18, 2000, now U.S. Pat. No. 6,376,924.
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Continuations (1)
|
Number |
Date |
Country |
Parent |
09/484066 |
Jan 2000 |
US |
Child |
10/080683 |
|
US |