The present invention relates to a semiconductor device including, on a substrate, a first functional area including a storage area and the like, a second functional area including a driving circuit and the like, and an electrode for externally inputting and outputting a signal.
As a technique of connecting a chip (a DRAM chip), on which a memory such as a DRAM (Dynamic Random Access Memory), a driving circuit and the like are formed, to an external substrate, a method of fixing the chip onto the external substrate through hot pressing using a solder bump is known. In the case where a bump connection pad is disposed on the DRAM chip, a load is applied to a DRAM cell array at the time of a bump connection (assembling) if the bump connection pad is provided immediately above the DRAM cell array. Therefore, there arises a problem that the DRAM cell array is damaged, the characteristics of the DRAM cell array are degraded, or the like.
Therefore, the bump connection pad is conventionally disposed at the position of a peripheral circuit (the driving circuit or the like) so as not to be situated immediately above the DRAM cell array.
Patent Document 1: Japanese Patent Application Publication No. Hei 4-162664
In the conventional semiconductor device, the bump connection pads and the bumps are disposed so as to avoid the DRAM cell array area. Therefore, the DRAM cell array is not affected even if a load is applied through the bumps at the connection of the DRAM chip. However, since the bump connection pads and the bumps are disposed so as to be separated from each other, for example, at both ends on the DRAM chip, there arises a problem that a yield at the time of the bump connection (assembling) is lowered. Specifically, even a slight inclination of the DRAM chip causes a variation in load applied to the bumps provided at both horizontal ends. Uniform pressure connection for all the bumps becomes difficult, for example, a bump at one end is successfully connected whereas a bump at the other end is not fully seated, resulting in lowered reliability of products.
The present invention is devised to solve the above problems. Specifically, in the present invention, a semiconductor device including a first functional area and a second functional area, which are provided on a substrate, wherein an electrode for externally inputting and outputting a signal is provided so as to overlap the second functional area provided inside a circumscribed rectangle of the first functional area when the substrate is viewed in a planar fashion.
In the present invention described above, the electrodes are provided so as to overlap the second functional area provided inside the circumscribed rectangle of the first functional area. Therefore, the electrodes are collectively arranged in approximately the center of the substrate. As a result, a pressure can be prevented from being applied to the first functional area upon connection. At the same time, pressure connection to an external substrate through the electrodes can be achieved without expanding the area where the electrodes are arranged. Thus, uniform connection to the electrodes can be achieved.
Hereinafter, embodiments of the present invention will be described based on the drawings.
The semiconductor device according to the first embodiment has two first functional areas (1a and 1b). Bumps (metal projections) B for externally inputting and outputting a signal are provided in the second functional area 2, which is an area between the first functional areas (an inner area of a circumscribed rectangle when the first functional areas 1 are viewed in a planar fashion). The semiconductor device is connected face-down to an external substrate 20 through the bumps B.
By the above-mentioned arrangement of each of the components, the bumps B can be provided in approximately the center of the substrate 10 so as not to be situated directly above the DRAM cell arrays corresponding to the first functional areas 1. Therefore, at heat pressure connection of the semiconductor device to the external substrate 20 through the bumps B, a pressure is not applied from the bumps B to the DRAM cell arrays (the first functional areas 1).
Specifically, the DRAM cell arrays corresponding to the first functional areas 1 have lower resistance against the applied pressure per given area (hereinafter, referred to simply as “resistance against the applied pressure”) than that of the area of the signal processing circuit or the driving circuit corresponding to the second functional area 2. Therefore, a pressure is not applied from the bumps B to the DRAM cell arrays (the first functional areas 1), thereby making possible to prevent the DRAM cell arrays from being damaged.
Moreover, since the bumps B are disposed in approximately the center of the substrate 10, a distance between the bumps at both extremities can be reduced as compared with the case where the bumps are provided at the ends of the substrate 10, and even if the substrate 10 is inclined to some degree, uniform bump connection to the external substrate 20 can be achieved.
By the above-mentioned arrangement of each of the components, the bumps B can be provided in approximately the center of the substrate 10 so as not to be situated directly above the DRAM cell arrays corresponding to the first functional areas 1. Therefore, at heat pressure connection of the semiconductor device to the external substrate 20 through the bumps B, the same functional effects as those in the previously described example are obtained. Specifically, a pressure is not applied from the bumps B to the DRAM cell arrays (the first functional areas 1) which have lower resistance against the applied pressure (lower resistance against the applied pressure than that of the area of the signal processing circuit or the driving circuit corresponding to the second functional area 2). Therefore, the DRAM cell arrays can be prevented from being damaged.
Moreover, the plurality of bumps B are arranged in a cross-like pattern. As a result, the bumps can be arranged in approximately the center of the substrate 10. At the same time, a wiring distance between each of the bumps B and the first functional area 1 can be reduced as much as possible, so that a signal delay can be prevented.
As described above, any number of the first functional areas 1 may be provided. The bumps B are provided at the position in the second functional area 2, which is an area between the first functional areas (for example, 1a to 1f). As a result, the arrangement of the bumps in approximately the center of the substrate 10 and the reduction of the wiring distance between each of the bumps B and the first functional areas 1 can be achieved at the same time.
As a result of the arrangement of each of the components as described above, the bumps can be arranged in approximately the center of the substrate 10 while the reduction of the wiring distance between each of the bumps B and the first functional areas 1 can be made possible.
In this embodiment, the first functional areas 1 (1a to 1d), each being cut, are arranged so as to surround the bumps B arranged in approximately the center of the substrate 10 in a rectangular pattern. As a result of such arrangement, the bumps can be arranged in approximately the center of the substrate 10 while the reduction of the wiring distance between each of the bumps B and the first functional areas 1 can be made possible. At the same time, layout efficiency of the substrate 10 can be enhanced.
This embodiment particularly differs from the other embodiments in that the corners of the bumps B partially overlap the first functional areas 1. Specifically, it is apparent that an overlap part of the first functional areas 1 with the bumps B is subjected to a pressure upon connection. Therefore, from the very beginning of design, a part of the first functional areas 1, which is pressurized by the bumps B, is set as an invalid area (a non-functioning area) in advance. As a result, the area of the bumps B and the first functional areas 1 can come closer to each other. Therefore, in addition to the effects of the semiconductor device according the fifth embodiment, layout efficiency can also be enhanced.
Even if the first functional area 1 is annular without being divided as described above, the bumps B can be arranged in approximately the center of the substrate 10. Moreover, the wiring distance between each of the bumps B and the first functional area 1 can be reduced.
It should be noted that, in each of the embodiments described above, the plurality of first functional areas 1 may be obtained by dividing a single functional area to be arranged or arranging a plurality of functional areas. For example, if the first functional area 1 is composed of a DRAM cell array, the DRAM cell array may be divided into a plurality of DRAM cell arrays to be arranged so as to achieve 256 Mbit in total (in this case, a single DRAM cell array obtained by the division corresponds to one first functional area 1). Alternatively, a plurality of DRAM cell arrays, each being a 256-Mbit DRAM cell array serving as a single first functional area 1, may be arranged (in this case, a total capacity is obtained by: the number of first functional areas 1×256 Mbit).
Although a rectangle shape has been mainly described as the shape of the first functional area 1, it is not limited thereto. The first functional area may include a curve area such as a circle. Furthermore, the same effects can be achieved if an electrode other than the bump B is used as long as it allows connection by the heat pressure.
As described above, according to the present invention, the following effects are obtained. Specifically, if the semiconductor device is to be connected to the external substrate by the heat pressure, a pressure through the electrodes is no longer applied to the first functional area, so that and the first functional area is prevented from being damaged. Furthermore, since the arrangement of the electrodes concentrates in approximately the center of the substrate, uniform connection to the electrodes provides a highly reliable apparatus.
Number | Date | Country | Kind |
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2003-040730 | Feb 2003 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP04/01079 | 2/3/2004 | WO | 7/27/2005 |