SEMICONDUCTOR DEVICE

Abstract

To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.

Description

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a partial cross-sectional view for illustrating a semiconductor device in accordance with example 1 of the present invention.

FIG. 2 is a cross-sectional view of a simulation model of a ground wiring layer, a second dielectric layer and a power supply wiring layer of the semiconductor device in accordance with example 1 of the present invention.

FIG. 3 is a graph obtained by an electromagnetic field simulation by the model of FIG. 2 to explain a transmission loss between a power supply wiring layer and a ground wiring layer.

FIG. 4 is a graph to explain noise between power supply and ground wirings when a driver of the semiconductor device in accordance with example 1 of the present invention is operated at an operation frequency of 1 GHz.

FIG. 5 is a partial cross-sectional view for illustrating a semiconductor device in accordance with example 2 of the present invention.

FIGS. 6A, 6B and 6C illustrate signal waveforms flowing in signal wiring, showing an ideal pattern, a pattern influenced by dielectric loss and a pattern of less dielectric loss, respectively.

FIG. 7 is an electric circuit to explain a simultaneous switching noise.

Claims

1. A semiconductor device, wherein a dielectric material whose dielectric loss tan δ is at least 0.2 is used for a dielectric layer interposed between a power supply wiring layer electrically connected to a semiconductor chip and a ground wiring layer.

2. The semiconductor device of claim 1, wherein said semiconductor device is so composed that a transmission loss generated in said dielectric layer acts as a low pass filter of said power supply wiring layer.

3. The semiconductor device of claim 1 further comprising; another dielectric layer interposed between a signal wiring layer electrically connected to said semiconductor chip and said ground wiring layer, wherein a dielectric material having a dielectric loss less than said dielectric loss tan δ of said dielectric layer is used for said another dielectric layer.

4. The semiconductor device of claim 2 further comprising; another dielectric layer interposed between a signal wiring layer electrically connected to said semiconductor chip and said ground wiring layer, wherein a dielectric material having a dielectric loss less than said dielectric loss tan δ of said dielectric layer is used for said another dielectric layer.

5. The semiconductor device of claim 1, wherein the dielectric loss tan δ of said dielectric layer is large to an extent that does not deteriorate the signal quality.

6. The semiconductor device of claim 1, wherein the dielectric loss tan δ is not more than 1.

7. A semiconductor device, wherein a dielectric material whose dielectric loss tan δ is at least 0.2 is used for a dielectric layer interposed between a signal wiring layer electrically connected to a semiconductor chip and a ground wiring layer.

8. The semiconductor device of claim 5, wherein said semiconductor device is so composed that a transmission loss generated in said dielectric layer reduces noise occurred in said signal wiring layer.

9. The semiconductor device of claim 7, wherein the dielectric loss tan δ of said dielectric layer is large to an extent that does not deteriorate the signal quality.

10. The semiconductor device of claim 7, wherein the dielectric loss tan δ is not more than 1