Patent Application
20230282645
The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor devices including high electron mobility transistors.
In semiconductor technology, group III-V semiconductor compounds may be used to construct various integrated circuit (IC) devices, such as high power field-effect transistors (FETs), high frequency transistors, or high electron mobility transistors (HEMTs). A HEMT is a field effect transistor having a two dimensional electron gas (2-DEG) layer close to a junction between two materials with different energy gaps (i.e., a hetero-junction). The 2-DEG layer is used as the transistor channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs). Compared with MOSFETs, HEMTs have a number of attractive properties, such as high electron mobility and the ability to transmit signals at high frequencies.
A half-bridge circuit is widely used in the field of power electronics. When a high-side switching element and a low-side switching element of a half-bridge circuit share the same substrate, they are easily affected by cross talk in series connection. Therefore, it is difficult to implement a half-bridge circuit in a system on a chip (SoC). HEMTs may be applied in a half-bridge circuit as the high-side switching element and the low-side switching element of the half-bridge circuit to achieve the benefits of SoC. However, when HEMTs are applied in a half-bridge circuit, there are still some problems that need to be overcome.
In view of this, the present disclosure provides a semiconductor device including high electron mobility transistors with an improved backside electrode to solve the problems of high electron mobility transistors being applied in a half-bridge circuit.
According to one embodiment of the present disclosure, a semiconductor device is provided and includes a substrate, an insulating layer, a semiconductor layer, a compound semiconductor stacked layer, a first transistor, a second transistor, an isolation structure, and a conductive structure. The insulating layer, the semiconductor layer and the compound semiconductor stacked layer are disposed on the substrate in sequence. The first transistor is disposed in a first device region and includes a first gate electrode, a first source electrode and a first drain electrode disposed on the compound semiconductor stacked layer. The second transistor is disposed in a second device region, and includes a second gate electrode, a second source electrode, and a second drain electrode disposed on the compound semiconductor stacked layer. The isolation structure is disposed between the first transistor and the second transistor. The conductive structure is disposed in the second device region, passes through the compound semiconductor stacked layer, and electrically connects the semiconductor layer to the second source electrode. There is no electrical connection between the semiconductor layer in the first device region and the first source electrode.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “over,” “above,” “on,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” and/or “beneath” other elements or features would then be oriented “above” and/or “over” the other elements or features. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments.
As disclosed herein, the term “about” or “substantial” generally means within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages disclosed herein should be understood as modified in all instances by the term “about” or “substantial”. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired.
Furthermore, as disclosed herein, the terms “coupled to” and “electrically connected to” include any directly and indirectly electrical connecting means. Therefore, if it is described in this document that a first component is coupled or electrically connected to a second component, it means that the first component may be directly connected to the second component, or may be indirectly connected to the second component through other components or other connecting means.
In the present disclosure, a “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, where group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and group V element may be nitrogen (N), phosphorous (P), arsenic (As), or antimony (Sb). Furthermore, the group III-V semiconductor may refer to, but not limited to, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), AlGaAs, InAlAs, InGaAs, or the like, or the combination thereof. Besides, based on different requirements, group III-V semiconductor may contain dopants to become semiconductor with specific conductivity type, such as n-type or p-type.
Although the disclosure is described with respect to specific embodiments, the principles of the disclosure, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the disclosure described herein. Moreover, in the description of the present disclosure, certain details have been left out in order to not obscure the inventive aspects of the disclosure. The details left out are within the knowledge of a person having ordinary skill in the art.
The present disclosure is directed to a semiconductor device including high electron mobility transistors (HEMTs). The HEMTs may be used as a high voltage switching element (or referred to as a high-side switching element) and a low voltage switching element (or referred to as a low-side switching element) of a half-bridge circuit. According to embodiments of the present disclosure, there is no electrical connection between the backside electrode and the source electrode of the HEMT for the high-side switching element. The backside electrode of the HEMT for the high-side switching element is electrically connected to a ground terminal, or the backside electrode of the HEMT for the high-side switching element is an electrically floating layer. Accordingly, there is no parasitic capacitance generated between the backside electrode of the high-side switching element and the substrate of the semiconductor device. Therefore, the embodiments of the present disclosure avoid the input/output voltage of the semiconductor devices being affected, and avoid the thickness between the backside electrode and the substrate of the semiconductor devices limiting the capability of power supply voltage (Vbus) of the devices.
According to embodiments of the present disclosure, the compound semiconductor stacked layer 110 is disposed on the semiconductor layer 105 to form HEMTs. The compound semiconductor stacked layer 110 may be formed on the semiconductor layer 105 by epitaxial growth, and the semiconductor layer 105 may be used as a nucleation layer for the compound semiconductor stacked layer 110. According to some embodiments, the compound semiconductor stacked layer 110 may include a buffer layer 106, a high resistance layer (or referred to as an electrical isolation layer) 107, a channel layer 108, and a barrier layer 109 that are stacked on the semiconductor layer 105 from bottom to top in sequence. The material of each layer of the compound semiconductor stacked layer 110 includes group III-V compound semiconductors (also referred to as group III-V semiconductors). In one embodiment, the buffer layer 106 may be a superlattice (SL) structure, for example, including a plurality of alternately stacked aluminum gallium nitride (AlGaN) layers and aluminum nitride (AlN) layers. The high resistance layer 107 may be, for example, a carbon-doped gallium nitride (c-GaN) layer. The channel layer 108 may be, for example, an undoped gallium nitride (u-GaN) layer. The barrier layer 109 may be, for example, an aluminum gallium nitride (AlGaN) layer, but not limited thereto. In addition, the compound semiconductor stacked layer 110 may further include other layers, such as an epitaxial layer (for example, AlN) for reducing lattice defects. The epitaxial layer may be disposed between the buffer layer 106 and the semiconductor layer 105. The composition and the arrangement of each layer in the compound semiconductor stacked layer 110 may be determined according to the requirements of various semiconductor devices.
According to embodiments of the present disclosure, the semiconductor device 100 further includes a first transistor 100-1 and a second transistor 100-2. The first transistor 100-1 is disposed in a first device region 101-1, and includes a first gate electrode G1, a first source electrode S1 and a first drain electrode D1 disposed on the compound semiconductor stacked layer 110. The second transistor 100-2 is disposed in a second device region 101-2, and includes a second gate electrode G2, a second source electrode S2 and a second drain electrode D2 disposed on the compound semiconductor stacked layer 110. In addition, the first transistor 100-1 further includes a first cap layer 111 disposed between the first gate electrode G1 and the barrier layer 109. The second transistor 100-2 further includes a second cap layer 112 disposed between the second gate electrode G2 and the barrier layer 109. In one embodiment, the first cap layer 111 and the second cap layer 112 are, for example, p-type gallium nitride (p-GaN) layers, but not limited thereto. Since there is a discontinuous energy gap between the channel layer 108 and the barrier layer 109, by stacking the channel layer 108 and the barrier layer 109 on each other, electrons will be gathered at the hetero-junction between the channel layer 108 and the barrier layer 109 due to the piezoelectric effect, thereby producing a thin layer with high electron mobility, i.e., a two-dimensional electron gas region 2DEG. For normally off devices, when no voltage is applied to the first gate electrode G1 and the second gate electrode G2, a region covered by the first cap layer 111 and the second cap layer 112 will not form two-dimensional electron gas (as shown in
In addition, the semiconductor device 100 further includes an isolation structure 120 disposed between the first transistor 100-1 and the second transistor 100-2. In some embodiments, the isolation structure 120 passes through the compound semiconductor stacked layer 110 and the semiconductor layer 105, and further extends downward to a position in the depth of the insulating layer 103. The bottom surface of the isolation structure 120 may be lower than the top surface of the insulating layer 103. A deep trench may be formed in the compound semiconductor stacked layer 110, the semiconductor layer 105 and the insulating layer 103 by etching, and then the deep trench is filled up with a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof. Next, the aforementioned structure is subjected to a chemical mechanical planarization (CMP) process to form the isolation structure 120. In some embodiments, the isolation structure 120 may be a ring-shaped insulating pillar structure with one or more circles respectively surrounding the first transistor 100-1 and the second transistor 100-2. In the embodiments of the present disclosure, the semiconductor layer 105 may be used as the backside electrodes of the first transistor 100-1 and the second transistor 100-2, and the isolation structure 120 passing through the compound semiconductor stacked layer 110 and the semiconductor layer 105 provides good electrical isolation between the first transistor 100-1 and the second transistor 100-2.
In addition, according to the embodiments of the present disclosure, there is no electrical connection between the semiconductor layer 105 in the first device region 101-1 and the first source electrode S1, i.e., the backside electrode B1 of the first transistor 100-1 (also referred to as the high-side switching element) is not directly electrically connected to the first source electrode S1. There is no conductive structure passing through the compound semiconductor stacked layer 110 and being connected to the semiconductor layer 105 in the vertical projection area of the first source electrode S1. Since the first source electrode S1 of the high-side switching element is electrically connected to the second drain electrode D2 of the low-side switching element through an interconnection structure 117 and has the potential of an output voltage, and the semiconductor layer 105 in the first device region 101-1 of the embodiments of the present disclosure is not electrically connected to the first source electrode S1, so that the semiconductor layer 105 in the first device region 101-1 does not have the potential of the output voltage. Therefore, the embodiments of the present disclosure avoid the occurrence of a parasitic capacitance being generated between the semiconductor layer 105 in the first device region 101-1 and the substrate 101, which protects the input/output voltage of the semiconductor device 100 from being affected and maintains a normal operating voltage of the semiconductor device 100.
According to an embodiment of the present disclosure, please refer to
In addition, in the semiconductor device 100 of
In addition, the parasitic capacitance Cox of the semiconductor device 200 of this embodiment is affected by the thickness of the insulating layer 103. In order to reduce the parasitic capacitance Cox, the thickness of the insulating layer 103 of the semiconductor device 200 must be increased. However, while the thickness of the insulating layer 103 is increased, the heat dissipation capability of the semiconductor device 200 will also become worse, thereby reducing the performance of the semiconductor device 200.
In contrast, for the semiconductor devices 100 illustrated in
Therefore, the semiconductor devices of the embodiments of the present disclosure use HEMTs as the high-side switching element and the low-side switching element of the half-bridge circuit to achieve the benefits of a system-on-a-chip (SoC), and avoid parasitic inductance and capacitance effects between the high-side and low-side switching elements caused by wire bonding. Meanwhile, the parasitic capacitance between the backside electrode of the high-side switching element and the substrate is eliminated, and the limitation of the thickness of the insulating layer under the backside electrode to the power supply voltage (Vbus) of the semiconductor devices is also avoided, thereby maintaining the heat dissipation capability of the semiconductor devices, and improving the performance of the semiconductor devices.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
