Claims
- 1. A semiconductor device comprising:
an internal circuit; a signal generation circuit which produces a selection signal; a clock input circuit including a first clock signal output circuit which receives a first clock signal and outputs a second clock signal which is a delayed version of said first clock signal with a first delay time and a second clock signal output circuit which receives said first clock signal and outputs a third clock signal which is a delayed version of said first clock signal with a second delay time; wherein said internal circuit is operable based on said second clock signal in case that said selection signal is in a first state, wherein said internal circuit is operable based on said third clock signal in case that said selection signal is in a second state, and wherein said first delay time is controlled to vary correspondingly with the variation in frequency of said first clock signal, and said second delay time is controlled to be fixed correspondingly with the variation in frequency of said first clock signal.
- 2. A semiconductor device according to claim 1, wherein said signal generation circuit has a terminal, and said selection signal is determined to have the first state or second state depending on the voltage applied to said terminal.
- 3. A semiconductor device according to claim 2, wherein said terminal is brought to an electrical floating state or applied a predetermined voltage.
- 4. A semiconductor device according to claim 1 further including a memory mat having a plurality of memory cells, wherein said first clock signal is supplied from the outside of said semiconductor device, and said internal circuit includes an output circuit which outputs data read out of said memory mat to the outside of said semiconductor device.
- 5. A semiconductor device according to claim 1, wherein said clock input circuit includes a selection circuit which has a first input terminal for receiving said second clock signal, a second terminal for receiving said third clock signal, a control terminal for receiving said selection signal, and an output terminal connected to said output circuit,
said selection circuit outputting said second clock signal to said output terminal if said selection signal is in the first state, or outputting said third clock signal to said output terminal if said selection signal is in the second state.
- 6. A semiconductor device according to claim 1 further including a memory mat having a plurality of dynamic memory cells, wherein said semiconductor device configures a semiconductor memory device of Double Data Rate type if said selection signal is in said first state, or configures a semiconductor memory device of Single Data Rate type if said selection signal is in said second state.
- 7. A semiconductor device according to claim 1 further including a memory mat having a plurality of memory cells, wherein said internal circuit includes an output circuit which outputs data read out of said memory mat,
said output circuit outputting data which is read out of said memory mat in a period twice the length of period of said first clock signal if said selection signal is in said first state, or outputting data which is read out of said memory mat in the period of said first clock signal if said selection signal is in said second state.
- 8. A semiconductor device according to claim 1, wherein said second clock signal output circuit includes a buffer circuit which receives said first clock signal and outputs said third clock signal, said buffer circuit having a delay time which is constant irrespective of the change in frequency of said first clock signal.
- 9. A semiconductor device according to claim 1, wherein said first clock signal output circuit comprises a circuit which compares the phases of said first clock signal with said second clock signal and produces said second clock signal in accordance with the result of comparison.
- 10. A semiconductor device according to claim 1, wherein said first clock signal output circuit includes a delayed lock loop circuit.
- 11. A semiconductor device according to claim 4, wherein said first delay time is a delay time which is corresponding with the delay time of said output circuit.
- 12. A semiconductor device according to claim 1, wherein said first clock signal output circuit is deactivated if said selection signal is in said second state.
- 13. A semiconductor device comprising:
a memory mat having a plurality of memory cells; a signal generation circuit which outputs a selection signal; a first circuit which includes a clock regenerating circuit which is controlled by said selection signal and outputs a second clock signal which is corresponding with said first clock signal; and a second circuit which outputs data read out of said memory mat in response to said second clock signal, wherein said clock regenerating circuit produces a third clock signal which is a delayed signal of said first clock signal with a first delay time, said first delay time is controlled to vary, said clock regenerating circuit is activated if said selection signal is in a first state, said clock regenerating circuit is deactivated if said selection signal is in a second state, said first circuit outputs said second clock signal in case that said selection signal is in said first state, and said first circuit outputs said second clock signal in case that said selection signal is in said second state.
- 14. A semiconductor device according to claim 13, wherein said signal generation circuit has a terminal, and said selection signal is determined to have the first state or second state depending on the voltage applied to said terminal.
- 15. A semiconductor device according to claim 14, wherein said terminal is brought to an electrical floating state or applied a predetermined voltage.
- 16. A semiconductor device according to claim 13, wherein said first clock signal is supplied from the outside of said semiconductor device, and said second circuit outputs data read out of said memory mat to the outside of said semiconductor device.
- 17. A semiconductor device according to claim 13, wherein said first circuit includes a fourth clock signal output circuit which receives said first clock signal and outputs a fourth clock signal which is corresponding with said first clock signal, and a selection circuit which includes a first and second input terminals for receiving said third and fourth clock signals, respectively, a control terminal for receiving said selection signal and an output terminal for outputting said second clock signal,
said selection circuit outputting said third clock signal to said output terminal if said selection signal is in said first state and outputting said fourth clock signal to said output terminal if said selection signal is in said second state.
- 18. A semiconductor device according to claim 17, wherein said-fourth clock signal output circuit includes a buffer circuit which receives said first clock signal and outputs said fourth clock signal, said buffer circuit having a constant delay time.
- 19. A semiconductor device according to claim 13, wherein said memory cells comprise dynamic memory cells, and said semiconductor device configures a semiconductor memory device of Double Data Rate type if said selection signal is in said first state, or configures a semiconductor memory device of Single Data Rate type if said selection signal is in said second state.
- 20. A semiconductor device according to claim 19, wherein said second circuit outputs data which is read out of said memory mat, twice for a period of said first clock signal in case that said selection signal is in said first state, and outputs data, which is read out of said memory mat, one time for a period of said first clock signal in case that said selection signal is in said second state.
- 21. A semiconductor device according to claim 13, wherein said clock regenerating circuit comprises a circuit which compares the phases of said first clock signal with said second clock signal and produces said second clock signal in accordance with the result of comparison.
- 22. A semiconductor device comprising:
a signal generation circuit which outputs a selection signal; an input/output circuit; a first and second data transfer lines connected to said input/output circuit; a first and second memory mats each including a plurality of memory cells; and a control circuit connected between said first and second memory mats and said first and second data transfer lines, wherein if said selection signal is in a first state, said control circuit is controlled such that data read out of said first memory mat is transferred to said input/output circuit using said first transfer line and data read out of said second memory mat is transferred to said input/output circuit using said second transfer line, and said input/output circuit is controlled such that input data to be stored in said first memory mat is transferred to said first memory mat using said first transfer line and input data to be stored in said second memory mat is transferred to said second memory mat using said second transfer line, or input data to be stored in said first memory mat is transferred to said first memory mat using said second transfer line and input data to be stored in said second memory mat is transferred to said second memory mat using said first transfer line, or if said selection signal is in a second state, said control circuit is controlled such that data read out of said first memory mat is transferred to said input/output circuit using said first transfer line or data read out of said second memory mat is transferred to said input/output circuit using said first transfer line, and said input/output circuit is controlled such that input data to be stored in said first memory mat is transferred to said first memory mat using said second transfer line and input data to be stored in said second memory mat is transferred to said second memory mat using said second transfer line.
- 23. A semiconductor device according to claim 22, wherein said memory cells comprise dynamic memory cells, and said semiconductor device configures a semiconductor memory device of Double Data Rate type if said selection signal is in said first state, or configures a semiconductor memory device of Single Data Rate type if said selection signal is in said second state.
- 24. A semiconductor device according to claim 22, wherein said signal generation circuit has a terminal, and said selection signal is determined to have the first state or second state depending on the voltage applied to said terminal.
- 25. A semiconductor device according to claim 24, wherein said terminal is brought to an electrical floating state or applied a predetermined voltage.
- 26. A semiconductor device according to claim 22, wherein said input/output circuit receives data from the outside of said semiconductor device and outputs data to the outside of said semiconductor device.
- 27. A semiconductor device comprising:
a signal generation circuit which produces a selection signal; an input/output circuit; a first and second data transfer lines connected to said input/output circuit; a first and second memory mats each including a plurality of memory cells; and a control circuit connected between said first and second memory mats and said first and second data transfer lines, wherein at reading out data from said first and second memory mats, with said selection signal being in a first state, said control circuit is controlled such that data read out of said first memory mat is transferred to said input/output circuit via said first transfer line and data read out of said second memory mat is transferred to said input/output circuit via said second transfer line, at reading out data from said first memory mat, with said selection signal being in a second state, said control circuit is controlled such that data read out of said first memory mat is transferred to said input/output circuit via said first transfer line, and at reading out data from said second memory mat, with said selection signal being in said second state, said control circuit is controlled such that data read out of said second memory mat is transferred to said input/output circuit via said first transfer line.
- 28. A semiconductor device according to claim 27, wherein said memory cells comprise dynamic memory cells, and said semiconductor device configures a semiconductor memory device of Double Data Rate type if said selection signal is in said first state, or configures a semiconductor memory device of Single Data Rate type if said selection signal is in said second state.
- 29. A semiconductor device according to claim 27, wherein said signal generation circuit has a terminal, and said selection signal is determined to have said first state or second state depending on the voltage applied to said terminal.
- 30. A semiconductor device according to claim 27, wherein said terminal is brought to an electrical floating state or applied a predetermined voltage.
- 31. A semiconductor device according to claim 27, wherein said input/output circuit receives data from the outside of said semiconductor device and outputs data to the outside of said semiconductor device.
- 32. A semiconductor device comprising:
a signal generation circuit which produces a selection signal; an input/output circuit; a first and second data transfer lines connected to said input/output circuit; a memory mat including a plurality of memory cells; and a control circuit connected between said memory mat and said first and second data transfer lines, wherein said control circuit and said input/output circuit are controllable such that if said selection signal is in a first state, said first and second data transfer lines work for bidirectional data transfer, or if said selection signal is in a second state, said first and second data transfer lines work for unidirectional data transfer.
- 33. A semiconductor device according to claim 32, wherein said memory cells comprise dynamic memory cells, and said semiconductor device configures a semiconductor memory device of Double Data Rate type if said selection signal is in said first state, or configures a semiconductor memory device of Single Data Rate type if said selection signal is in said second state.
- 34. A semiconductor device according to claim 32, wherein said signal generation circuit has a terminal, and said selection signal is determined to have said first state or second state depending on the voltage applied to said terminal.
- 35. A semiconductor device according to claim 34, wherein said terminal is brought to an electrical floating state or applied a predetermined voltage.
- 36. A semiconductor device according to claim 32, wherein said input/output receives data from the outside of said semiconductor device and outputs data to the outside of said semiconductor device.
- 37. A semiconductor device comprising:
a clock terminal for receiving a clock signal; a data terminal; a signal generation circuit which outputs a selection signal; a data transfer line; an input/output circuit connected between said data terminal and said data transfer line; and a memory mat including a plurality of memory cells, wherein if said selection signal is in a first state, said input circuit is enabled to place data, which has been received on said data terminal, on said data transfer line at a timing which is later by the duration of one period of said clock signal than the write command data input, or if said selection signal is in a second state, said input circuit is enabled to place data, which has been received on said data terminal, on said data transfer line at a timing which is later by the duration of two periods of said clock signal than the write command data input.
- 38. A semiconductor device according to claim 37, wherein said memory cells comprise dynamic memory cells, and said semiconductor device configures a semiconductor memory device of Double Data Rate type if said selection signal is in the first state, or configures a semiconductor memory device of Single Data Rate type if said selection signal is in the second state.
- 39. A semiconductor device according to claim 37, wherein said signal generation circuit has a terminal, and said selection signal is determined to have the first state or second state depending on the voltage applied to said terminal.
- 40. A semiconductor device according to claim 39, wherein said terminal is brought to an electrical floating state or applied a predetermined voltage.
- 41. A semiconductor device comprising:
a clock terminal which receives a clock signal; a first control terminal which receives a first control signal; a second control terminal which receives a second control signal; a data terminal; a data transfer line; an input circuit connected between said data terminal and said data transfer line; a memory mat including a plurality of memory cells connected to said data transfer line; a control circuit which responds to said first control signal to output a signal indicative of the negation of data writing into said memory mat; and a signal generation circuit which produces a selection signal, wherein if said selection signal is in a first state, data supplied to said data terminal is taken into said input circuit in response to said second control signal, and said first control signal is taken into said control circuit in response to said second control signal, and wherein if said selection signal is in a second state, data supplied to said data terminal is taken into said input circuit in response to said clock signal, and said first control signal is taken into said control circuit in response to said clock signal.
- 42. A semiconductor device according to claim 41, wherein said memory cells comprise dynamic memory cells, and said semiconductor device configures a semiconductor memory device of Double Data Rate type if said selection signal is in the first state, or configures a semiconductor memory device of Single Data Rate type if said selection signal is in the second state.
- 43. A semiconductor device according to claim 42, wherein said first control signal is a data mask signal and said second control signal is a data strobe signal.
- 44. A semiconductor device according to claim 42, wherein said signal generation circuit has a terminal, and said selection signal is determined to have the first state or second state depending on the voltage applied to said terminal.
- 45. A semiconductor device according to claim 44, wherein said terminal is brought to an electrical floating state or applied a predetermined voltage.
- 46. A semiconductor device including:
an internal circuit; a signal generation circuit which outputs a selection signal; and a clock input circuit including a first clock signal output circuit and a second clock signal output circuit, said first clock signal output circuit having a phase judgement function and a phase adjustment function and operating to receive a first clock signal and produce a second clock signal which is synchronized and phase-controlled with respect to said first clock signal, said second clock signal output circuit operating to receive said first clock signal and produce a third clock signal based on the buffering of said first clock signal, wherein if said selection signal is in a first state, said internal circuit is enabled to operate based on said second clock signal, and wherein if said selection signal is in a second state, said internal circuit is enabled to operate based on said third clock signal.
- 47. A semiconductor device according to claim 46 further including a memory mat including a plurality of memory cells,
wherein said first clock signal is supplied from the outside of said semiconductor device, and said internal circuit include an output circuit which releases data read out of said memory mat to the outside of said semiconductor device.
Priority Claims (1)
Number |
Date |
Country |
Kind |
11-245820 |
Aug 1999 |
JP |
|
Parent Case Info
[0001] This is a divisional of U.S. application Ser. No. 09/531,467, filed Mar. 20, 2000, the entire disclosure of which is incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09531467 |
Mar 2000 |
US |
Child |
09964669 |
Sep 2001 |
US |