Patent Application
20150372107
1. Technical Field
The present disclosure relates to methods of forming semiconductor devices having one or more fin structures (“fins”), and to semiconductor devices having one or more fins. Some embodiments described in the present disclosure relate to finFETs and/or to methods for fabricating finFETs.
2. Discussion of the Related Art
Transistors are fundamental device elements of many modern digital processors and memory devices, and have found numerous applications in various areas of electronics including data processing, data storage, and high-power applications. Currently, there are a variety of transistor types and designs that may be used for different applications. Various transistor types include, for example, bipolar junction transistors (BJT), junction field-effect transistors (JFET), metal-oxide-semiconductor field-effect transistors (MOSFET), vertical channel or trench field-effect transistors, and superjunction or multi-drain transistors.
Two types of transistors which have emerged within the MOSFET family of transistors show promise for scaling to ultra-high density and nanometer-scale channel lengths. One of these transistor types is a so-called fin field-effect transistor or “finFET.” The channel of a finFET is formed in a three-dimensional fin that may extend from a surface of a substrate. FinFETs have favorable electrostatic properties for complimentary MOS (CMOS) scaling to smaller sizes. Because the fin is a three-dimensional structure, the transistor's channel can be formed on three or more surfaces of the fin, so that the finFET can exhibit a high current switching capability for a given surface area occupied on substrate. Since the channel and device can be raised from the substrate surface, there can be reduced electric field coupling between adjacent devices as compared to conventional planer MOSFETs.
The second type of transistor is called a fully-depleted, silicon-on-insulator or “FD-SOI” FET. The channel, source, and drain of an FD-SOI FET are formed in a thin planar semiconductor layer that overlies a thin insulator. Because the semiconductor layer and the underlying insulator are thin, the body of the transistor (which lies below the thin insulator) can act as a second gate. The thin layer of semiconductor on insulator permits higher body biasing voltages that can boost performance. The thin insulator also reduces leakage current to the transistor's body region relative to the leakage current that would otherwise occur in bulk FET devices.
According to some embodiments, a method is provided, comprising: forming a fin on a substrate, forming a first layer covering the fin, forming a gate structure at least partially surrounding at least a portion of the fin and the first layer, and depositing a second layer on one or more side surfaces of the gate structure without depositing the second layer on the first layer at one or more side surfaces of the fin.
In some embodiments, forming the first layer comprises forming an oxide layer disposed at a top surface of the fin and at the one or more side surfaces of the fin.
In some embodiments, the gate structure comprises polysilicon.
In some embodiments, the second layer comprises a nitride layer.
In some embodiments, the nitride layer comprises a silicon nitride layer.
In some embodiments, depositing the second layer on one or more side surfaces of the gate structure without depositing the second layer on the on the first layer at the one or more side surfaces of the fin comprises using a selective nitridation process to deposit the nitride layer on the polysilicon layer at the one or more side surfaces of the gate structure without depositing the nitride layer on the oxide layer at the one or more side surfaces of the fin.
In some embodiments, the method further comprises forming a third layer on the first layer at the one or more side surfaces of the fin and on the second layer at the one or more side surfaces of the gate structure.
In some embodiments, the second and third layers comprise a nitride and collectively form a nitride layer, and a first thickness of the nitride layer disposed on a first of the one or more side surfaces of the gate structure is greater than a second thickness of the nitride layer disposed on a first of the one or more side surfaces of the fin.
In some embodiments, the nitride layer covers the one or more side surfaces of the gate structure, the top surface of the gate structure, and a portion of the gate structure forming a peripheral boundary between the one or more side surfaces of the gate structure and the top surface of the gate structure.
In some embodiments, the method further comprises etching the nitride layer to remove the nitride layer from the first layer covering the fin, and to form spacers at the one or more side surfaces of the gate structure.
In some embodiments, the method further comprises etching to remove the first layer from the side surfaces of the fin and a top surface of the fin; and doping first and second portions of the fin to form respective drain and source junctions of a finFET.
In some embodiments, the gate structure comprises a sacrificial gate, and the method further comprises removing the sacrificial gate; and forming a gate conductor of a finFET in an area from which the sacrificial gate was removed.
In some embodiments, the fin forms part of a finFET.
In some embodiments, the substrate comprises a silicon substrate, the fin comprises silicon, and the first layer comprises ethylene oxide.
In some embodiments, the silicon substrate comprises a bulk silicon substrate or a silicon-on-insulator substrate.
According to some embodiments, a method is provided, comprising: forming a fin on a substrate, forming a first layer covering the fin, forming a gate structure at least partially surrounding at least a portion of the fin, and selectively depositing a spacer layer over the substrate, wherein the spacer layer is deposited with a first thickness on one or more side surfaces of the gate structure and with a second thickness, less than the first thickness, on the first layer at one or more side surfaces of the fin.
In some embodiments, forming the first layer comprises forming an oxide layer disposed at a top surface of the fin and at the one or more side surfaces of the fin.
In some embodiments, the gate structure comprises polysilicon.
In some embodiments, the spacer layer comprises a nitride layer.
In some embodiments, the nitride layer comprises a silicon nitride layer.
In some embodiments, selectively depositing the spacer layer comprises depositing second and third layers over the substrate, and the second and third layers collectively form the spacer layer.
In some embodiments, depositing the second layer over the substrate comprises selectively depositing the second layer on the one or more side surfaces of the gate structure without depositing the second layer on the first layer at the one or more side surfaces of the fin.
In some embodiments, depositing the third layer comprises depositing the third layer on the first layer at the one or more side surfaces of the fin and on the second layer at the one or more side surfaces of the gate structure.
In some embodiments, the second layer comprises a first nitride layer, and the third layer comprises a second nitride layer.
In some embodiments, the first and second nitride layers comprise silicon nitride.
In some embodiments, depositing the second and third layers over the substrate comprises depositing the second and third layers in consecutive steps of a semiconductor fabrication process.
In some embodiments, depositing the spacer layer over the substrate comprises forming the spacer layer without etching the spacer layer.
In some embodiments, the fin forms part of a finFET.
According to some embodiments, a device is provided, comprising: a fin formed on a substrate, a first layer covering the fin, a gate structure at least partially surrounding at least a portion of the fin, and second and third layers formed over the substrate, wherein the second and third layers collectively form a spacer layer, wherein the spacer layer is disposed on one or more side surfaces of the gate structure and at one or more side surfaces of the fin, and wherein the spacer layer has a first thickness at the one or more side surfaces of the gate structure and a second thickness, less than the first thickness, at the one or more side surfaces of the fin.
According to some embodiments, a device is provided, comprising first and second parallel semiconductor fins formed on a substrate separated with a pitch between approximately 10 nm and 30 nm.
In some embodiments, the fin pitch is between approximately 10 nm and 20 nm.
In some embodiments, the fin pitch is between approximately 10 nm and 15 nm.
One of ordinary skill in the art will understand that the figures, described herein, are for illustration purposes only. It is to be understood that in some instances various aspects of the illustrated embodiments may be shown exaggerated or enlarged to facilitate an understanding of the embodiments. In the drawings, like reference characters generally refer to like features, functionally similar elements and/or structurally similar elements throughout the various figures. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the teachings. Where the drawings relate to fabrication of integrated devices, an illustrated device may be representative of a large plurality of devices that may be fabricated in parallel. The drawings are not intended to limit the scope of the present teachings in any way.
An example of a fully-depleted silicon-on-insulator (FD-SOI) FET 100 is depicted in
In some embodiments, the source region 120 and drain region 140 of an FD-SOI FET may be doped with acceptor or donor impurities to form regions of a first conductivity type (e.g., p-type or n-type). The channel region 150 may be doped to be of an opposite conductivity type, and may be of a same conductivity type as a back body region 115 (e.g., partially-depleted SOI or PD-SOI). In some implementations, the channel region 150 may be undoped (FD-SOI). An FD-SOI FET can exhibit reduced leakage currents compared to bulk FET devices and offer flexible bias strategies for improving speed or reducing threshold voltages for low-voltage applications.
An example of a finFET 200 is depicted in the perspective view of
In some embodiments, during operation of the finFET, the entire fin portion encased by the gate structure may be inverted and form a bulk channel rather than a surface channel. In some embodiments, a metallic film may be deposited between a gate electrode 231 and gate oxide 235 (e.g., to improve gate conductance and/or gate switching speeds).
FinFETs like the finFET depicted in
Alternatively, in some embodiments finFETs may be formed on an SOI substrate. When a finFET is formed on an SOI substrate, the fins may be attached to the thin semiconductor layer of the SOI substrate at base regions of the fins, or the fins may be formed by etching through the insulating layer of the SOI substrate such that the base regions of the fins are attached to the substrate layer of the SOI substrate.
Source, channel, and drain regions of a finFET may be doped with donor or acceptor impurities to create different regions of different conductivity types. Several different configurations of source, channel, and drain regions are possible. According to some embodiments, source region 220 and drain region 240 may be doped to be of a first conductivity type and the channel region 250 may be doped to be of an opposite conductivity type (or may be undoped). The terms “source region” and “drain region” as used may include extension regions of the fins that lie between source and drain contact regions and the channel region of the finFET device.
The finFET may further include a body region that may be of a same conductivity type as the channel region, or undoped (e.g., like the channel region). The doping of source and drain regions in a finFET may be of various geometries. In some embodiments, vertical portions of the fin 215 may be doped to form source 220 and drain 240 regions. Alternatively, according to some embodiments, outer sheath portions of a fin 215 may be doped to form source and drain regions.
As has been consistent since the early days of semiconductor device manufacturing, minimum feature sizes of semiconductor devices continue to shrink with each next generation of devices, or manufacturing “node,” allowing a corresponding increase in the density of devices on an integrated circuit. This trend has been recognized and represented by the well-known Moore's law relationship. As finFETs reduce in size, the width of the fin becomes narrower, and the spacing between fins, or “fin pitch,” may also decrease. Some finFETs may comprise multiple fins per device, and a reduction in fin pitch may allow an increase in the number of fins for the device and the amount of current switched by the finFET. The inventors have recognized that some processing techniques used for manufacturing finFETs may not be suitable for making finFETs where the fin pitch becomes less than about 30 nm. Problems associated with these processing techniques are described in connection with
According to one processing technique, the fins may be formed with a fin width (317a, 317b) of approximately 8 nm, and the spacer layer 355 may be subsequently deposited at a minimum thickness (316a, 316b) of approximately 8 nm. As can be seen, for a fin pitch 390 of approximately 24 nm, the portions of spacer layer 355 formed on fin 317a and fin 317b merge together, “pinching off” the space between the fins. When deposition of the spacer layer leads to pinch-off between the fins, it may be difficult to reliably remove the spacer layer from the fins without damaging the fins. The same difficulties would be encountered in other configurations where the spacing between adjacent fins is approximately equal to or less than twice the minimum spacer layer thickness (e.g., if the minimum spacer layer thickness were about 10 nm and the fin width were about 10 nm in the example of
A technique for reliably fabricating finFETs with fin pitch of less than approximately 30 nm is illustrated in
In the example of
In the example of
In the example of
For example, the portions of layer 480 adjacent the finFET's gate structure may form gate spacers, and may require a minimum thickness of (e.g., 5-10 nm) to function properly as gate spacers. However, forming the portions of layer 480 adjacent the finFET's fins with the same thickness as the gate spacers may pinch off the space between the fins, particularly in devices where the fin pitch is small. Thus, forming layer 480 with differential thickness in the regions adjacent the finFET's gate structure and the regions adjacent the finFET's fins may facilitate formation of a suitable gate spacer without pinching off the space between the finFET's fins.
The deposition of a spacer layer 480 having greater thickness adjacent the finFET gate structure and less thickness adjacent the finFET fin may be achieved using any suitable technique. In some embodiments, layer 480 of material may include two or more layers. In some embodiments, portions of layer 480 formed adjacent the finFET's gate structure may include a first layer 460 and a second layer (not illustrated), while portions of layer 480 formed adjacent the finFET's fins may include only the first layer 460. Each of the two or more layers included in layer 480 may include, but is not limited to, a nitride (e.g., silicon nitride, SiOCN, SiPCN, and/or any other suitable nitride), a boron silicide (SiB), any material suitable for forming a gate spacer structure, and/or any other suitable material.
Using embodiments of the technique illustrated in
Some of the acts 502-512 of method 500 are illustrated in
In some embodiments, an insulating layer 405 may be formed over the substrate adjacent to lower portions of the fin(s). In some embodiments, insulating layer 405 may be formed by depositing insulating material over the substrate, by etching portions of an insulating material, and/or by any other suitable technique.
At act 504, a protective layer 450 is formed over the substrate, at least partially covering the finFET's one or more fins. The protective layer may be formed over the substrate by any suitable process that deposits or otherwise forms a layer of suitable material at least over one or more fins. In some embodiments, the protective layer may be formed locally on the substrate to cover one or more fins within a selected region of the substrate. In the example of
At act 506, a gate structure is formed over the substrate, at least partially surrounding at least a portion of the finFET's one or more fins and the protective layer. In some embodiments, the gate structure may be formed by depositing one or more layers over the substrate, and using lithographic techniques to pattern a gate structure over the fins. For example, a poly-silicon layer may be deposited over the fins, and may be planarized. A hard mask (e.g., a silicon nitride mask) may be deposited and patterned over the poly-silicon layer. The hard mask may be patterned using photolithography techniques and etching. The pattern of the hard mask may be transferred to the poly-silicon via etching to from the gate structure. Other suitable techniques and materials may be used in other embodiments to form the gate structure.
In some embodiments, gate structure 430 may include, but is not limited to, a sacrificial gate, a gate conductor of finFET 402, one or more spacers, a gate insulator, any other suitable layer, and/or any other suitable material. A sacrificial gate may include one or more layers and/or materials formed as a “dummy gate” for the finFET 402, and subsequently removed prior to formation of the finFET's gate conductor. The sacrificial gate may include, but not limited to, one or more layers of polysilicon. A gate conductor may include one or more layers and/or materials configured such that a voltage applied thereto controls a current between the finFET's source and drain (e.g., one or more layers of polysilicon and/or metallic material). A spacer may include one or more layers and/or materials (e.g., one or more nitride layers) disposed at sidewalls of the gate structure adjacent source and drain regions of the finFET. A gate insulator may include one or more layers and/or materials disposed adjacent to the finFET channel and configured to insulate the gate conductor from the channel (e.g., one or more layers of silicon oxide, ethylene-type oxide, and/or any other suitable material).
In the example of
At act 508, a spacer layer 480 is deposited over the substrate. In some embodiments, the spacer layer may be disposed on one or more side surfaces of the gate structure, on a top surface of the gate structure (e.g., on a top surface of hard mask layer disposed at a top surface of the gate structure), on one or more side surfaces of a fin (e.g., on the “protective layer” disposed at one or more side surfaces of the fin), and/or on the top surface of the fin (e.g., on the “protective layer” disposed at the top surface of the fin). In some embodiments, a thickness of the spacer layer in a region adjacent (e.g., on) a side surface of the gate structure may exceed a thickness of the spacer layer in regions adjacent (e.g., on) top and/or side surfaces of the fin(s).
In some embodiments, depositing the spacer layer in act 508 may include a process step of forming (e.g., depositing) a first layer 475. In some embodiments, the first layer 475 may be formed on one or more side surfaces of the gate structure without forming the first layer adjacent to one or more top and/or side surfaces of the fin(s) (e.g., without forming the first layer on the protective layer 450 disposed adjacent to the top and/or side surfaces of the fin(s), or with minimal formation of the first layer on the fin surfaces), as depicted in
In some embodiments, the first layer may be formed (e.g., deposited) using a selective formation (e.g., selective deposition) process (e.g., selective nitridation process) in which a material (e.g., a nitride) is formed on some materials (e.g., silicon and/or polysilicon) but not others (e.g., oxide, such as silicon oxide and/or ethylene-type oxide), or formed on some materials (e.g., silicon and/or polysilicon) at faster rates than on other materials (e.g., oxide, such as silicon oxide and/or ethylene-type oxide). The selective formation process may include, but is not limited to, the selective nitridation process described in U.S. patent application Ser. No. 13/623,620, filed Sep. 20, 2012 and titled “Surface Stabilization Process to Reduce Dopant Diffusion,” now published as U.S. Pub. No. 2013/0109162, which is hereby incorporated by reference herein in its entirety; Applied Materials' commercially available Byron process; and/or any other suitable selective formation process.
In some embodiments, depositing the spacer layer 480 may further include a process step of forming (e.g., depositing) a second layer 460. In some embodiments, the first and second layers may collectively form the spacer layer. In some embodiments, the first and second layers may be deposited in distinct process steps (e.g., in successive (“consecutive”) process steps).
In some embodiments, the second layer may be formed over the entire substrate. In some embodiments, the second layer may be formed over the gate structure. The portion of the second layer formed over the gate structure may cover the gate structure and the first layer formed in act 508. In some embodiments, the second layer may be formed over the fin(s). The portion of the second layer formed over the fin(s) may cover the fin(s) and the protective layer 450 formed in act 504 of method 500.
The second layer may be formed by any suitable process that deposits or otherwise forms the second layer to the wafer or die, including, but not limited to, epitaxy, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and/or any suitable thin nitride deposition technique. In some embodiments, deposition of the second layer may comprise additive processes (processes which add material to the wafer or die, e.g., deposition) and/or modification processes (processes which modify properties of material on the wafer or die, e.g., doping) but not removal processes (processes which remove material from the wafer or die, e.g., etching). The second layer may be conformally deposited over the gate and fin structures. In some embodiments, the technique used to deposit the second layer may be atomic-layer deposition (ALD).
In some embodiments, the second layer may include the same material as the first layer, or any suitable material.
In some embodiments, the protective layer formed on the fins during act 504 of method 500 may be removed from portions of the fins not covered by gate structure 430 prior to formation of the second layer in act 508. Such removal of protective layer 450 may be carried out using etching and/or any technique suitable for removing the protective layer from a semiconductor device. As discussed above, removing the protective layer from the fins prior to formation the second layer in act 508 may facilitate fabrication of finFETs with reduced fin pitch.
In some embodiments, the first and second layers deposited in act 508 may collectively form the spacer layer deposited in act 508. In some embodiments, the spacer layer may provide protective covering at the “corners” of gate structure 430 (e.g., the peripheral boundary between the top surface of gate structure 430 and the side surfaces of gate structure 430). The portion of the spacer layer material covering the corners of gate structure 430 may prevent exposure of the gate conductor during a spacer etch and a parasitic epitaxial growth at the corners of the gate structure during a subsequent epitaxial step (e.g., a subsequent epitaxial step for forming a strained source and/or drain junction).
Although a two-step process of forming the spacer layer 480 has been described, the spacer layer may be formed by any suitable process that deposits or otherwise selectively forms one or more suitable materials on the wafer or die, including, but not limited to, epitaxy, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), sputtering, e-beam evaporation, and/or atomic layer deposition (ALD). In some embodiments, formation of the spacer layer may comprise additive processes (processes which add material to the wafer or die, e.g., deposition) and/or modification processes (processes which modify properties of material on the wafer or die, e.g., doping) but not removal processes (processes which remove material from the wafer or die, e.g., etching). According to some embodiments, the spacer layer forms selectively on exposed surfaces of the gate structure 430, but does not form, or minimally forms, at the fins (415a, 415b).
In act 510, a portion of the spacer layer 480 may be removed from finFET 402. The portion of the spacer layer may be removed by etching (e.g., anisotropic etching and/or timed etching) or any other suitable technique. In some implementations, a short isotropic etch may be used to remove residual spacer layer at the fins. In some embodiments, the removal process may remove all or substantially all of the spacer layer from the regions adjacent the finFET's fins. In some embodiments, the removal process may remove only a portion of the spacer layer from the regions adjacent the gate structure's side surfaces, thereby forming gate spacers adjacent the gate structure's side surfaces.
In act 512, drain and/or source junctions may be formed in the finFET's fin(s). In some embodiments, forming the drain and/or source junctions may include a process step of removing portions of the protective layer not covered by the gate structure from the top and/or side surfaces of the fin(s). A description of techniques for removing the protective layer from the fins has been given above and is not repeated here. In some embodiments, after removing the protective layer, the drain and/or source junctions of the finFET may be formed by doping the fins.
In some embodiments, the techniques described herein may improve control over the locations of the source and drain junctions. In some embodiments, the source and drain junctions may be formed using ion implantation, where the remaining spacer after etching acts as a self-aligned, ion-implantation mask. By carefully controlling the thickness of the selective nitridation layer 475 and subsequent second layer 460 (e.g., via ALD), the thickness of the spacer layer on the sidewalls of the gate can be determined to a high degree of precision. For example, the thickness of the spacer layer on the sidewalls of the gate can be determined to within about ±5 nm in some embodiments, and within about ±2 nm in some embodiments, and yet within about ±1 nm in some embodiments. By determining the thickness of the spacer layer with a high degree of precision, the locations of the source and drain junctions can be determined also with high precision.
In some embodiments, the techniques described herein may reduce damage to the fins during the finFET's fabrication, relative to conventional techniques.
The technology described herein may be embodied as a method, of which at least one example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments. Additionally, a method may include more acts than those illustrated, in some embodiments, and fewer acts than those illustrated in other embodiments. In some embodiments, a method may include a single act illustrated in
Although embodiments of the techniques described herein have been described as conferring particular benefits, some embodiments of the techniques described herein may confer only one, fewer than all, or none of the described benefits.
Although embodiments of the techniques described herein have been described in relation to finFETs with fin pitch less than approximately 30 nm, the techniques described herein are not limited in this regard. In some embodiments, these techniques may be applied to finFETs with fin pitch greater than approximately 30 nm.
As used herein, an act of “forming” a layer may include any suitable process that deposits, grows, coats, transfers, or otherwise forms a layer of material on a wafer or die, including, but not limited to, epitaxy, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), sputtering, e-beam evaporation, and/or atomic layer deposition (ALD). In some embodiments, forming a layer may comprise additive processes (processes which add material to the wafer or die), modification processes (processes which modify properties of material on the wafer or die), and/or removal processes (processes which remove material from the wafer or die, e.g., etching).
In some embodiments, the techniques described herein may be used to form semiconductor devices as components in integrated circuits.
Although the drawings depict one or a few transistor structures, it will be appreciated that a large number of transistors can be fabricated in parallel following the described semiconductor manufacturing processes. The transistors may be incorporated as part of microprocessing or memory circuitry for digital or analog signal processing devices. The transistors may be incorporated in logic circuitry, in some implementations. The transistors may be used in consumer electronic devices such as smart phones, computers, televisions, sensors, microprocessors, microcontrollers, field-programmable gate arrays, digital signal processors, application specific integrated circuits, logic chips, analog chips, and digital signal processing chips.
Although some of the foregoing methods and structures are described in connection with “finFETs,” the methods and structures may be employed for variations of finFET devices in some embodiments. For example, according to some implementations, the methods and structures may be employed for the fabrication of tri-gate, pi-gate, or omega-gate transistors. In some embodiments, the methods and structures may be employed for the fabrication of gate-all-around (GAA) transistors.
The terms “approximately,” “substantially,” and “about” may be used to mean within ±20% of a target dimension in some embodiments, within ±10% of a target dimension in some embodiments, within ±5% of a target dimension in some embodiments, and yet within ±2% of a target dimension in some embodiments. The terms “approximately,” “substantially,” and “about” may include the target dimension.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and the equivalents thereto.
