BACKGROUND
Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments.
FIGS. 2-5, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B, 11C, 11D, 12A, 12B, 12C, 12D, 12E, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, 20C, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, 25C, 26A, 26B, 26C, 27A, 27B, 27C, 27D, 28-33, 34A, 34B, 35A, 35B, 36A, 36B, and 36C illustrate various views of a nano-Field Effect Transistor (FET) device at various stages of manufacturing, in accordance with an embodiment.
FIGS. 37-43 illustrate cross-sectional views of a nano-FET device at various stages of manufacturing, in accordance with another embodiment.
FIGS. 44 and 45 illustrate cross-sectional views of a semiconductor package at various stages of manufacturing, in an embodiment.
FIG. 46 illustrate a flow chart of a method of forming a semiconductor device, in an embodiment.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Throughout the discussion herein, unless otherwise specified, the same or similar numerals in different figures refer to the same or similar component formed by a same or similar formation method using the same or similar material(s).
Various embodiments provide methods for forming metal-insulator-metal (MIM) capacitors in the back-end-of-the-line (BEOL) process of semiconductor devices and semiconductor devices including the same. In some embodiments, the MIM capacitors are formed in one or more dielectric layers of an interconnect structure on a backside of a semiconductor die. The backside interconnect structure may be routed for power supply lines and electrical ground lines. In an embodiment, an MIM capacitor is formed by: removing portions of a dielectric layer dispose between two adjacent conductive lines in the dielectric layer to form an opening, forming barrier layers along sidewalls of the two adjacent conductive lines exposed by the opening, and filling the opening with a high-k dielectric material. In another embodiment, MIM capacitors are formed by: forming conductive lines with barrier layers in a dielectric layer, removing a portion of the dielectric layer disposed between two adjacent conductive lines to form an opening, lining sidewalls of the two adjacent conductive lines exposed by the opening with a high-k dielectric material, and forming a new conductive line with barrier layer to fill the opening. The MIM capacitors may stabilize the power supply lines and the electrical ground lines, resulting in improved device performance. Forming the MIM capacitors including high-k dielectric materials allows for the decoupling capacitors to hold greater charges, while minimizing the size of the MIM capacitors.
Some embodiments discussed herein are described in the context of a die including nano-FETs. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs.
FIG. 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments. The nano-FETs comprise nanostructures 55 (e.g., nanosheets, nanowire, or the like) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 act as channel regions for the nano-FETs. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and from between neighboring STI regions 68. Additionally, although bottom portions of the fins 66 are illustrated as being single, continuous materials with the substrate 50, the bottom portions of the fins 66 and/or the substrate 50 may comprise a single material or a plurality of materials. In this context, the fins 66 refer to the portion extending between the neighboring STI regions 68.
Gate dielectric layers 100 are over top surfaces of the fins 66 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are over the gate dielectric layers 100. Epitaxial source/drain regions 92 are disposed on the fins 66 on opposing sides of the gate dielectric layers 100 and the gate electrodes 102.
FIG. 1 further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions 92 of a nano-FET. Cross-section B-B′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions 92 of multiple nano-FETs. Cross-section C-C′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin 66 of the nano-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions 92 of the nano-FET. Subsequent figures refer to these reference cross-sections for clarity.
Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).
FIGS. 2 through 36C are various views (e.g., cross-sectional views, top views) of a nano-FET device 180 at various stages of manufacturing, in accordance with an embodiment. FIGS. 2 through 5, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28-33, 34A, 35A, 35B, and 36A illustrate reference cross-section A-A′ illustrated in FIG. 1. FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 12D, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, and 36B illustrate reference cross-section B-B′illustrated in FIG. 1. FIGS. 6C, 7C, 8C, 9C, 10C, 11C, 11D, 12C, 12E, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C, 23C, 24C, 25C, 26C, 27C, 27D, and 36C illustrate reference cross-section C-C′ illustrated in FIG. 1. FIG. 34B is a top view of the structure in FIG. 34A.
In FIG. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.
The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region 50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region 50N may be physically separated from the p-type region 50P (as illustrated by divider 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P may be provided.
Further in FIG. 2, a multi-layer stack 64 is formed over the substrate 50. The multi-layer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For purposes of illustration and as discussed in greater detail below, the first semiconductor layers 51 will be removed and the second semiconductor layers 53 will be patterned to form channel regions of nano-FETs in the n-type region 50N and the p-type region 50P. However, in some embodiments the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETs in the n-type region 50N, and the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in the p-type region 50P. In some embodiments the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in the n-type region 50N, and the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETs in the p-type region 50P. In some embodiments, the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in both the n-type region 50N and the p-type region 50P.
The multi-layer stack 64 is illustrated as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53 for illustrative purposes. In some embodiments, the multi-layer stack 64 may include any number of the first semiconductor layers 51 and the second semiconductor layers 53. Each of the layers of the multi-layer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layers 51 may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium or the like, and the second semiconductor layers 53 may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, or the like. The multi-layer stack 64 is illustrated as having a bottommost semiconductor layer suitable for p-type nano-FETs for illustrative purposes. In some embodiments, multi-layer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs.
The first semiconductor materials and the second semiconductor materials may be materials having a high etch selectivity to one another. As such, the first semiconductor layers 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layers 53 of the second semiconductor material thereby allowing the second semiconductor layers 53 to be patterned to form channel regions of nano-FETs. Similarly, in embodiments in which the second semiconductor layers 53 are removed and the first semiconductor layers 51 are patterned to form channel regions, the second semiconductor layers 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layers 51 of the first semiconductor material, thereby allowing the first semiconductor layers 51 to be patterned to form channel regions of nano-FETs.
Referring now to FIG. 3, fins 66 are formed in the substrate 50 and nanostructures 55 are formed in the multi-layer stack 64, in accordance with some embodiments. In some embodiments, the nanostructures 55 and the fins 66 may be formed in the multi-layer stack 64 and the substrate 50, respectively, by etching trenches in the multi-layer stack 64 and the substrate 50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures 55 by etching the multi-layer stack 64 may further define first nanostructures 52A-52C (collectively referred to as the first nanostructures 52) from the first semiconductor layers 51 and define second nanostructures 54A-54C (collectively referred to as the second nanostructures 54) from the second semiconductor layers 53. The first nanostructures 52 and the second nanostructures 54 may be collectively referred to as nanostructures 55.
The fins 66 and the nanostructures 55 may be patterned by any suitable method. For example, the fins 66 and the nanostructures 55 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.
FIG. 3 illustrates the fins 66 in the n-type region 50N and the p-type region 50P as having substantially equal widths for illustrative purposes. In some embodiments, widths of the fins 66 in the n-type region 50N may be greater or thinner than the fins 66 in the p-type region 50P. Further, while each of the fins 66 and the nanostructures 55 are illustrated as having a consistent width throughout, in other embodiments, the fins 66 and/or the nanostructures 55 may have tapered sidewalls such that a width of each of the fins 66 and/or the nanostructures 55 continuously increases in a direction towards the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.
In FIG. 4, shallow trench isolation (STI) regions 68 are formed adjacent the fins 66. The STI regions 68 may be formed by depositing an insulation material over the substrate 50, the fins 66, and nanostructures 55, and between adjacent fins 66. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures 55. Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along a surface of the substrate 50, the fins 66, and the nanostructures 55. Thereafter, a fill material, such as those discussed above may be formed over the liner.
A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures 55. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures 55 such that top surfaces of the nanostructures 55 and the insulation material are level after the planarization process is complete.
The insulation material is then recessed to form the STI regions 68. The insulation material is recessed such that upper portions of fins 66 in the n-type region 50N and the p-type region 50P protrude from between neighboring STI regions 68. Further, the top surfaces of the STI regions 68 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 68 may be formed flat, convex, and/or concave by an appropriate etch. The STI regions 68 may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins 66 and the nanostructures 55). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.
The process described above with respect to FIGS. 2 through 4 is just one example of how the fins 66 and the nanostructures 55 may be formed. In some embodiments, the fins 66 and/or the nanostructures 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and/or the nanostructures 55. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together.
Additionally, the first semiconductor layers 51 (and resulting first nanostructures 52) and the second semiconductor layers 53 (and resulting second nanostructures 54) are illustrated and discussed herein as comprising the same materials in the p-type region 50P and the n-type region 50N for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.
Further in FIG. 4, appropriate wells (not separately illustrated) may be formed in the fins 66, the nanostructures 55, and/or the STI regions 68. In embodiments with different well types, different implant steps for the n-type region 50N and the p-type region 50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins 66 and the STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about 1013 atoms/cm3 to about 1014 atoms/cm3. After the implant, the photoresist is removed, such as by an acceptable ashing process.
Following or prior to the implanting of the p-type region 50P, a photoresist or other masks (not separately illustrated) is formed over the fins 66, the nanostructures 55, and the STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region 50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 1013 atoms/cm3 to about 1014 atoms/cm3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.
After the implants of the n-type region 50N and the p-type region 50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.
In FIG. 5, a dummy dielectric layer 70 is formed on the fins 66 and/or the nanostructures 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, such as by a CMP. The mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), and poly-crystalline silicon-germanium (poly-SiGe). The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials that have a high etching selectivity from the etching of isolation regions. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It is noted that the dummy dielectric layer 70 is shown covering only the fins 66 and the nanostructures 55 for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI regions 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI regions 68.
FIGS. 6A through 18C illustrate various additional steps in the manufacturing of embodiment devices. FIGS. 6A through 18C illustrate features in either the n-type region 50N or the p-type region 50P. In FIGS. 6A through 6C, the mask layer 74 (see FIG. 5) may be patterned using acceptable photolithography and etching techniques to form masks 78. The pattern of the masks 78 then may be transferred to the dummy gate layer 72 and to the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the fins 66. The pattern of the masks 78 may be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins 66.
In FIGS. 7A through 7C, a first spacer layer 80 and a second spacer layer 82 are formed over the structures illustrated in FIGS. 6A through 6C. The first spacer layer 80 and the second spacer layer 82 will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. In FIGS. 7A through 7C, the first spacer layer 80 is formed on top surfaces of the STI regions 68; top surfaces and sidewalls of the fins 66, the nanostructures 55, and the masks 78; and sidewalls of the dummy gates 76 and the dummy gate dielectric 71. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer 82 may be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.
After the first spacer layer 80 is formed and prior to forming the second spacer layer 82, implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above in FIG. 4, a mask, such as a photoresist, may be formed over the n-type region 50N, while exposing the p-type region 50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in a range from about 1×1015 atoms/cm3 to about 1×1019 atoms/cm3. An anneal may be used to repair implant damage and to activate the implanted impurities.
In FIGS. 8A through 8C, the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83. As will be discussed in greater detail below, the first spacers 81 and the second spacers 83 act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of the fins 66 and/or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 may act as an etch stop layer when patterning the second spacer layer 82 and such that the second spacer layer 82 may act as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 may be etched using an anisotropic etch process wherein the first spacer layer 80 acts as an etch stop layer, wherein remaining portions of the second spacer layer 82 form second spacers 83 as illustrated in FIG. 8B. Thereafter, the second spacers 83 acts as a mask while etching exposed portions of the first spacer layer 80, thereby forming first spacers 81 as illustrated in FIGS. 8B and 8C.
As illustrated in FIG. 8B, the first spacers 81 and the second spacers 83 are disposed on sidewalls of the fins 66 and/or nanostructures 55. As illustrated in FIG. 8C, in some embodiments, the second spacer layer 82 may be removed from over the first spacer layer 80 adjacent the masks 78, the dummy gates 76, and the dummy gate dielectrics 71, and the first spacers 81 are disposed on sidewalls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 60. In other embodiments, a portion of the second spacer layer 82 may remain over the first spacer layer 80 adjacent the masks 78, the dummy gates 76, and the dummy gate dielectrics 71.
It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers 81 may be patterned prior to depositing the second spacer layer 82), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps.
In FIGS. 9A through 9C, first recesses 86 and second recesses 87 are formed in the fins 66, the nanostructures 55, and the substrate 50, in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the first recesses 86 and first epitaxial materials and epitaxial source/drain regions will be subsequently formed in the second recesses 87. The first recesses 86 and the second recesses 87 may extend through the first nanostructures 52 and the second nanostructures 54, and into the substrate 50. As illustrated in FIG. 9B, top surfaces of the STI regions 58 may be level with bottom surfaces of the first recesses 86. In various embodiments, the fins 66 may be etched such that bottom surfaces of the first recesses 86 are disposed below the top surfaces of the STI regions 68 or the like. Bottom surfaces of the second recesses 87 may be disposed below the bottom surfaces of the first recesses 86 and the top surfaces of the STI regions 68. The first recesses 86 and the second recesses 87 may be formed by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 78 mask portions of the fins 66, the nanostructures 55, and the substrate 50 during the etching processes used to form the first recesses 86 and the second recesses 87. A single etch process or multiple etch processes may be used to etch each layer of the nanostructures 55 and/or the fins 66. Timed etch processes may be used to stop the etching after the first recesses 86 and the second recesses 87 reach desired depths. The second recesses 87 may be etched by the same processes used to etch the first recesses 86 and an additional etch process before or after the first recesses 86 are etched. In some embodiments, regions corresponding to the first recesses 86 may be masked while the additional etch process for the second recesses 87 is performed.
In FIGS. 10A through 10C, portions of sidewalls of the layers of the multi-layer stack 64 formed of the first semiconductor materials (e.g., the first nanostructures 52) exposed by the first recesses 86 and the second recesses 87 are etched to form sidewall recesses 88. Although sidewalls of the first nanostructures 52 adjacent the sidewall recesses 88 are illustrated as being straight in FIG. 10C, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In an embodiment in which the first nanostructures 52 include, e.g., SiGe, and the second nanostructures 54 include, e.g., Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of the first nanostructures 52.
In FIGS. 11A through 11D, first inner spacers 90 are formed in the sidewall recess 88. The first inner spacers 90 may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated in FIGS. 10A through 10C. The first inner spacers 90 act as isolation features between subsequently formed source/drain regions and a gate structure. As will be discussed in greater detail below, source/drain regions and epitaxial materials will be formed in the first recesses 86 and the second recesses 87, while the first nanostructures 52 will be replaced with corresponding gate structures.
The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the first inner spacers 90. Although outer sidewalls of the first inner spacers 90 are illustrated as being flush with sidewalls of the second nanostructures 54, the outer sidewalls of the first inner spacers 90 may extend beyond or be recessed from sidewalls of the second nanostructures 54.
Moreover, although the outer sidewalls of the first inner spacers 90 are illustrated as being straight in FIG. 11C, the outer sidewalls of the first inner spacers 90 may be concave or convex. As an example, FIG. 11D illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from sidewalls of the second nanostructures 54. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like. The first inner spacers 90 may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions 92, discussed below with respect to FIGS. 12A through 12E) by subsequent etching processes, such as etching processes used to form gate structures.
In FIGS. 12A through 12E, first epitaxial materials 91 are formed in the second recesses 87 and epitaxial source/drain regions 92 are formed in the first recesses 86 and the second recesses 87. In some embodiments, the first epitaxial materials 91 may be sacrificial materials, which are subsequently removed to form backside vias (such as the backside vias 130, discussed below with respect to FIGS. 26A through 26D). As illustrated in FIGS. 12B through 12E, top surfaces of the first epitaxial materials 91 may be level with bottom surfaces of the first recesses 86. However, in some embodiments, top surfaces of the first epitaxial materials 91 may be disposed above or below bottom surfaces of the first recesses 86. The first epitaxial materials 91 may be epitaxially grown in the second recesses 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial materials 91 may include any acceptable material, such as silicon germanium or the like. The first epitaxial materials 91 may be formed of materials having high etch selectivity to materials of the epitaxial source/drain regions 92, the substrate 50, and dielectric layers (such as the STI regions 68 and second dielectric layers 125, discussed below with respect to FIGS. 24A through 24C). As such, the first epitaxial materials 91 may be removed and replaced with the backside vias without significantly removing the epitaxial source/drain regions 92 and the dielectric layers.
The epitaxial source/drain regions 92 are then formed in the first recesses 86 and over the first epitaxial materials 91 in the second recesses 87. In some embodiments, the epitaxial source/drain regions 92 may exert stress on the second nanostructures 54, thereby improving performance. As illustrated in FIG. 12C, the epitaxial source/drain regions 92 are formed in the first recesses 86 and the second recesses 87 such that each dummy gate 76 is disposed between respective neighboring pairs of the epitaxial source/drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source/drain regions 92 from the dummy gates 76 and the first inner spacers 90 are used to separate the epitaxial source/drain regions 92 from the nanostructures 55 by an appropriate lateral distance so that the epitaxial source/drain regions 92 do not short out with subsequently formed gates of the resulting nano-FETs.
The epitaxial source/drain regions 92 in the n-type region 50N, e.g., the NMOS region, may be formed by masking the p-type region 50P, e.g., the PMOS region. Then, the epitaxial source/drain regions 92 are epitaxially grown in the first recesses 86 and the second recesses 87 in the n-type region 50N. The epitaxial source/drain regions 92 may include any acceptable material appropriate for n-type nano-FETs. For example, if the second nanostructures 54 are silicon, the epitaxial source/drain regions 92 may include materials exerting a tensile strain on the second nanostructures 54, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions 92 may have surfaces raised from respective upper surfaces of the nanostructures 55 and may have facets.
The epitaxial source/drain regions 92 in the p-type region 50P, e.g., the PMOS region, may be formed by masking the n-type region 50N, e.g., the NMOS region. Then, the epitaxial source/drain regions 92 are epitaxially grown in the first recesses 86 and the second recesses 87 in the p-type region 50P. The epitaxial source/drain regions 92 may include any acceptable material appropriate for p-type nano-FETs. For example, if the first nanostructures 52 are silicon germanium, the epitaxial source/drain regions 92 may comprise materials exerting a compressive strain on the first nanostructures 52, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions 92 may also have surfaces raised from respective surfaces of the multi-layer stack 56 and may have facets.
The epitaxial source/drain regions 92, the first nanostructures 52, the second nanostructures 54, and/or the substrate 50 may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×1019 atoms/cm3 and about 1×1021 atoms/cm3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 92 may be in situ doped during growth.
As a result of the epitaxy processes used to form the epitaxial source/drain regions 92 in the n-type region 50N and the p-type region 50P, upper surfaces of the epitaxial source/drain regions 92 have facets which expand laterally outward beyond sidewalls of the nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source/drain regions 92 of a same nano-FET to merge as illustrated by FIG. 12B. In other embodiments, adjacent epitaxial source/drain regions 92 remain separated after the epitaxy process is completed as illustrated by FIG. 12D. In the embodiments illustrated in FIGS. 12B and 12D, the first spacers 81 may be formed to a top surface of the STI regions 68 thereby blocking the epitaxial growth. In some other embodiments, the first spacers 81 may cover portions of the sidewalls of the nanostructures 55 further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 58.
The epitaxial source/drain regions 92 may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions 92 may comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments in which the epitaxial source/drain regions 92 comprise three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.
FIG. 12E illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from sidewalls of the second nanostructures 54. As illustrated in FIG. 12E, the epitaxial source/drain regions 92 may be formed in contact with the first inner spacers 90 and may extend past sidewalls of the second nanostructures 54.
In FIGS. 13A through 13C, a first interlayer dielectric (ILD) 96 is deposited over the structure illustrated in FIGS. 12A through 12C. The first ILD 96 may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source/drain regions 92, the masks 78, and the first spacers 81. The CESL 94 may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD 96.
In FIGS. 14A through 14C, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD 96 with the top surfaces of the dummy gates 76 or the masks 78. The planarization process may also remove the masks 78 on the dummy gates 76, and portions of the first spacers 81 along sidewalls of the masks 78. After the planarization process, top surfaces of the dummy gates 76, the first spacers 81, and the first ILD 96 are level within process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed through the first ILD 96. In some embodiments, the masks 78 may remain, in which case the planarization process levels the top surface of the first ILD 96 with top surface of the masks 78 and the first spacers 81.
In FIGS. 15A through 15C, the dummy gates 76, and the masks 78 if present, are removed in one or more etching steps, so that third recesses 98 are formed. Portions of the dummy gate dielectrics 60 in the third recesses 98 are also be removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 60 are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates 76 at a faster rate than the first ILD 96 or the first spacers 81. Each of the third recess 98 exposes and/or overlies portions of nanostructures 55, which act as channel regions in subsequently completed nano-FETs. Portions of the nanostructures 55 which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions 92. During the removal, the dummy gate dielectrics 60 may be used as etch stop layers when the dummy gates 76 are etched. The dummy gate dielectrics 60 may then be removed after the removal of the dummy gates 76.
In FIGS. 16A through 16C, the first nanostructures 52 are removed extending the third recesses 98. The first nanostructures 52 may be removed by performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, the STI regions 58 remain relatively unetched as compared to the first nanostructures 52. In embodiments in which the first nanostructures 52 include, e.g., SiGe, and the second nanostructures 54A-54C include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructures 52.
In FIGS. 17A through 17C, gate dielectric layers 100 and gate electrodes 102 are formed for replacement gates. The gate dielectric layers 100 are deposited conformally in the third recesses 98. The gate dielectric layers 100 may be formed on top surfaces and sidewalls of the substrate 50 and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures 54. The gate dielectric layers 100 may also be deposited on top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the STI regions 68 and on sidewalls of the first spacers 81 and the first inner spacers 90.
In accordance with some embodiments, the gate dielectric layers 100 comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, in some embodiments, the gate dielectrics may comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers 100 include a high-k dielectric material, and in these embodiments, the gate dielectric layers 100 may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation methods of the gate dielectric layers 100 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.
The gate electrodes 102 are deposited over the gate dielectric layers 100, respectively, and fill the remaining portions of the third recesses 98. The gate electrodes 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although single layer gate electrodes 102 are illustrated in FIGS. 17A and 17C, the gate electrodes 102 may comprise any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers which make up the gate electrodes 102 may be deposited in the n-type region 50N between adjacent ones of the second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent ones of the first nanostructures 52.
The formation of the gate dielectric layers 100 in the n-type region 50N and the p-type region 50P may occur simultaneously such that the gate dielectric layers 100 in each region are formed from the same materials, and the formation of the gate electrodes 102 may occur simultaneously such that the gate electrodes 102 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region may be formed by distinct processes, such that the gate dielectric layers 100 may be different materials and/or have a different number of layers, and/or the gate electrodes 102 in each region may be formed by distinct processes, such that the gate electrodes 102 may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.
After the filling of the third recesses 98, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers 100 and the material of the gate electrodes 102, which excess portions are over the top surface of the first ILD 96. The remaining portions of material of the gate electrodes 102 and the gate dielectric layers 100 thus form replacement gate structures of the resulting nano-FETs. The gate electrodes 102 and the gate dielectric layers 100 may be collectively referred to as “gate structures.”
In FIGS. 18A through 18C, the gate structures (including the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) are recessed, so that recess are formed directly over the gate structures and between opposing portions of first spacers 81. Gate masks 104 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled in the recesses, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. Subsequently formed gate contacts (such as the gate contacts 114, discussed below with respect to FIGS. 20A through 20C) penetrate through the gate masks 104 to contact the top surfaces of the recessed gate electrodes 102.
As further illustrated by FIGS. 18A through 18C, a second ILD 106 is deposited over the first ILD 96 and over the gate masks 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.
In FIGS. 19A through 19C, the second ILD 106, the first ILD 96, the CESL 94, and the gate masks 104 are etched to form fourth recesses 108 exposing surfaces of the epitaxial source/drain regions 92 and/or the gate structures. The fourth recesses 108 may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the fourth recesses 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; may be etched through the gate masks 104 using a second etching process; and may then be etched through the CESL 94 using a third etching process. A mask, such as a photoresist, may be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the fourth recesses 108 extend into the epitaxial source/drain regions 92 and/or the gate structures, and a bottom of the fourth recesses 108 may be level with (e.g., at a same level, or having a same distance from the substrate 50), or lower than (e.g., closer to the substrate 50) the epitaxial source/drain regions 92 and/or the gate structures. Although FIG. 19C illustrates the fourth recesses 108 as exposing the epitaxial source/drain regions 92 and the gate structures in a same cross-section, in various embodiments, the epitaxial source/drain regions 92 and the gate structures may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts.
After the fourth recesses 108 are formed, first silicide regions 110 are formed over the epitaxial source/drain regions 92. In some embodiments, the first silicide regions 110 are formed by first depositing a metal (not separately illustrated) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions 92 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions 92, then performing a thermal anneal process to form the first silicide regions 110. The un-reacted portions of the deposited metal are then removed, e.g., by an etching process. Although the first silicide regions 110 are referred to as silicide regions, the first silicide regions 110 may also be germanide regions, or silicon germanide regions (e.g., regions comprising silicide and germanide).
In FIGS. 20A through 20C, source/drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in the fourth recesses 108. The source/drain contacts 112 and the gate contacts 114 may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the source/drain contacts 112 and the gate contacts 114 each include a barrier layer and a conductive material, and are each electrically coupled to an underlying conductive feature (e.g., a gate electrode 102 and/or a first silicide region 110). The gate contacts 114 are electrically coupled to the gate electrodes 102 and the source/drain contacts 112 are electrically coupled to the first silicide regions 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from surfaces of the second ILD 106. The epitaxial source/drain regions 92, the second nanostructures 54, and the gate structures (including the gate dielectric layers 100 and the gate electrodes 102) may collectively be referred to as transistor structures 109. The transistor structures 109 may be formed in a device layer, with a first interconnect structure (such as the front-side interconnect structure 120, discussed below with respect to FIGS. 21A through 21C) being formed over a front-side thereof and a second interconnect structure (such as the backside interconnect structure 136, discussed below with respect to FIGS. 36A through 36C) being formed over a backside thereof. Although the device layer is described as having nano-FETs, other embodiments may include a device layer having different types of transistors (e.g., planar FETs, finFETs, thin film transistors (TFTs), or the like).
Although FIGS. 20A through 20C illustrate a source/drain contact 112 extending to each of the epitaxial source/drain regions 92, the source/drain contacts 112 may be omitted from certain ones of the epitaxial source/drain regions 92. For example, as explained in greater detail below, conductive features (e.g., backside vias or power rails) may be subsequently attached through a backside of one or more of the epitaxial source/drain regions 92. For these particular epitaxial source/drain regions 92, the source/drain contacts 112 may be omitted or may be dummy contacts that are not electrically connected to any overlying conductive lines (such as the first conductive features 122, discussed below with respect to FIGS. 21A through 21C).
FIGS. 21A through 36C illustrate intermediate steps of forming front-side interconnect structures and backside interconnect structures on the transistor structures 109. The front-side interconnect structures and the backside interconnect structures may each comprise conductive features that are electrically connected to the nano-FETs formed on the substrate 50. The process steps described in FIGS. 21A through 36C may be applied to both the n-type region 50N and the p-type region 50P. As noted above, a back-side conductive feature (e.g., a backside via or a power rail) may be connected to one or more of the epitaxial source/drain regions 92. As such, the source/drain contacts 112 may be optionally omitted from the epitaxial source/drain regions 92.
In FIGS. 21A through 21C, a front-side interconnect structure 120 is formed on the second ILD 106. The front-side interconnect structure 120 may be referred to as a front-side interconnect structure because it is formed on a front-side of the transistor structures 109 (e.g., a side of the transistor structures 109 on which active devices are formed).
The front-side interconnect structure 120 may comprise one or more layers of first conductive features 122 formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 may comprise a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. The first dielectric layers 124 may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like.
The first conductive features 122 may comprise conductive lines and conductive vias interconnecting the layers of conductive lines. The conductive vias may extend through respective ones of the first dielectric layers 124 to provide vertical connections between layers of the conductive lines. The first conductive features 122 may be formed through any acceptable process, such as, a damascene process, a dual damascene process, or the like.
In some embodiments, the first conductive features 122 may be formed using a damascene process in which a respective first dielectric layer 124 is patterned utilizing a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of the first conductive features 122. An optional diffusion barrier and/or optional adhesion layer may be deposited and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the first conductive features 122 may be formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the respective first dielectric layer 124 and to planarize surfaces of the first dielectric layer 124 and the first conductive features 122 for subsequent processing.
FIGS. 21A through 21C illustrate five layers of the first conductive features 122 and the first dielectric layers 124 in the front-side interconnect structure 120. However, it should be appreciated that the front-side interconnect structure 120 may comprise any number of first conductive features 122 disposed in any number of first dielectric layers 124. The front-side interconnect structure 120 may be electrically connected to the gate contacts 114 and the source/drain contacts 112 to form functional circuits. In some embodiments, the functional circuits formed by the front-side interconnect structure 120 may comprise logic circuits, memory circuits, image sensor circuits, or the like.
In FIGS. 22A through 22C, a carrier substrate 150 is bonded to a top surface of the front-side interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B (collectively referred to as a bonding layer 152). The carrier substrate 150 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. The carrier substrate 150 may provide structural support during subsequent processing steps and in the completed device.
In various embodiments, the carrier substrate 150 may be bonded to the front-side interconnect structure 120 using a suitable technique, such as dielectric-to-dielectric bonding, or the like. The dielectric-to-dielectric bonding may comprise depositing the first bonding layer 152A on the front-side interconnect structure 120. In some embodiments, the first bonding layer 152A comprises silicon oxide (e.g., a high density plasma (HDP) oxide, or the like) that is deposited by CVD, ALD, PVD, or the like. The second bonding layer 152B may likewise be an oxide layer that is formed on a surface of the carrier substrate 150 prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials may be used for the first bonding layer 152A and the second bonding layer 152B.
The dielectric-to-dielectric bonding process may further include applying a surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water or the like) that may be applied to one or more of the bonding layers 152. The carrier substrate 150 is then aligned with the front-side interconnect structure 120 and the two are pressed against each other to initiate a pre-bonding of the carrier substrate 150 to the front-side interconnect structure 120. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). After the pre-bonding, an annealing process may be applied by, for example, heating the front-side interconnect structure 120 and the carrier substrate 150 to a temperature of about 170° C.
Further in FIGS. 22A through 22C, after the carrier substrate 150 is bonded to the front-side interconnect structure 120, the device may be flipped such that a backside of the transistor structures 109 faces upwards. The backside of the transistor structures 109 may refer to a side opposite to the front-side of the transistor structures 109 on which the active devices are formed.
In FIGS. 23A through 23C, a thinning process may be applied to the backside of the substrate 50. The thinning process may comprise a planarization process (e.g., a mechanical grinding, a CMP, or the like), an etch-back process, a combination thereof, or the like. The thinning process may expose surfaces of the first epitaxial materials 91 opposite the front-side interconnect structure 120. Further, a portion of the substrate 50 may remain over the gate structures (e.g., the gate electrodes 102 and the gate dielectric layers 100) and the nanostructures 55 after the thinning process. As illustrated in FIGS. 23A through 23C, backside surfaces of the substrate 50, the first epitaxial materials 91, the STI regions 68, and the fins 66 may be level with one another following the thinning process.
In FIGS. 24A through 24C, remaining portions of the fins 66 and the substrate 50 are removed and replaced with a second dielectric layer 125. The fins 66 and the substrate 50 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The etching process may be one that is selective to the material of the fins 66 and the substrate 50 (e.g., etches the material of the fins 66 and the substrate 50 at a faster rate than the material of the STI regions 68, the gate dielectric layers 100, the epitaxial source/drain regions 92, and the first epitaxial materials 91). After etching the fins 66 and the substrate 50, surfaces of the STI regions 68, the gate dielectric layers 100, the epitaxial source/drain regions 92, and the first epitaxial materials 91 may be exposed.
The second dielectric layer 125 is then deposited on the backside of the transistor structures 109 in recesses formed by removing the fins 66 and the substrate 50. The second dielectric layer 125 may be deposited over the STI regions 68, the gate dielectric layers 100, and the epitaxial source/drain regions 92. The second dielectric layer 125 may physically contact surfaces of the STI regions 68, the gate dielectric layers 100, the epitaxial source/drain regions 92, and the first epitaxial materials 91. The second dielectric layer 125 may be substantially similar to the second ILD 106, described above with respect to FIGS. 18A through 18C. For example, the second dielectric layer 125 may be formed of a like material and using a like process as the second ILD 106. As illustrated in FIGS. 24A through 24C, a CMP process or the like may be used to remove material of the second dielectric layer 125 such that top surfaces of the second dielectric layer 125 are level with top surfaces of the STI regions 68 and the first epitaxial materials 91. Note that in the discussion herein, the term “a like material” (or “a like process”) is used to refer to the same or a similar material (or process).
In FIGS. 25A through 25C, the first epitaxial materials 91 are removed to form fifth recesses 128 and second silicide regions 129 are formed in the fifth recesses 128. The first epitaxial materials 91 may be removed by a suitable etching process, which may be an isotropic etching process, such as a wet etching process. The etching process may have a high etch selectivity to materials of the first epitaxial materials 91. As such, the first epitaxial materials 91 may be removed without significantly removing materials of the second dielectric layer 125, the STI regions 68, or the epitaxial source/drain regions 92. The fifth recesses 128 may expose sidewalls of the STI regions 68, backside surfaces of the epitaxial source/drain regions 92, and sidewalls of the second dielectric layer 125.
Second silicide regions 129 may then be formed in the fifth recesses 128 on backsides of the epitaxial source/drain regions 92. The second silicide regions 129 may be similar to the first silicide regions 110, described above with respect to FIGS. 19A through 19C. For example, the second silicide regions 129 may be formed of a like material and using a like process as the first silicide regions 110.
In FIGS. 26A through 26C, backside vias 130 are formed in the fifth recesses 128. The backside vias 130 may extend through the second dielectric layer 125 and the STI regions 68 and may be electrically coupled to the epitaxial source/drain regions 92 through the second silicide regions 129. The backside vias 130 may be similar to the source/drain contacts 112, described above with respect to FIGS. 20A through 20C. For example, the backside vias 130 may be formed of a like material and using a like process as the source/drain contacts 112.
Next, in FIG. 27A through 36C, a backside interconnect structure 136 having embedded metal-insulator-metal (MIM) capacitors 147 (may also be referred to as decoupling capacitors 147) are formed. In some embodiments, the backside interconnect structure 136 is used to distribute power for the semiconductor device formed, and may be referred to as backside power distribution network (PDN). Besides distributing power, the disclosed backside interconnect structure 136 includes integrated MIM capacitors, and achieves a capacitance density of about 100 fF/μm2 or higher. The integrated MIM capacitors may be used to form power circuits and/or to stabilize reference voltages in the PDN, thus achieving improved performance for the device formed.
In FIGS. 27A through 27D, conductive lines 134 and a third dielectric layer 132 are formed over the second dielectric layer 125, the STI regions 68, and the backside vias 130. The third dielectric layer 132 may be similar to the second dielectric layer 125. For example, third dielectric layer 132 may be formed of a like material and using a like process as the second dielectric layer 125.
The conductive lines 134 are formed in the third dielectric layer 132. Forming the conductive lines 134 may include patterning recesses in the third dielectric layer 132 using a combination of photolithography and etching processes, for example. A pattern of the recesses in the third dielectric layer 132 may correspond to a pattern of the conductive lines 134. The conductive lines 134 are then formed by depositing a conductive material in the recesses. In some embodiments, the conductive lines 134 comprise a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the conductive lines 134 comprise copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like. An optional diffusion barrier and/or optional adhesion layer may be deposited prior to filling the recesses with the conductive material. Suitable materials for the barrier layer/adhesion layer include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive lines 134 may be formed using, for example, CVD, ALD, PVD, plating or the like. The conductive lines 134 are physically and electrically coupled to the epitaxial source/drain regions 92 through the backside vias 130 and the second silicide regions 129. A planarization process (e.g., a CMP, a grinding, an etch-back, or the like) may be performed to remove excess portions of the conductive lines 134 formed over the third dielectric layer 132.
In some embodiments, the conductive lines 134 are power rails, which are conductive lines that electrically connect the epitaxial source/drain regions 92 to a reference voltage, a supply voltage, or the like. By placing power rails on a backside of the resulting semiconductor die rather than on a front-side of the semiconductor die, advantages may be achieved. For example, a gate density of the nano-FETs and/or interconnect density of the front-side interconnect structure 120 may be increased. Further, the backside of the semiconductor die may accommodate wider power rails, reducing resistance and increasing efficiency of power delivery to the nano-FETs. For example, a width of the conductive lines 134 may be at least twice a width of first level conductive lines (e.g., first conductive features 122) of the front-side interconnect structure 120.
FIG. 27D illustrates an embodiment in which the epitaxial source/drain regions 92 to which the backside vias 130 are electrically coupled have heights greater than the epitaxial source/drain regions 92 which are not electrically coupled to the backside vias 130. The heights of the epitaxial source/drain regions 92 may be selected by controlling depths of the first recesses 86 and the second recesses 87 and/or controlling the thickness of the first epitaxial materials 91. Forming the epitaxial source/drain regions 92 which are not electrically coupled to the backside vias 130 with heights less than the epitaxial source/drain regions 92 which are electrically coupled to the backside vias 130 results in the epitaxial source/drain regions 92 which are not electrically coupled to the backside vias 130 being separated from the conductive lines 134 by a greater thickness of the second dielectric layer 125. This provides better isolation of the epitaxial source/drain regions 92 which are not electrically coupled to the backside vias 130 from the conductive lines 134 and improves device performance.
In FIGS. 28 through 36C, remaining portions of the backside interconnect structure 136 are formed over the third dielectric layer 132 and the conductive lines 134. The backside interconnect structure 136 may be referred to as a backside interconnect structure because it is formed on a backside of the transistor structures 109 (e.g., a side of the transistor structures 109 opposite the side of the transistor structure 109 on which active devices are formed). The backside interconnect structure 136 (see, e.g., FIG. 35A) may comprise the third dielectric layer 132 and the conductive lines 134. The backside interconnect structure 136 may further comprise conductive lines 140A-140C (collectively referred to as conductive lines 140) and conductive vias 139A-139C (collectively referred to as conductive vias 139) formed in fourth dielectric layers 138A-138F (collectively referred to as fourth dielectric layers 138). In addition, the backside interconnect structure 136 may include etch stop layers 141A-141F (collectively referred to as etch stop layers 141) formed between adjacent dielectric layers of the backside interconnect structure 136. The conductive vias 139 (may be referred to as vias 139) may extend through respective ones of the fourth dielectric layers 138 and respective ones of the etch stop layers 141 to provide vertical connections between layers of the conductive lines 140.
A power supply voltage VDD (which may be a positive power supply voltage) and a power supply voltage VSS (which may be an electrical ground or a negative power supply voltage) may be routed through the conductive lines 140, and MIM capacitors 147 (e.g., decoupling capacitors) may be formed in the backside interconnect structure 136. The MIM capacitors 147 may be formed in any of the fourth dielectric layers 138. In addition, the MIM capacitors 147 may be formed in the third dielectric layer 132. In some embodiments, the process to form the MIM capacitors 147 in the third dielectric layer 132 or in the fourth dielectric layers 138 having vias 139 may be more complex than the process to form the MIM capacitors 147 in the fourth dielectric layers 138 having the conductive lines 140, and therefore, the MIM capacitors 147 are formed only in the fourth dielectric layers 138 having the conductive lines 140. These and other variations are fully intended to be included within the scope of the present disclosure.
In some embodiments, the fourth dielectric layers 138 are formed of a low-k dielectric material(s) or an extra low-k (ELK) dielectric material(s). Examples of the low-k or extra low-k dielectric material include fluorine-doped silicon oxide, carbon-doped silicon oxide (CDO), porous silicon oxide, or the like. The fourth dielectric layers 138 may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like. Using low-k or extra low-k dielectric materials may advantageously reduce the parasitic capacitance of the device formed, thereby reducing RC delay and improve device performance. As will be discussed hereinafter, in regions where the MIM capacitors 147 are formed, portions of the low-k or extra low-k dielectric material are replaced with a high-k dielectric material, because high-k dielectric material increases the capacitance density of the MIM capacitors 147 formed. By using both low-k (or extra low-k) dielectric material(s) and high-k dielectric material(s) in the fourth dielectric layers 138 having the MIM capacitors 147, a balance of performance requirements between reduced RC delay and higher capacitance density is achieved.
To avid cluttering and to show details of the backside interconnect structure 136, FIGS. 28 through 35B illustrate the backside interconnect structure 136 without showing other portions of the semiconductor device (e.g., portions below the third dielectric layer 132 in FIGS. 27A-27D).
Referring now to FIGS. 28 and 29. In FIG. 28, an etch stop layer 141A and a fourth dielectric layer 138A are formed successively on the third dielectric layer 132. Vias 139A are formed to extend through the fourth dielectric layer 138A and the etch stop layer 141A, and to be electrically coupled to respective ones of the conductive lines 134. Next, in FIG. 29, an etch stop layer 141B and a fourth dielectric layer 138B are formed successively on the fourth dielectric layer 138A, and conductive lines 140A are formed in the fourth dielectric layer 138B. At least some of the conductive lines 140A extend through the fourth dielectric layer 138B and the etch stop layer 141B, and are electrically coupled to respective ones of the vias 139A. Some of the conductive lines 140A may not be coupled to underlying vias 139A, and may be used for routing electrical signals within the fourth dielectric layer 138B.
The etch stop layer 141 (e.g., 141A or 141B) may be formed of a suitable material such as silicon nitride, silicon oxynitride, silicon carbide, or the like, using a suitable formation method such as CVD, PECVD, ALD, or the like. The fourth dielectric layer 138 (e.g., 138A or 138B) is formed on the respective etch stop layer 141 using a low-k or extra low-k dielectric materials.
The conductive vias 139 and the conductive lines 140 may be formed using any acceptable process, such as, a damascene process, a dual damascene process, or the like. In some embodiments, the conductive vias 139 (or the conductive lines 140) may be formed using damascenes processes in which a respective fourth dielectric layer 138 and a respective etch stop layer 141 are patterned utilizing a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of the conductive vias 139 (or the conductive lines 140). An optional diffusion barrier and/or optional adhesion layer may be deposited and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the conductive vias 139 (or the conductive lines 140) may be formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the respective fourth dielectric layer 138 and to planarize surfaces of the fourth dielectric layer 138 and the conductive vias 139 (or the conductive lines 140) for subsequent processing.
Next, in FIG. 30, portions of the fourth dielectric layer 138B in a region 142 of the fourth dielectric layer 138B are removed, e.g., by a suitable etching process such as an anisotropic etching process. An etching mask (not shown) may be used to cover areas of the fourth dielectric layer 138B outside the region 142 and to expose areas of the fourth dielectric layer 138B inside the region 142. Portions of the fourth dielectric layer 138B exposed by the etching mask are removed. As illustrated in FIG. 30, after removal of the portions of the fourth dielectric layer 138B, openings 149 are formed in the region 142 of the fourth dielectric layer 138. The openings 149 exposes upper surfaces and sidewalls of some of the conductive lines 140A in the region 142 of the fourth dielectric layer 138B. In the example of FIG. 30, the etch stop layer 141B is exposed at the bottom of the openings 149, e.g., due to the etching process used to remove the fourth dielectric layer 138B being selective to (e.g., having a higher etching rate for) the material of the fourth dielectric layer 138B.
Next, in FIG. 31, a barrier material 143 is formed (e.g., conformally) over the structure in FIG. 30. The barrier material 143 may be tantalum nitride, titanium nitride, tantalum, titanium, or the like, and may be formed by a suitable formation method such as CVD, PVD, PECVD, ALD, or the like. As illustrated in FIG. 31, the barrier material 143 extends along sidewalls and upper surfaces of the conductive lines 140A in the region 142 and along the upper surface of the fourth dielectric layer 138B.
Next, in FIG. 32, the barrier material 143 is etched by, e.g., an anisotropic etching process. In some embodiments, the anisotropic etching process removes portions of the barrier material 143 from the upper surface of the fourth dielectric layer 138B and from the bottoms of the openings 149. The anisotropic etching process also removes portions of the etch stop layer 141B at the bottoms of the openings 149, in some embodiments. Remaining portions of the barrier material 143, which extend along sidewalls of the conductive lines 140A in the region 142 or along sidewalls of the fourth dielectric layer 138B exposed by the openings 149, form barrier layers 143. In the example of FIG. 32, due to the conductive lines 140A having slanted sidewalls (e.g., having trapezoidal cross-sections) and due to the anisotropicity of the anisotropic etching process, some horizontal portions of the barrier material 143 (and the etch stop layer 141B) at the bottoms of the openings 149 adjacent to the conductive lines 104A remain after the anisotropic etching process. As a result, the barrier layers 143 along sidewalls of the conductive lines 104A have L-shaped cross-sections.
Next, in FIG. 33, a high-k dielectric material 145 is formed to fill the openings 149. The high-k dielectric material 145 may have a k-value great than about 7.0 (e.g., between about 7.0 and about 40), and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In some embodiments, the high-k dielectric material 145 is ZrO2, Al2O3, HFO2, Ta2O5, or TiO2. A suitable formation method, such as CVD, PECVD, ALD, or the like, may be used to form the high-k dielectric material 145.
Next, in FIG. 34A, a planarization process, such as CMP, is performed to remove excess portions of the high-k dielectric material 145 from the upper surface of the fourth dielectric layer 138B, and to achieve a coplanar surface for the fourth dielectric layer 138B, the barrier layers 143, and the high-k dielectric material 145. After the planarization process, a plurality of MIM capacitors 147 are formed in the region 142 of the fourth dielectric layer 138B between adjacent conductive lines 140A. Each of the MIM capacitor 147 includes a first barrier layer 143 (labeled as 143A) along a first sidewall of a first conductive line 140A, a second barrier layer 143 (labeled as 143B) along a second sidewall of a second conductive line 140A adjacent to the first conductive line 140A, and the high-k dielectric material 145 between the first barrier layer 143A and the second barrier layer 143B. The high-k dielectric material 145 fills the space between the first barrier layer 143A and the second barrier layer 143B completely (e.g., extends continuously from the first barrier layer 143A to the second barrier layer 143B). In the example of FIG. 34A, the high-k dielectric material 145 includes a downward protrusion that extends through the etch stop layer 141B to the fourth dielectric layer 138A. An aspect ratio of the conductive line 140A, calculated as the ratio between the height of the conductive line 140 and the width of the conductive line 140A, may be about 2 or about 4, as an example. An aspect ratio of the high-k dielectric material 145 may be larger than 10, as an example.
FIG. 34B illustrates a top view of the conductive lines 140A, the barrier layers 143 around the conductive lines 140A, and the high-k dielectric material 145 between adjacent conductive lines 140A. Note that for simplicity and clarity, not all features are illustrated. In the example of FIG. 34B, the barrier layer 143 extends along (e.g., covers) all four sidewalls of each conductive line 140A. The barrier layers 143 along two opposing sidewalls of two adjacent conductive lines 140A and the high-k dielectric material 145 in between form an MIM capacitor 147. The barrier layers 143 (e.g., 143A and 134B) function as the electrodes of the capacitor, and the high-k dielectric material 145 function as the dielectric medium between the electrodes of the capacitor. In the illustrated embodiments, the MIM capacitor 147 is coupled between two adjacent conductive lines 140A. In some embodiments, the adjacent conductive lines 140 are used to route the supply voltages VDD (e.g., a positive power supply voltage) and VSS (e.g., electrical ground) in alternating orders. The MIM capacitors 147 may function as decoupling capacitors to stabilize the voltages on the conductive lines 140A. As a result, less voltage disturbance (also referred to as supply voltage noise) is observed on the conductive lines 140A, and the performance of the device formed is improved due to less supply voltage noise.
Next, in FIG. 35A, additional layers of the etch stop layers 141 (e.g., 141C, 141D, 141E, and 141F) and additional layers of the fourth dielectric layers 138 (e.g., 138C, 138D, 138E, and 138F) are formed over the fourth dielectric layer 138B. Additional layers of the vias 139 (e.g., 139B and 139C) and additional layers of the conductive lines 140 (e.g., 140B and 140C) are formed in alternating layers of the fourth dielectric layers 138, as illustrated in FIG. 35A. The material(s) and the formation method for the etch stop layer 141, the fourth dielectric layers 138, the vias 139, and the conductive lines 140 are same as or similar to those discussed above, thus details are not repeated.
Next, an etch stop layer 141G, a passivation layer 144, under bump metallization (UBM) structures 146, and external connectors 148 are formed over the backside interconnect structure 136. The etch stop layer 141G may be formed using the same or similar material as the etch stop layer 141F. The passivation layer 144 may comprise polymers such as PBO, polyimide, BCB, or the like. Alternatively, the passivation layer 144 may include non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer 144 may be deposited by, for example, CVD, PVD, ALD, or the like.
The UBM structures 146 are formed through the passivation layer 144 and the etch stop layer 141G to the conductive lines 140 in the backside interconnect structure 136, and external connectors 148 are formed on the UBM structures 146. The UBM structures 146 may comprise one or more layers of copper, nickel, gold, or the like, which are formed by a plating process, or the like. The external connectors 148 (e.g., solder balls, copper pillars, copper pillars with solder material on top) are formed on the UBM structures 146. The formation of the external connectors 148 may include placing solder balls on exposed portions of the UBM structures 146 and reflowing the solder balls. In some embodiments, the formation of the external connectors 148 includes performing a plating step to form solder regions over the topmost conductive lines 140C and then reflowing the solder regions. The UBM structures 146 and the external connectors 148 may be used to provide input/output connections to other electrical components, such as, other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like. The UBM structures 146 and the external connectors 148 may also be referred to as backside input/output pads that may provide signal, supply voltage, and/or ground connections to the nano-FETs described above.
FIG. 35A illustrates three layers of the conductive vias 139, three layers of the conductive lines 140, and six layers of the fourth dielectric layers 138 in the backside interconnect structure 136. However, it should be appreciated that the backside interconnect structure 136 may comprise any number of conductive vias 139 and conductive lines 140 disposed in any number of fourth dielectric layers 138. The backside interconnect structure 136 may be electrically connected to the conductive lines 134 (e.g., power rails) to provide circuits (e.g., power circuits) on the backside of the nano-FETs. In addition, although MIM capacitors 147 are illustrated to be formed in one of the fourth dielectric layers 138 (e.g., 138B), the MIM capacitors 147 may be formed in any of the fourth dielectric layers 138, as discussed above.
Recall that in the formation process for each of the vias 139 and the conductive lines 140 and 134, an optional barrier layer may be formed before the conductive material (e.g., copper) fills the trench in the dielectric layer (e.g., 138 or 132). This optional barrier layer, if formed, is not explicitly illustrated in FIG. 35A. Therefore, FIG. 35A may illustrate an embodiment where the optional barrier layer is not formed in the vias 139 and the conductive lines 140 and 134. However, for the conductive lines 140A in regions (e.g., 142) where the MIM capacitors 147 are formed, the barrier layers 143 are formed along the sidewalls of those conductive lines 140 in the regions, as illustrated in FIG. 35A.
FIG. 35A may also illustrate another embodiment where the optional barrier layer is formed for all of the vias 139 and the conductive lines 140 and 134. Although the optional barrier layer is not explicitly illustrated in FIG. 35A, skilled artisans will readily appreciate that the optional barrier may have the same or similar shape as the optional barrier layer 151 shown in FIG. 35B. In addition, for the conductive lines 140A in regions (e.g., 142) where the MIM capacitors 147 are formed, the barrier layers 143 are also formed along the sidewalls of those conductive lines 140, as illustrated in FIG. 35A. In other words, for the conductive lines 140A in regions (e.g., 142) where the MIM capacitors 147 are formed, double layers of barrier layers (e.g., 151 and 143) are formed along their sidewalls, and a single layer of barrier layer (e.g., 151) is formed along their bottoms. In contrast, the conductive lines 140 outside the regions (e.g., 142) have a single layer of barrier layer (e.g., 151) formed along their sidewalls and bottoms.
FIG. 35B illustrates an embodiment where the optional barrier layer 151 (e.g., TiN, TaN, Ti, Ta) is formed for all of the vias 139 and the conductive lines 140 and 134 in the backside interconnect structure 136, except the conductive lines 140A in the region 142 where the MIM capacitors 147 are formed. In some embodiments, during the processing step of FIG. 29, before the optional barrier layer 151 is formed for the conductive lines 140A in the fourth dielectric layer 138B, a patterned mask (e.g., a patterned photoresist) is formed to cover trenches (e.g., at locations of the subsequently formed conductive lines 140A) in the region 142 of the fourth dielectric layer 138B, such that the optional barrier layer 151 is formed for conductive lines 140 outside the region 142 only. The patterned mask layer is then removed, and the electrically conductive material is formed in the trenches to form the conductive lines 140A. As a result of the above described formation process for the optional barrier layer 151, the conductive lines 140A outside the region 142 have the optional barrier layer 151 formed along their sidewalls and their bottoms, whereas the conductive lines 140 in the region 142 have the barrier layers 143 formed along their sidewalls. Note that the bottoms of the conductive lines 140 in the region 142 are free of the barrier layers 151 and 143. In some embodiments, the electrical resistance of the material (e.g., TiN, TaN) of the barrier layers (e.g., 151, 143) is higher than the conductive material (e.g., Cu) of the conductive lines 140C. The example of FIG. 35B forms a single layer of barrier layer 143 along the sidewalls of the conductive lines 140A in the region 142, thus avoiding double layers of barrier layer being formed along the sidewalls of the conductive lines 140A in the region 142, which may reduce overall electrical resistance of the PDN and the power consumption of the MIM capacitors 147.
Including the decoupling capacitors 147 in the backside interconnect structure 136 between the conductive lines 140 for routing the power supply voltages VSS and VDD stabilizes the power supply voltages VSS and VDD, which results in improved device performance. Routing the power supply voltages VSS and VDD in the backside interconnect structure 136 and providing the decoupling capacitors 147 in the backside interconnect structure 136 allows for the transistor structures 109 to be formed in a smaller area, which allows for more devices to be formed in a given area. Using the high-k dielectric materials 145 in the decoupling capacitors 147, which have high k-values (e.g., k-values greater than about 7.0) increases the amount of charge the decoupling capacitors 147 can hold, while allowing the size of the decoupling capacitors 147 to be minimized.
FIGS. 36A-36C illustrate cross-sectional views of the nano-FET device 180 after the backside interconnect structure 136, the passivation layer 144, the UBM structures 146, and the external connectors 148 are formed. For simplicity, the MIM capacitors 147 in FIGS. 36A-36C are illustrated in a simplified version as comprising two barrier layers and a high-k dielectric material in between, with the understanding that details of the MIM capacitors are illustrated in, e.g., FIG. 35A, 35B, or 43. In some embodiments, multiple (e.g., identical) nano-FET devices 180 are formed on the carrier substrate 150, and a dicing process is performed next to singulate the multiple nano-FET devices into individual (e.g., separate) nano-FET devices. For ease of discussion, the portion of the naon-FET device 180 disposed between the front-side interconnect structure 120 and the backside interconnect structure 136 is referred to as a device layer 160.
FIGS. 37-43 illustrate another embodiment for forming the backside interconnect structure 136. To avid cluttering and to show details of the backside interconnect structure 136, FIGS. 37-43 illustrate the backside interconnect structure 136 without showing other portions of the semiconductor device (e.g., portions below the third dielectric layer 132 in FIGS. 27A-27D).
In FIG. 37, the etch stop layers 141A/141B and the fourth dielectric layer 138A/138B are formed on the third dielectric layer 132. Vias 139A are formed in the fourth dielectric layer 138A, and conductive lines 140A are formed in the fourth dielectric layer 138B. The processing is the same as or similar to that in FIG. 29, thus not repeated here. Notably, in the embodiment of FIGS. 37-43, the optional barrier layer 151 is formed for each of the vias 139 and the conductive lines 140 and 134. A pitch D1 between adjacent conductive lines 140 has a value of, e.g., 80 nm.
Next, in FIG. 38, portions of the fourth dielectric layer 138B in the region 142 of the fourth dielectric layer 138B are removed to form openings 149. Sidewalls of the conductive lines 140A in the openings 149 are exposed. A suitable etching process, such as an anisotropic etching process, may be performed using a mask layer to remove the portions of the fourth dielectric layer 138B.
Next, in FIG. 39, the high-k dielectric material 145 is formed (e.g., conformally) in the openings 149 and over the upper surface of the fourth dielectric layer 138B. The high-k dielectric material 145 lines the exposed sidewalls and the upper surfaces of the conductive lines 140A.
Next, in FIG. 40, an anisotropic etching process is performed to remove portions the high-k dielectric material 145 from the upper surface of the fourth dielectric layer 138B and from the bottoms of the openings 149. The anisotropic etching process also removes portions of the etch stop layer 141B from the bottoms of the openings 149, in some embodiments. Remaining portions of the high-k dielectric material 145 line (e.g., cover) the sidewalls of the conductive lines 140 exposed by the openings 149. Due to the anisotropicity of the anisotropic etching process, portions of the etch stop layer 141B underlying the remaining portions of the high-k dielectric material 145 also remain in the device.
Next, in FIG. 41, a barrier material 151′ is formed (e.g., conformally) on the upper surface of the fourth dielectric layer 138B and to line the sidewalls and the bottoms of the openings 149. In some embodiments, the barrier material 151′ is the same material used to form the optional barrier layer 151, such as titanium nitride, tantalum nitride, titanium, tantalum, or the like. Next, a conductive material 153 is formed in the openings 149 on the barrier material 151′. The conductive material 153 may be the same material used to form the conductive lines 140, such as copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like, and may be formed using, for example, CVD, ALD, PVD, plating or the like.
Next, in FIG. 42, a planarization process, such as CMP, is performed to remove excess portions of the barrier material 151′ and excess portions of the conductive material 153 from the upper surfaces of the fourth dielectric layer 138B. The remaining portions of the conductive material 153 and the remaining portions of the barrier material 151′ in the openings 149 form new conductive lines 140A. The remaining portions of the barrier material 151′ are referred to as the barrier layers 151 of the newly formed conductive lines 140A. After the planarization process, a coplanar upper surface is achieved between the fourth dielectric layer 138B, the conductive lines 140A, the barrier layers 151, and the high-k dielectric material 145.
As illustrated in FIG. 42, due to the newly formed conductive lines 140A being formed between existing conductive lines 140A in the region 142, the pitch D2 between the conductive lines 140A in the region 142 is half of the pitch D1 in FIG. 37. Note that the pitch between adjacent conductive lines 140A outside the region 142, or between a conductive line 140 at the border of the region 142 and an adjacent conductive line 140 outside the region 142, still has the same value as the pitch D1.
In FIG. 42, a plurality of MIM capacitors 147 are formed in the region 142. Each of the MIM capacitors 147 include a portion of the barrier layer 151 (labeled as 151A) along a first sidewall of a first conductive line 140A, a portion of the barrier layer 151 (labeled as 151B) along a second sidewall of a second conductive line 140A adjacent to the first conductive line 140A, and a portion of the high-k dielectric material 145 disposed in between. Due to the smaller pitch D2 between adjacent conductive lines 140A in the region 142, the capacitance density may be increased (e.g., doubled) compared with the embodiment of FIGS. 28-35B. An aspect ratio of the conductive line 140A may be about 2 or about 4, as an example. An aspect ratio of the high-k dielectric material 145 may be larger than 10, as an example.
Next, in FIG. 43, additional layers of the etch stop layers 141 (e.g., 141C, 141D, 141E, and 141F) and additional layers of the fourth dielectric layers 138 (e.g., 138C, 138D, 138E, and 138F) are formed over the fourth dielectric layer 138B. Additional layers of the vias 139 (e.g., 139B and 139C) and additional layers of the conductive lines 140 (e.g., 140B and 140C) are formed in alternating layers of the fourth dielectric layers 138, as illustrated in FIG. 43. Next, the etch stop layer 141G, the passivation layer 144, the under bump metallization (UBM) structures 146, and the external connectors 148 are formed over the backside interconnect structure 136.
FIGS. 44 and 45 illustrate cross-sectional views of a semiconductor package 200 at various stages of manufacturing, in an embodiment. For simplicity, a simplified cross-sectional view of the nano-FET device 180 is used in FIGS. 44 and 45, where details of the front-side interconnect structure 120, the device layer 160, and the backside interconnect structure 136 are omitted. Therefore, the front-side interconnect structure 120, the device layer 160, and the backside interconnect structure 136 of the nano-FET device 180 are simply shown as rectangular shaped boxes.
In FIG. 44, the nano-FET device 180 (see, e.g., FIGS. 36A-36C) is attached to an interposer 170. The interposer 170 includes a substrate 171 (e.g., a glass substrate, a ceramic substrate, a polymer substrate, or the like), a redistribution structure (RDS) 173 on a first side of the substrate 171, external connectors 175 on a second side of the substrate 171, and conductive paths 172 (e.g., through substrate vias (TSVs)) in the substrate 171 and electrically coupling the RDS 173 with the external connectors 175. The RDS 173 includes a plurality of dielectric layers and conductive features (e.g., vias and conductive lines) formed in the plurality of dielectric layers. The external connectors 148 of the nano-FET device 180 are coupled to (e.g., bonded to) conductive pads at the upper surface of the RDS 173, in an embodiment.
Next, in FIG. 45, the external connectors 175 of the interposer 170 are bonded to conductive pads on an upper surface of a substrate 177. The substrate 177 may be, e.g., a printed circuit board (PCB). A lid 183 is bonded to the carrier substrate 150 using a thermal interface material (TIM) 181. A heat sink 185 is attached to an upper surface of the lid 183 for dissipation of heat generated by the nano-FET device 180 during operation. In some embodiments, the high-k dielectric material used in forming the MIM capacitors 147 advantageously increases the efficiency of heat transfer from the backside interconnect structure 136 toward the heat sink 185.
Embodiments may achieve advantages. For example, including the MIM capacitors 147 in the backside interconnect structures 136 stabilizes the power supply voltage VDD and the power supply voltage VSS, which improves device performance. The MIM capacitors 147 are much closer to the nano-FETs formed and have better electrical resistance for the electrodes (e.g., the barrier layers). Moreover, including the MIM capacitors 147, the power supply voltage VDD and/or the power supply voltage VSS in the backside interconnect structure 136 allows for more devices to be formed in a smaller area, thus increasing device integration density. Using the high-k dielectric materials 145 in the MIM capacitors 147 allows for smaller MIM capacitors 147 to be formed, while increasing the amount of charge the MIM capacitors 147 can hold. The high-k dielectric material 145 also increases heat dissipation efficiency. Conventional methods for forming embedded MIM capacitors need extra processing steps, which increases production cost and may cause stress and device failure at chip edge, the disclosed methods herein can be easily integrated into exiting BEOL processing with no negative impact on the chip integrity.
FIG. 46 illustrates a flow chart of a method 1000 of forming a semiconductor device, in accordance with some embodiments. It should be understood that the embodiment method shown in FIG. 46 is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as illustrated in FIG. 46 may be added, removed, replaced, rearranged, or repeated.
Referring to FIG. 46, at block 1010, a device layer that comprises nanostructures and a gate structure around the nanostructures is formed. At block 1020, a first interconnect structure is formed on a front-side of the device layer. At block 1030, a second interconnect structure is formed on a backside of the device layer opposing the front-side of the device layer, comprising: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer by removing portions of the dielectric layer disposed between the first conductive feature and the second conductive feature; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature facing the second conductive feature and along a second sidewall of the second conductive feature facing the first conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.
In accordance with an embodiment, a method of forming a semiconductor device includes: forming a device layer that comprises nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer opposing the front-side of the device layer, comprising: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer by removing portions of the dielectric layer disposed between the first conductive feature and the second conductive feature; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature facing the second conductive feature and along a second sidewall of the second conductive feature facing the first conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer. In an embodiment, a first dielectric constant of the first dielectric material is lower than a second dielectric constant of the second dielectric material. In an embodiment, the first dielectric material is a low-K dielectric material, and the second dielectric material is a high-K dielectric material. In an embodiment, forming the opening is performed before forming the first barrier layer and the second barrier layer, wherein after removing the portions of the dielectric layer to form the opening, the opening exposes the first sidewall of the first conductive feature and exposes the second sidewall of the second conductive feature. In an embodiment, forming the first barrier layer and the second barrier layer comprises: lining sidewalls and a bottom of the opening with a barrier material; and after the lining, removing the barrier material from the bottom of the opening, wherein a first remaining portion of the barrier material along the first sidewall of the first conductive feature forms the first barrier layer, and a second remaining portion of the barrier material along the second sidewall of the second conductive feature forms the second barrier layer. In an embodiment, removing the barrier material comprises performing an anisotropic etching process to remove the barrier material from the bottom of the opening. In an embodiment, forming the second dielectric material comprises, after forming the first barrier layer and the second barrier layer, filling the opening with the second dielectric material, wherein after the filling, the second dielectric material extends continuously from the first barrier layer to the second barrier layer. In an embodiment, forming the opening is performed after forming the first barrier layer and the second barrier layer, wherein after removing the portions of the dielectric layer to form the opening, the opening exposes the first barrier layer disposed along the first sidewall of the first conductive feature and exposes the second barrier layer disposed along the second sidewall of the second conductive feature. In an embodiment, forming the second dielectric material comprises: lining sidewalls and a bottom of the opening with the second dielectric material, wherein a first portion of the second dielectric material extends along the first barrier layer, a second portion of the second dielectric material extends along the second barrier layer, and a third portion of the second dielectric material extends along the bottom of the opening; and after lining the sidewalls and the bottom of the opening with the second dielectric material, removing the third portion of the second dielectric material from the bottom of the opening. In an embodiment, the method further comprises, after removing the third portion of the second dielectric material: lining the sidewalls and the bottom of the opening with a barrier material; and after lining the sidewalls and the bottom of the opening with the barrier material, filling the opening with an electrically conductive material. In an embodiment, the method further comprises, after filling the opening: removing the barrier material from a first surface of the dielectric layer distal from the device layer, wherein after removing the barrier material, a remaining portion of the electrically conductive material in the opening forms a third conductive feature, wherein remaining portions of the barrier material extend along sidewalls of the third conductive feature and a bottom of the third conductive feature.
In accordance with an embodiment, a method of forming a semiconductor device includes: forming a device layer that comprises nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a first side of the device layer; and forming a second interconnect structure on a second side of the device layer opposing the first side of the device layer, comprising: forming a dielectric layer along the second side of the device layer using a first dielectric material; forming a first conductive feature in the dielectric layer and surrounded by a first barrier layer; forming a second conductive feature in the dielectric layer and surrounded by a second barrier layer; removing portions of the dielectric layer disposed between the first conductive feature and the second conductive feature to form an opening in the dielectric layer, the opening exposing a first sidewall of the first barrier layer and a second sidewall of the second barrier layer; forming a second dielectric material different from the first dielectric material along the first sidewall of the first barrier layer and along the second sidewall of the second barrier layer; after forming the second dielectric material, lining sidewalls and a bottom of the opening with a third barrier layer; and after forming the third barrier layer, filling the opening with an electrically conductive material. In an embodiment, the first dielectric material has a lower dielectric constant than the second dielectric material. In an embodiment, the first dielectric material is a low-K dielectric material, and the second dielectric material is a high-K dielectric material. In an embodiment, the first barrier layer, the second barrier layer, and the third barrier layer are formed of a same material. In an embodiment, the first conductive feature and the second conductive feature are conductive lines. In an embodiment, the first conductive feature and the second conductive feature are vias.
In accordance with an embodiment, a semiconductor device includes: a device layer comprising nanostructures and a gate structure around the nanostructures; a first interconnect structure on a first side of the device layer; and a second interconnect structure on a second side of the device layer opposing the first side of the device layer, comprising: a dielectric layer along the second side of the device layer, wherein the dielectric layer comprises a first dielectric material; a first conductive feature and a second conductive feature that are embedded in the dielectric layer; and a metal-insulator-metal (MIM) capacitor in the dielectric layer, comprising: a first barrier layer along a first sidewall of the first conductive feature facing the second conductive feature; a second barrier layer along a second sidewall of the second conductive feature facing the first conductive feature; and a second dielectric material in the dielectric layer between the first barrier layer and the second barrier layer, wherein the second dielectric material is different from the first dielectric material. In an embodiment, the second dielectric material has a higher dielectric constant than the first dielectric material. In an embodiment, the second dielectric material extends continuously from the first barrier layer to the second barrier layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Patent Application
20250142901
