Various semiconductor device packing techniques may be used to incorporate one or more semiconductor dies into a semiconductor device package. In some cases, semiconductor dies may be stacked in a semiconductor device package to achieve a smaller horizontal or lateral footprint of the semiconductor device package and/or to increase the density of the semiconductor device package. Semiconductor device packing techniques that may be performed to integrate a plurality of semiconductor dies in a semiconductor device package may include integrated fanout (InFO), package on package (PoP), chip on wafer (CoW), wafer on wafer (WoW), and/or chip on wafer on substrate (CoWoS), among other examples.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In a wafer on wafer (WoW) semiconductor die package, semiconductor dies are directly bonded such that the semiconductor dies are vertically arranged in the WoW semiconductor die package. The use of direct bonding and vertical stacking of dies may reduce interconnect lengths between the semiconductor dies (which reduces power loss and signal propagation times) and may enable increased density of semiconductor die packages in a semiconductor device package that includes the WoW semiconductor die package.
In some cases, decoupling trench capacitors may be included in one or more semiconductor dies in a WoW semiconductor die package. The decoupling trench capacitors, which may be implemented as deep trench capacitor (DTC) structures, may be included to decouple various circuits in the one or more semiconductor dies. In particular, the decoupling trench capacitors may provide noise decoupling by shunting noise (e.g., voltage spikes, voltage swings) from a circuit in the one or more semiconductor dies, thereby preventing the noise from affecting other circuits in the one or more semiconductor dies.
Decoupling trench capacitors may be formed in a semiconductor substrate in a device region of a semiconductor die included in a WoW semiconductor die package. The quantity, density, and/or depth of decoupling trench capacitors may be increased in the semiconductor substrate to increase the amount of decoupling capacitance provided for the circuits of the WoW semiconductor die package. However, increasing the quantity, density, and/or depth of the decoupling trench capacitors may result in increased physical stress in the semiconductor die, which may increase the likelihood of cracking, warpage, and/or device failures in the semiconductor die.
During fabrication of the decoupling trench capacitors, an etch process is performed to remove portions of the semiconductor substrate to form a plurality of trenches for the decoupling trench capacitors. The etch process may be performed such that the sidewalls of the trenches are substantially straight and vertical in the semiconductor substrate, and such that the trenches have a relatively high aspect ratio (e.g., a ratio of the depth to the width of the semiconductor substrate). Deposition processes are performed to form a plurality of electrodes and dielectric layers within the trenches such that the electrodes and dielectric layers completely fill each of the trenches.
However, during the fabrication process and/or during operation of the decoupling trench capacitors, the electrodes and dielectric layers are exposed to heat (e.g., due to baking process(es) and/or heat generated by high voltages and/or currents). The heat may cause the dielectric layers and/or the electrodes to undergo thermal expansion, which results in forces being applied to the sidewalls of the trenches. The deeper the trenches are, and/or the greater the density of the decoupling (and therefore the greater the density of the trenches), the more likely that these forces may cause warping, breaking, and/or cracking of the semiconductor die.
In some implementations described herein, a semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.
In this way, the performance of the circuits of the semiconductor die package may be increased while reducing the likelihood of failures in the semiconductor die package that might otherwise be caused by warping, breaking, and/or cracking of the semiconductor die package. This may reduce the likelihood of that the semiconductor die package may have to be reworked and/or scrapped, which may reduce processing times and/or increase the yield of semiconductor substrates including the decoupling trench capacitor structures described herein.
The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool 102 includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the deposition tool 102 includes an epitaxial tool that is configured to form layers and/or regions of a device by epitaxial growth. In some implementations, the example environment 100 includes a plurality of types of deposition tools 102.
The exposure tool 104 is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light (EUV) source, and/or the like), an x-ray source, an electron beam (e-beam) source, and/or the like. The exposure tool 104 may expose a photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include a pattern for forming one or more structures of a semiconductor device, may include a pattern for etching various portions of a semiconductor device, and/or the like. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.
The developer tool 106 is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some implementations, the developer tool 106 develops a pattern by removing unexposed portions of a photoresist layer. In some implementations, the developer tool 106 develops a pattern by removing exposed portions of a photoresist layer. In some implementations, the developer tool 106 develops a pattern by dissolving exposed or unexposed portions of a photoresist layer through the use of a chemical developer.
The etch tool 108 is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool 108 may include a wet etch tool, a dry etch tool, and/or the like. In some implementations, the etch tool 108 includes a chamber that is filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. In some implementations, the etch tool 108 may etch one or more portions of the substrate using a plasma etch or a plasma-assisted etch, which may involve using an ionized gas to isotropically or directionally etch the one or more portions.
The planarization tool 110 is a semiconductor processing tool that is capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, a planarization tool 110 may include a chemical mechanical planarization (CMP) tool and/or another type of planarization tool that polishes or planarizes a layer or surface of deposited or plated material. The planarization tool 110 may polish or planarize a surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool 110 may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring (e.g., typically of a greater diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.
The plating tool 112 is a semiconductor processing tool that is capable of plating a substrate (e.g., a wafer, a semiconductor device, and/or the like) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and/or the like) electroplating device, and/or an electroplating device for one or more other types of conductive materials, metals, and/or similar types of materials.
The bonding tool 114 is a semiconductor processing tool that is capable of bonding two or more work pieces (e.g., two or more semiconductor substrates, two or more semiconductor devices, two or more semiconductor dies) together. For example, the bonding tool 114 may be a direct bonding tool that is a type of bonding tool that is configured to bond semiconductor dies together directly through copper-to-copper (or other direct metal) connections. As another example, the bonding tool 114 may include a eutectic bonding tool that is capable of forming a eutectic bond between two or more wafers together. In these examples, the bonding tool 114 may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers.
Wafer/die transport tool 116 includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and/or another type of device that is configured to transport substrates and/or semiconductor devices between semiconductor processing tools 102-114, that is configured to transport substrates and/or semiconductor devices between processing chambers of the same semiconductor processing tool, and/or that is configured to transport substrates and/or semiconductor devices to and from other locations such as a wafer rack, a storage room, and/or the like. In some implementations, wafer/die transport tool 116 may be a programmed device that is configured to travel a particular path and/or may operate semi-autonomously or autonomously. In some implementations, the example environment 100 includes a plurality of wafer/die transport tools 116.
For example, the wafer/die transport tool 116 may be included in a cluster tool or another type of tool that includes a plurality of processing chambers, and may be configured to transport substrates and/or semiconductor devices between the plurality of processing chambers, to transport substrates and/or semiconductor devices between a processing chamber and a buffer area, to transport substrates and/or semiconductor devices between a processing chamber and an interface tool such as an equipment front end module (EFEM), and/or to transport substrates and/or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some implementations, a wafer/die transport tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and/or other types of contamination or byproducts from a substrate and/or semiconductor device) and a plurality of types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these implementations, the wafer/die transport tool 116 is configured to transport substrates and/or semiconductor devices between the processing chambers of the deposition tool 102 without breaking or removing a vacuum (or an at least partial vacuum) between the processing chambers and/or between processing operations in the deposition tool 102.
In some implementations, one or more of the semiconductor processing tools 102-116 and/or the wafer/die transport tool 116 may perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-114 and/or the wafer/die transport tool 116 may form a plurality of decoupling trench capacitor regions in a device region of a first semiconductor die structure, where a first plurality of decoupling trench capacitor structures, of a first decoupling trench capacitor region of the plurality of decoupling trench capacitor regions, are formed to a first depth in the device region, and where a second plurality of decoupling trench capacitor structures, of a second decoupling trench capacitor region of the plurality of decoupling trench capacitor regions, are formed to a second depth in the device region, and where the first depth and the second depth are different depths relative to a surface of the device region; may form an interconnect region over the device region after forming the plurality of decoupling trench capacitor regions; and/or may bond a first semiconductor die with a second semiconductor die at a bonding interface.
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The first semiconductor die 202 and the second semiconductor die 206 may be bonded together (e.g., directly bonded) at a bonding interface 208. In some implementations, one or more layers may be included between the first semiconductor die 202 and the second semiconductor die 206 at the bonding interface 208, such as one or more passivation layers, one or more bonding films, and/or one or more layers of another type.
The second semiconductor die 206 may include a device region 210 and an interconnect region 212 adjacent to and/or above the device region 210. In some implementations, the second semiconductor die 206 may include additional regions. Similarly, the first semiconductor die 202 may include a device region 214 and an interconnect region 216 adjacent to and/or below the device region 214. In some implementations, the first semiconductor die 202 may include additional regions. The first semiconductor die 202 and the second semiconductor die 206 may be bonded at the interconnect region 212 and the interconnect region 216. The bonding interface 208 may be located at a first side of the interconnect region 216 facing the interconnect region 212 and corresponding to a first side of the second semiconductor die 202.
The device regions 210 and 214 may each include a semiconductor substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium substrate (Ge), a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. The device region 210 of the second semiconductor die 206 may include one or more semiconductor devices 218 included in the semiconductor substrate of the device region 210. The semiconductor devices 218 may include one or more transistors (e.g., planar transistors, fin field effect transistors (FinFETs), nanosheet transistors (e.g., gate all around (GAA) transistors), memory cells, capacitors, inductors, resistors, pixel sensors, circuits (e.g., integrated circuits (ICs)), and/or another type of semiconductor devices.
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At least two or more of the respective pluralities of decoupling trench capacitor structures 220a-220c may be formed to different depths (or heights) in the device region 214 relative to a surface (e.g., the bottom surface) of the semiconductor substrate of the device region 214. For example, a depth (or height) of the decoupling trench capacitor structures 220b in the decoupling trench capacitor region 204c may be greater relative to a depth (or height) of the decoupling trench capacitor structures 220a in the decoupling trench capacitor region 204a. As another example, a depth (or height) of the decoupling trench capacitor structures 220c in the decoupling trench capacitor region 204e may be greater relative to the depth (or height) of the decoupling trench capacitor structures 220c in the decoupling trench capacitor region 204c, and may be greater relative to the depth (or height) of the decoupling trench capacitor structures 220a in the decoupling trench capacitor region 204a. In some implementations, the decoupling trench capacitor structures included in the same decoupling trench capacitor region may be formed to the same depth (or the same height). In some implementations, two or more decoupling trench capacitor structures included in the same decoupling trench capacitor region may be formed to different depths (or different heights).
The depths of the decoupling trench capacitor structures 220a-220c (and other decoupling trench capacitor structures in the decoupling trench capacitor regions 204a-204n) may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for the semiconductor devices 218 included in circuits of the semiconductor die package 200, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package 200. Some of the circuits of the semiconductor die package 200 may have greater decoupling capacitance requirements than other circuits in order to properly operate at desired performance parameters. Accordingly, deeper decoupling trench capacitor structures may be formed for these circuits relative to the depth of decoupling trench capacitor structures that are formed for other circuits that have lesser decoupling capacitance requirements. This enables a balance between satisfying capacitance requirements in the semiconductor die package 200 and reducing the likelihood of warpage in the semiconductor die package 200.
Additionally and/or alternatively, the arrangement or layout of decoupling trench capacitor structure depths (or heights) across the semiconductor die package 200 may be determined or selected based on the overall floorplan of the first semiconductor die 202 and/or the second semiconductor die 206. For example, decoupling trench capacitor structures of greater depth (or greater height) may be included at or near an edge (e.g., an outer edge or an outer perimeter) of the first semiconductor die 202 and/or the second semiconductor die 206 to reduce the likelihood of warpage in the first semiconductor die 202 and/or the second semiconductor die 206. Decoupling trench capacitor structures of lesser depth (or lesser height) may be included closer to the center of the first semiconductor die 202 and/or the second semiconductor die 206. However, other arrangements of decoupling trench capacitor structure depths (or heights) across the semiconductor die package 200 may be selected to satisfy an equivalent series resistance (ESR) parameter for the interconnection regions 212 and 216, among other performance parameters.
Various design rules and/or principals may be employed when determining the arrangement or layout of decoupling trench capacitor structure depths (or heights) across the semiconductor die package 200. In some implementations, a target decoupling trench capacitor structure depth (or height) may be selected for the semiconductor die package 200, and the depths (or heights) of the decoupling trench capacitor structures across the semiconductor die package 200 may be selected within a particular range of the target decoupling trench capacitor structure depth (or height). As an example, a target decoupling trench capacitor structure depth (or height) may be selected for the semiconductor die package 200, and the depths (or heights) of the decoupling trench capacitor structures across the semiconductor die package 200 may be selected from a range of approximately +/−15% of the target decoupling trench capacitor structure depth (or height). However, other values for the range are within the scope of the present disclosure.
In some implementations, other parameters for the decoupling trench capacitor structures of the semiconductor die package 200 may be selected in a similar manner. For example, a target decoupling trench capacitor structure width (or critical dimension) may be selected for the semiconductor die package 200, and the widths (or critical dimensions) of the decoupling trench capacitor structures across the semiconductor die package 200 may be selected from a range of approximately +/−30% of the target decoupling trench capacitor structure depth (or height). However, other values for the range are within the scope of the present disclosure.
As another example, a target decoupling trench capacitor structure aspect ratio (e.g., a ratio of the height to the width) may be selected for the semiconductor die package 200, and the aspect ratios of the decoupling trench capacitor structures across the semiconductor die package 200 may be selected from a range of approximately +/−12% of the target decoupling trench capacitor structure depth (or height). However, other values for the range are within the scope of the present disclosure.
The interconnect regions 212 and 216 may be referred to as back end of line (BEOL) regions. The interconnect region 212 may include one or more dielectric layers 222, which may include a silicon nitride (SiNx), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), a low dielectric constant (low-k) dielectric material, and/or another type of dielectric material. In some implementations, one or more etch stop layers (ESLs) may be included in between layers of the one or more dielectric layers 222. The one or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and/or a silicon oxide (SiOx), among other examples.
The interconnect region 212 may further include metallization layers 224 in the one or more dielectric layers 222. The semiconductor devices 218 in the device region 210 may be electrically connected and/or physically connected with one or more of the metallization layers 224. The metallization layers 224 may include conductive lines, trenches, vias, pillars, interconnects, and/or another type of metallization layers. Contacts 226 may be included in the one or more dielectric layers 222 of the interconnect region 212. The contacts 226 may be electrically connected and/or physically connected with one or more of the metallization layers 224. The contacts 226 may include conductive terminals, conductive pads, conductive pillars, under bump metallization (UBM) structures, and/or another type of contacts. The metallization layers 224 and the contacts 226 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and/or another type of conductive materials.
The interconnect region 216 may include one or more dielectric layers 228, which may include a silicon nitride (SiNx), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), a low dielectric constant (low-k) dielectric material, and/or another type of dielectric material. In some implementations, one or more etch stop layers (ESLs) may be included in between layers of the one or more dielectric layers 228. The one or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and/or a silicon oxide (SiOx), among other examples.
The interconnect region 216 may further include metallization layers 230 in the one or more dielectric layers 228. The decoupling trench capacitor structures 220a-220c in the device region 214 may be electrically connected and/or physically connected with one or more of the metallization layers 230. The metallization layers 230 may include conductive lines, trenches, vias, pillars, interconnects, and/or another type of metallization layers. Contacts 232 may be included in the one or more dielectric layers 228 of the interconnect region 216. The contacts 232 may be electrically connected and/or physically connected with one or more of the metallization layers 230. Moreover, the contacts 232 may be electrically and/or physically connected with the contacts 226 of the second semiconductor die 206. The contacts 232 may include conductive terminals, conductive pads, conductive pillars, UBM structures, and/or another type of contacts. The metallization layers 230 and the contacts 232 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and/or another type of conductive materials.
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The redistribution structure 234 may include one or more dielectric layers 236 and a plurality of metallization layers 238 disposed in the one or more dielectric layers 236. The dielectric layer(s) 236 may include polybenzoxazole (PBO), a polyimide, a low temperature polyimide (LTPI), an epoxy resin, an acrylic reason, a phenol resin, benzocyclobutene (BCB), one or more dielectric layers, and/or another suitable dielectric material.
The metallization layers 238 of the redistribution structure 234 may include one or more materials such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, and/or a palladium (Pd) material, among other examples. The metallization layers 238 of the redistribution structure 234 may include metal lines, vias, interconnects, and/or another type of metallization layers.
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UBM layers 242 may be included on a top surface of the one or more dielectric layers 236. The UBM layers 242 may be electrically connected and/or physically connected with one or more metallization layers 238 in the redistribution structure 234. The UBM layers 242 may be included in recesses in the top surface of the one or more dielectric layers 236. The UBM layers 242 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and/or another type of conductive materials.
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The depth (D2) of the decoupling trench capacitor structures 220b in the decoupling trench capacitor region 204c may be greater relative to the depth (D1) of the decoupling trench capacitor structures 220a in the decoupling trench capacitor region 204a. The depth (D3) of the decoupling trench capacitor structures 220c in the decoupling trench capacitor region 204e may be greater relative to the depth (D2) of the decoupling trench capacitor structures 220b in the decoupling trench capacitor region 204c, and may be greater relative to the depth (D1) of the decoupling trench capacitor structures 220a in the decoupling trench capacitor region 204a.
In some implementations, the depth (D2) (corresponding to the height of the decoupling trench capacitor structures 220b) may be selected as the target depth for the semiconductor die package 200. In these implementations, the depth (D1) (corresponding to the height of the decoupling trench capacitor structures 220a) and the depth (D3) (corresponding to the height of the decoupling trench capacitor structures 220c) may be selected to be within a range of approximately 15% less than the depth (D2) to approximately 15% greater than the depth (D2). However, other values for the range are within the scope of the present disclosure.
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The ESD protection circuit 312 may include one or more semiconductor diodes and/or another type of semiconductor devices that are configured to provide the one or more semiconductor devices 218 with ESD protection (e.g., protection against electrical shots, protection against electrostatic buildup). One or more regions of the semiconductor substrate of the device region 210 may be doped to form an n-well 314. N-type contacts 316 and p-type contacts 318 of the one or more diodes of the ESD protection circuit 312 may be included in the n-well 314.
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The decoupling trench capacitor structure 220 may include a plurality of conductive layers 402 and a plurality of dielectric layers 404. The conductive layers 402 and the dielectric layers 404 may be arranged in an alternating configuration in the decoupling trench capacitor structure 220. For example, a first conductive layer 402 may be included in the decoupling trench capacitor structure 220, a first dielectric layer 404 may be included over the first conductive layer 402, a second conductive layer 402 may be included over the first dielectric layer 404, and so on. A dielectric layer 404 between a pair of conductive layers 402 may correspond to a trench capacitor of the decoupling trench capacitor structure 220, where the conductive layers 402 correspond to the electrodes of the trench capacitor and the dielectric layer 404 corresponds to the dielectric medium of the trench capacitor. In this way, the decoupling trench capacitor structure 220 includes a plurality of layered trench capacitors that extend into the semiconductor substrate of the device region 214.
In general, a deeper decoupling trench capacitor structure 220 may provide a greater amount of decoupling capacitance relative to a shallower deeper decoupling trench capacitor structure 220. Additionally and/or alternatively, a wider deeper decoupling trench capacitor structure 220 may include a greater quantity of conductive layers 402 and a greater quantity of dielectric layers 404 and, therefore, a greater quantity of decoupling trench capacitors relative to a narrower deeper decoupling trench capacitor structure 220. This enables a wider deeper decoupling trench capacitor structure 220 to also provide a greater amount of decoupling capacitance relative to a narrower deeper decoupling trench capacitor structure 220.
The conductive layers 402 may include one or more conductive materials such as a conductive metal (e.g., copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co)), a conductive ceramic (e.g., tantalum nitride (TaN), titanium nitride (TiN)), and/or another type of conductive material. The dielectric layers 404 may include one or more dielectric materials such as an oxide (e.g., silicon oxide (SiOx)), a nitride (e.g., silicon nitride (SixNy), and/or another suitable dielectric material.
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As an example of the above, one or more of the semiconductor processing tools 102-114 may perform photolithography patterning operations, etching operations, deposition operations, CMP operations, and/or another type of operations to form a plurality of decoupling trench capacitor structures 220a in a decoupling trench capacitor region 204a of the device region 214, a plurality of decoupling trench capacitor structures 220b in a decoupling trench capacitor region 204c of the device region 214, and a plurality of decoupling trench capacitor structures 220c in a decoupling trench capacitor region 204e of the device region 214. In some implementations, a depth (or height) of the decoupling trench capacitor structures 220b in the decoupling trench capacitor region 204c is greater relative to a depth (or height) of the decoupling trench capacitor structures 220a in the decoupling trench capacitor region 204a. In some implementations, a depth (or height) of the decoupling trench capacitor structures 220c in the decoupling trench capacitor region 204e is greater relative to the depth (or height) of the decoupling trench capacitor structures 220c in the decoupling trench capacitor region 204c, and is greater relative to the depth (or height) of the decoupling trench capacitor structures 220a in the decoupling trench capacitor region 204a.
To form a decoupling trench capacitor structure, a recess may be formed in the semiconductor substrate (e.g., from the surface 246) of the device region 214 using a pattern in a photoresist layer, a hard mask, and/or another type of masking layer. For example, the deposition tool 102 forms a photoresist layer over the semiconductor substrate of the device region 214. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the semiconductor substrate of the device region 214 to form the recess. The deposition tool 102 may perform a deposition operation (e.g., a CVD operation, a PVD operation, an ALD operation) to deposit a first conductive layer 402 in the recess such that the first conductive layer 402 conforms to the shape of the recess. The deposition tool 102 may perform a deposition operation (e.g., a CVD operation, a PVD operation, an ALD operation) to deposit a first dielectric layer 404 on the first conductive layer 402. The deposition tool 102 may perform a deposition operation (e.g., a CVD operation, a PVD operation, an ALD operation) to deposit a second conductive layer 402 on the first dielectric layer 404. The deposition tool 102 may perform a deposition operation (e.g., a CVD operation, a PVD operation, an ALD operation) to deposit a second dielectric layer 404 on the second conductive layer 402. The deposition tool 102 may perform subsequent deposition operations until a sufficient or desired quantity of deep trench capacitors are formed in the recess for the deep trench capacitor structure.
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The decoupling trench capacitor structures 220a in the decoupling trench capacitor region 204a may be electrically connected and/or physically connected with one or more of the metallization layers 230. The decoupling trench capacitor structures 220b in the decoupling trench capacitor region 204c may be electrically connected and/or physically connected with one or more of the metallization layers 230. The decoupling trench capacitor structures 220c in the decoupling trench capacitor region 204e may be electrically connected and/or physically connected with one or more of the metallization layers 230.
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In some implementations, a pattern in a photoresist layer is used to form the one or more recesses 902. In these implementations, the deposition tool 102 forms the photoresist layer over the silicon substrate of the device region 214. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches through the semiconductor substrate of the device region 214 and into a portion of the dielectric layer 228 of the interconnect region 216 to form the one or more recesses 902. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the one or more recesses 902 based on a pattern.
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The deposition tool 102 and/or the plating tool 112 may deposit the one or more BTSV structures 240 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form the recesses 902. In these implementations, the deposition tool 102 forms the photoresist layer on the one or more dielectric layers 236. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the one or more dielectric layers 236 to form the recesses 902. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recesses 904 based on a pattern.
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The bus 1010 may include one or more components that enable wired and/or wireless communication among the components of the device 1000. The bus 1010 may couple together two or more components of
The memory 1030 may include volatile and/or nonvolatile memory. For example, the memory 1030 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). The memory 1030 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). The memory 1030 may be a non-transitory computer-readable medium. The memory 1030 may store information, one or more instructions, and/or software (e.g., one or more software applications) related to the operation of the device 1000. In some implementations, the memory 1030 may include one or more memories that are coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1020), such as via the bus 1010. Communicative coupling between a processor 1020 and a memory 1030 may enable the processor 1020 to read and/or process information stored in the memory 1030 and/or to store information in the memory 1030.
The input component 1040 may enable the device 1000 to receive input, such as user input and/or sensed input. For example, the input component 1040 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and/or an actuator. The output component 1050 may enable the device 1000 to provide output, such as via a display, a speaker, and/or a light-emitting diode. The communication component 1060 may enable the device 1000 to communicate with other devices via a wired connection and/or a wireless connection. For example, the communication component 1060 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.
The device 1000 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1030) may store a set of instructions (e.g., one or more instructions or code) for execution by the processor 1020. The processor 1020 may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors 1020, causes the one or more processors 1020 and/or the device 1000 to perform one or more operations or processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, the processor 1020 may be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.
The number and arrangement of components shown in
As shown in
As further shown in
As further shown in
Process 1100 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.
In a first implementation, bonding the first semiconductor die 202 and the second semiconductor die 206 includes performing a bonding operation to bond the first semiconductor die 202 and the second semiconductor die 206.
In a second implementation, alone or in combination with the first implementation, process 1100 includes forming a plurality of semiconductor devices 218 in another device region 210 of the second semiconductor die 206, and forming another interconnect region 212 over the other device region 210, where the first plurality of decoupling trench capacitor structures 220a and the second plurality of decoupling trench capacitor structures 220b are configured to provide a decoupling capacitance for the plurality of semiconductor devices 218 of the second semiconductor die 206.
In a third implementation, alone or in combination with one or more of the first and second implementations, process 1100 includes forming a first portion 302b of a seal ring structure 302 in the first semiconductor die 202, and forming a second portion 302a of the seal ring structure 302 in the second semiconductor die, where the first portion 302b of the seal ring structure 302 and the second portion 302a of the seal ring structure 302 are joined at the bonding interface 208 when the first semiconductor die 202 and the second semiconductor die 204 are bonded.
In a fourth implementation, alone or in combination with one or more of the first through third implementations, forming the first portion 302b of the seal ring structure 302 includes forming a portion 304b of an inner seal ring structure 304 of the seal ring structure 302 in the first semiconductor die 202, and forming a portion 306b of an outer seal ring structure 306 of the seal ring structure 302 in the first semiconductor die 202.
In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process 1100 includes forming, in the interconnect region 216, a metallization layer 308 that electrically connects the first portion 302b of the seal ring structure 302 with a third plurality of decoupling trench capacitor structures 220 in a third decoupling trench capacitor region 204b of the plurality of decoupling trench capacitor regions 204a-204n.
In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, process 1100 includes forming an ESD protection circuit 312 in the second semiconductor die 206, where the ESD protection circuit 312 is electrically connected with the second portion 302a of the seal ring structure 302.
Although
In this way, a semiconductor die included in a semiconductor die package may include a plurality of decoupling trench capacitor regions in a device region of the semiconductor die. At least two or more of the decoupling trench capacitor regions include decoupling trench capacitor structures having different depths. The depths of the decoupling trench capacitor structures in the decoupling trench capacitor regions may be selected to provide sufficient capacitance so as to satisfy circuit decoupling parameters for circuits of the semiconductor die package, while reducing the likelihood of warping, breaking, and/or cracking of the semiconductor die package.
As described in greater detail above, some implementations described herein provide a semiconductor die package. The semiconductor die package includes a first semiconductor die. The first semiconductor die includes a first device region that includes a first decoupling trench capacitor region including a first decoupling trench capacitor structure and a second decoupling trench capacitor region including a second decoupling trench capacitor structure, where a first height of the first decoupling trench capacitor structure in the first decoupling capacitor region, and a second height of a second decoupling trench capacitor structures in the second decoupling capacitor region, are different heights. The first semiconductor die includes a first interconnect region vertically adjacent to the first device region at a first side of the first interconnect region and including a plurality of metallization layers that are electrically connected with the first and second decoupling trench capacitor structures. The semiconductor die package includes a second semiconductor die, bonded with the first semiconductor die at a second side of the first interconnect region opposing the first side. The second semiconductor die includes a second device region including one or more semiconductor devices and a second interconnect region vertically adjacent to the second device region.
As described in greater detail above, some implementations described herein provide a method. The method includes forming a plurality of decoupling trench capacitor regions in a device region of a first semiconductor die. A first plurality of decoupling trench capacitor structures, of a first decoupling trench capacitor region of the plurality of decoupling trench capacitor regions, are formed to a first depth in the device region. A second plurality of decoupling trench capacitor structures, of a second decoupling trench capacitor region of the plurality of decoupling trench capacitor regions, are formed to a second depth in the device region. The first depth and the second depth are different depths relative to a surface of the device region. The method includes forming an interconnect region over the device region after forming the plurality of decoupling trench capacitor regions. The method includes bonding the first semiconductor die with a second semiconductor die at a bonding interface.
As described in greater detail above, some implementations described herein provide a semiconductor die package. The semiconductor die package includes a first semiconductor die. The first semiconductor die includes a first device region that includes a first decoupling trench capacitor region including a first decoupling trench capacitor structure and a second decoupling trench capacitor region including a second decoupling trench capacitor structure. The first semiconductor die includes a first interconnect region vertically adjacent to the first device region at a first side of the first interconnect region. The semiconductor die package includes a second semiconductor die, bonded with the first semiconductor die at a second side of the first interconnect region opposing the first side. The second semiconductor die includes a second device region that includes one or more semiconductor devices and an ESD protection circuit. The second semiconductor die includes a second interconnect region vertically adjacent to the second device region. The semiconductor die package includes a seal ring structure that extends through the first interconnect region and the second interconnect region, where the seal ring structure electrically connects the ESD protection circuit with the first and second decoupling trench capacitor structures.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This Patent application claims priority to U.S. Provisional Patent Application No. 63/377,648, filed on Sep. 29, 2022, and entitled “SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION.” The disclosure of the prior Application is considered part of and is incorporated by reference into this Patent Application.
Number | Date | Country | |
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63377648 | Sep 2022 | US |