Patent Application
20150249135
Embodiments of the present invention relate to semiconductor heterostructures for electronic and optoelectronic devices. Embodiments of the present invention particularly relate to III-V-antimonide-heterostructures, and specifically to a III-V-compound semiconductor heterostructure.
The demand for electronic devices and optoelectronic devices for the infrared range can be met by semiconductor heterostructures based on group-III antimonides. From III-V compound semiconductor materials, antimonides offer a comparable small band gap, from 1.65 eV of AlAsSb down to 0.2 eV of InSb. Therefore, devices based on III-V-antimonide-heterostructures are well-suited as emitters for optical data transmission, solar energy harvesting, gas sensing applications, medical applications, plastic welding, etc.
For the fabrication of high-quality electronic and optoelectronic semiconductor devices, a precise control of the electronic band structure is desired. Accordingly, heterostructures with tailored compositional transitions are desired. In particular, layer quality after growth and the potential impact of high temperature processing steps on the layer quality have to be controlled and known. One aspect to be considered is interdiffusion resulting in a degradation of steep concentration profiles.
For example, semiconductor lasers operating in the 2-5 micrometer range and providing a high output power are a common desire. Such a semiconductor laser can be constructed of a stack of layers, typically III-V-semiconductors, formed on a binary substrate, such as GaSb, GaAs, InP, Si, InSb, InAs, GaP, or Ge. Some applications have employed semiconductor lasers with binary or/and ternary compounds for the waveguide and active region, while other applications use quaternary compounds or even quinternary compounds. For example mixed group-V quaternary alloys can be GaInAsSb, AlGaAsSb, and AlInAsSb, whereas AlGaInAsSb can be a quinternary alloy.
Particularly for high performance electronic and optoelectronic devices with band structures, which are complex and/or difficult to grow, as well as doping levels, which are complex and/or difficult to manufacture, interdiffusion or intermixing of materials in binary, ternary, quaternary and quinternary systems need to be considered and controlled.
Typically, heterostructures in binary, ternary, quaternary and quinternary system are grown under group-V-rich conditions, because group-III-rich conditions have been experiences to be disadvantageous due to droplet formation and the like. Further, there have been attempts to generate group-III-rich surfaces from group-V-rich surfaces, e.g. by heating in order to achieve a group-III-rich surface reconstruction of a semiconductor layer. This is for example described in patent application publication US 2009/0085073.
In view of the above, it is an object of the present invention to provide an improved semiconductor structure and improved methods of manufacturing thereof that overcome at least some of the problems in the art.
In light of the above, a III-V compound semiconductor heterostructure grown on a substrate according to independent claim 1 is provided. Further aspects, advantages, and features of the present invention are apparent from the dependent claims, the description, and the accompanying drawings.
According to one embodiment, a III-V compound semiconductor heterostructure grown on a substrate is provided. The heterostructure includes a first semiconductor layer, wherein the first layer semiconductor layer is a compound semiconductor layer with (III)1(V)1, wherein (III) represents one or more group-III elements and (V) represents one or more group-V elements, an intermediate layer on the first semiconductor layer, wherein the intermediate layer is a compound semiconductor layer with (III)x>1(V)2-x, and wherein the intermediate layer has a thickness of 10 monolayers or below, and a second semiconductor layer, wherein the first layer semiconductor layer is a compound semiconductor layer with (III)1(V)1.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments. The accompanying drawings relate to embodiments of the invention and are described in the following:
Reference will now be made in detail to the various embodiments of the invention, one or more examples of which are illustrated in the figures. Within the following description of the drawings, the same reference numbers refer to same components. Generally, only the differences with respect to individual embodiments are described. Each example is provided by way of explanation of the invention and is not meant as a limitation of the invention. Further, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the description includes such modifications and variations.
Embodiments described herein refer to heterostructures. Accordingly, parts of e.g. a light emitting structure, such as a laser, a LED, a SLED, etc., are provided, wherein the heterostructures and devices include a compound semiconductor layer-stack. Typically, the formation of a heterostructure includes forming compound semiconductor layers (III)1(V)1, wherein (III) represents one or more group-III elements and (V) represents one or more group-V elements. According to typical embodiments, which can be combined with other embodiments described herein, such compound semiconductors can be described as (A)1(D)1, wherein A is selected from the group consisting of Al, Ga, and In, and D is selected from the group selected from the group consisting of As and Sb. Such compound semiconductors can further be described as (AB)1(D)1, wherein A and B are selected from the group consisting of Al, Ga, and In, and D is selected from the group selected from the group consisting of As and Sb, or (A)1(DE)1, wherein A is selected from the group consisting of Al, Ga, and In, and D and E are selected from the group selected from the group consisting of As and Sb; thereby, a ternary compound semiconductor is formed. Even further, such compound semiconductors can be described as (AB)1(DE)1, wherein A and B are selected from the group consisting of Al, Ga, and In, and D and E are selected from the group selected from the group consisting of As and Sb, or (ABC)1(D)1, wherein AB and C are selected from the group consisting of Al, Ga, and In, and D is selected from the group selected from the group consisting of As and Sb; thereby, a quaternary compound semiconductor is formed. Even further, such compound semiconductors can be described as (ABC)1(DE)1, wherein A, B and C are selected from the group consisting of Al, Ga, and In, and D and E are selected from the group selected from the group consisting of As and Sb; thereby, a quinternary compound semiconductor is formed. For the above compounds, the numeral “1” behind the brackets, i.e. ( . . . )1 indicate that the one or more group-III elements and the one or more group-V elements are provided in the compound semiconductor under stoichiometric conditions, such that a crystal structure is grown, which could in theory be defect free.
Even though the (III)1(V)1 compound semiconductor layers are grown to be stoichiometric, they are typically grown under a group-V rich condition, i.e. the availability of group-V element atoms at the growth surface exceeds the availability of group-III element atoms. This usually results in a stable growth condition. Contrary thereto, an overplus of group-III element atoms might result in droplet formation and other defects to be incorporated in the semiconductor layer.
According to different embodiments, which can be combined with other embodiments described herein, the compound semiconductor layers (III)1(V)1, wherein (III) represents one or more group-III elements and (V) represents one or more group-V elements, can typically be grown on substrates selected from the group consisting of GaSb, GaAs, InP, Si, InSb, InAs, GaP, and Ge. Typically, substrate choice is determined by availability, lattice matching, costs or the like.
According to embodiments described herein, the intermediate layer is provided to have an understoichiometric property (III)x>1(V)x<1 or (III)x>1(V)2-x, i.e. a group-V understochiometric property. According to typical embodiments, which can be combined with other embodiments described herein, x can be smaller than 2 and can particularly be 1.1 or smaller. Thereby, for example if x=1.1 a heterostructure with (III)1.1(V)0.9 can be provided. If x=1.05, for example a heterostructure with (III)1.05(V)0.95 is provided. According to yet further optional modifications, x can be 1.05 or smaller, 1.02 or smaller. Such heterostructures allow for elimination or minimization of Sb, surface Sb, or excess Sb on the growth surface. Sb, surface Sb, or excess Sb on the growth surface can be susceptible to being exchanged by incoming As atoms. Exchange of Sb by As results in intermixing between subsequent layers of the heterostructure, defect creation and interface degradation during the growth or post-growth annealing. Accordingly, embodiments described herein provide a heterostructure, wherein Sb atoms are sufficiently strong bound to a surface, incorporated in the layer or are reduced or even eliminated at the surface. Thereby, exchange of Sb by other atoms, particularly by As can be reduced and the quality of the heterostructure can be improved. Also, it allows the reduction of less stable antimony oxides on the oxide-semiconductor surface, which is beneficial for improved device operation.
The above example relates to antimony being replaced by other atoms as exchange of Sb can have a stronger effect as compared to other elements. However, undesired exchange of elements in one layer during growth of another layer or from another layer, e.g. during annealing, can also be present for elements other than Sb. Accordingly, the above described intermediate layer can also be applied for boundaries between different layers of a heterostructure, where antimony is not a dominating element.
The MOSFET structure shown in
According to embodiments described herein, the insertion or intermediate layer is deposited or grown to have an understoichiometric property (III)x>1(V)x<1, i.e. a group-V understochiometric property. Such heterostructures allow for elimination or minimization of Sb, surface Sb, or excess Sb on the growth surface. Sb, surface Sb, or excess Sb on the growth surface can be susceptible to being exchanged by incoming As atoms. Exchange of Sb by As results in intermixing between subsequent layers of the heterostructure, defect creation and interface degradation during the growth or post-growth annealing. Accordingly, embodiments described herein include a heterostructure, wherein Sb atoms are sufficiently strong bound to a surface, are incorporated in a layer to be bound therein, or are reduced or even eliminated at the surface. Thereby, exchange of Sb by other atoms, particularly by As can be reduced and the quality of the heterostructure can be improved.
The above example relates to antimony being replaced by other atoms as exchange of Sb can have a stronger effect as compared to other elements. However, undesired exchange of elements in one layer during growth of another layer or from another layer, e.g. during annealing, can also be present for elements other than Sb. Accordingly, the above described intermediate layer can also be applied for boundaries between different layers of a heterostructure, where antimony is not a dominating element.
The HEMT structure shown in
According to embodiments described herein, intermediate or insertion layers can be utilized for the different heterostructures. These insertion layer can be provided in the quinternary compound semiconductor system of Al, Ga, In, As, and Sb such that the band gap characteristics of the desired heterostructure is not disturbed or is disturbed only to an acceptable amount. The under-stoichiometric property (III)x>1(V)x<1, i.e. a group-V under-stoichiometric property, and characteristics of the intermediate layer improves the boundary characteristics for the heterostructure layer boundaries. According to different embodiments, which can be combined with other embodiments described herein, the thickness of the intermediate layer can be 10 monolayers or below, particularly 7 monolayers or below. For example, the intermediate layers described herein can have a thickness such that the intermediate layer forms also only a part or portion of a monolayer. Thereby, the intermediate layer has a number of atoms, which do not fully cover the surface of the below deposited layer. However, the non-stoichiometric property can still be able to reduce exchange of atoms between the neighboring semiconductor layers of different composition. Yet, embodiments described herein generate a heterostructure, wherein Sb atoms are sufficiently strong bound to a surface, are incorporated in a layer to be bound therein, or are reduced or even eliminated at the surface. Thus, exchange of Sb on the growth surface by incoming As atoms can be reduced.
According to embodiments described herein, the insertion or intermediate layers are grown to have an understoichiometric property (III)x>1(V)x<1, i.e. a group-V understoichiometric property. Such heterostructures allow for elimination or minimization of Sb, surface Sb, or excess Sb on the growth surface. Sb, surface Sb, or excess Sb on the growth surface can be susceptible to being exchanged by incoming As atoms. Depending on the desired band structure of the heterostructure 300, the intermediate layers 120 and 122 can have different compositions respectively, i.e. the amount of the respective elements of Al, Ga, In, As, and Sb can vary. Yet, the amount of group-III elements and the amount of group-V elements is not stoichiometric and is given by (III)x>1(V)x<1. The insertion or intermediate layers at the emitter-base interface and the base-collector interface improve abrupt junctions from one desired composition to another desired composition in the neighboring layer, i.e. exchange of atoms between neighboring heterostructure layers, particularly As exchanging Sb, can be reduced. This abrupt composition changes or abrupt junctions can reduce leakage currents and, thus, increased emitter efficiency.
However, according to modifications of the embodiments described with respect to
According to embodiments described herein, the insertion or intermediate layers are grown to have an understoichiometric property (III)x>1(V)x<1, i.e. a group-V understoichiometric property. Such heterostructures allow for elimination or minimization of Sb, surface Sb, or excess Sb on the growth surface. Sb, surface Sb, or excess Sb on the growth surface can be susceptible to being exchanged by incoming As atoms. Insertion layers at heterointerfaces improve interface abruptness, crystalline quality, creates desired interfaces, reduces layer intermixing and enhances strain control and optical-electrical properties. These improvements are important factors for high quality type-ii superlattices and heterostructures for ICLs, and QCL as shown by heterostructure 400 of
Between these layers, intermediate or insertion layers 120 are provided. According to embodiments described herein, the insertion or intermediate layers are grown to have an understoichiometric property (III)x>1(V)x<1, i.e. a group-V understoichiometric property. Such heterostructures allow for elimination or minimization of Sb, surface Sb, or excess Sb on the growth surface. Sb, surface Sb, or excess Sb on the growth surface can be susceptible to being exchanged by incoming As atoms. Insertion layers at heterointerfaces improve interface abruptness, crystalline quality, creates desired interfaces, reduces layer intermixing and enhances strain control and optical-electrical properties.
According to a typical example, A, B, C, D, and E, each given by one of Al, Ga, In, As, and Sb can be provided as (ABC)1(DE)1 for a barrier layer 512 and/or 516. According to modifications thereof, the compound semiconductor can also be binary, ternary or quaternary such that one or more of A, B, C, D, and E is not included in the barrier layer. Typically, the thickness of the one, more, or all of the barrier layers 512, 514 can be 7 monolayers thick to 2 μm thick. In the above described abbreviation of (ABC)1(DE)1, A, B, C are group-III and D, E are group-V elements, respectively, and are grown under group-V rich conditions. Such barrier layer is followed by a thin insertion or intermediate layer 120, which can be 7 ML to parts of ML thick. The intermediate layer 120 is a compound semiconductor layer with (ABC)x>1(DE)x<1, and grown under group-III rich conditions.
The thin insertion layer 120 is followed by another compound semiconductor layer (ABC)1(DE)1, which can be an active layer 514. The active layer can be 2 μm to 7 ML thick. As shown in
According to different embodiments, which can be combined with other embodiments described herein, the compound semiconductor layers can be grown on any desired substrate, such as GaSb, GaAs, InP, Si, InSb, InAs, GaP, and Ge.
Typically, a first semiconductor layer and/or a second semiconductor layer are grown under group-V rich conditions. This can for example, be a barrier layer, which is grown under group-V rich conditions. The first and second semiconductor layer can be grown at a temperature of 250° C. to 550° C. and up to the layer reaching a desired thickness.
Between the two semiconductor layers, an insertion or intermediate layer with under-stoichiometric properties are provided. According to yet further embodiments, e.g. a heterostructure as shown in
The embodiments described herein allow the elimination, minimization or reduction of Sb on the growth surface, which is very susceptible to being exchanged by incoming As atoms. Accordingly, intermixing between layers can be reduced, which, in turn reduces defect creation and interface degradation during the growth or post-growth annealing of the structures.
Particularly, in light emitting structures such above mentioned techniques allow the suppression of wavelength shift due to intermixing between active layers and barrier layers during growth and post-growth annealing. This results in improved device performance in terms of electrical, optical and temperature parameters. Moreover, such techniques allow the fabrication of devices with reproducible parameters, especially, emission wavelength and electro-optical performance from run-to-run. Thereby, it should be noted that exchange of elements, interdiffusion or the like typically results in unpredictable fluctuations in devices, which cannot be controlled. Accordingly, intermediate or insertion layers according to embodiments described herein, even though they might result in a deviation of the perfect heterostructure for a device, might still be superior as compared to common heterostructures, as the common heterostructures show unpredictable fluctuations due to lack of control of exchange of elements.
In general, such abovementioned heterostructure can be applied to a variety of semiconductor devices as described herein. Thereby, light emitting devices or light absorbing structures can be selected from the group consisting of: a laser, an LED, an SLED, an ICL, a QCL, a photo detector, and a type-II superlattice detector. Transistors can be selected from the group consisting of: a HBT, a MOSFET, a FET, and a HEMT. The improved properties of such heterostructures can be particularly useful for optoelectronic device, because the improvement might be especially useful for structures where electrical and optical properties are to be improved at the same time.
According to embodiments described herein, intermediate or insertion layers can be utilized for the different heterostructures. These insertion layer can be provided in the quinternary compound semiconductor system of Al, Ga, In, As, and Sb such that the band gap characteristics of the desired heterostructure is not disturbed or is disturbed only to an acceptable amount. The non-stoichiometric characteristics of the intermediate layer improves the boundary characteristics for the heterostructure layer boundaries. According to different embodiments, which can be combined with other embodiments described herein, the thickness of the intermediate layer can be 10 monolayers or below, particularly 7 monolayers or below. For example, the intermediate layers described herein can have a thickness such that the intermediate layer forms also only a part or portion of a monolayer. Thereby, the intermediate layer has a number of atoms, which do not fully cover the surface of the below deposited layer. However, the non-stoichiometric property can still be able to reduce exchange of atoms between the neighboring semiconductor layers of different composition. Further, utilizing the insertion or intermediate layers allows for higher concentration gradients as the exchange of atoms or intermixing of elements is reduced.
While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
| Number | Date | Country | Kind |
|---|---|---|---|
| 12188884.6 | Oct 2012 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2013/071763 | 10/17/2013 | WO | 00 |
