1. Field of the Invention
The present invention relates to a semiconductor manufacturing method and an exposure mask used in a lithography process for manufacturing semiconductor devices.
2. Description of the Related Art
The integration of semiconductor devices has constantly increased by four times every three years, because MOS type logic devices require higher functionality and memory devices require larger storing capacity. The improvement in the integration is provided by miniaturizing the design size of semiconductor devices. The miniaturization is very advantageous because it increases operating speed and reduces power consumption in semiconductor devices, and therefore it is desired more and more.
Under this situation, downsizing to 0.1 μm or less has been required as the minimum processing size of semiconductor devices, for example a wiring pitch, gate clearance, etc., and manufacturing processes of semiconductor devices are becoming more and more difficult.
Especially, lithography technology is confronted with much more difficulty. In lithography technology, a circuit pattern formed in a mask is transferred to a resist film of a semiconductor substrate using ultraviolet light generated by an exposure apparatus. The resist film is then developed to form the circuit pattern in the resist film. Etching is performed based on the circuit pattern, to form circuit elements such as gate electrodes and wirings. An ArF excimer laser having a wavelength of 0.193 μm is used as an ultraviolet light source.
Recently, the minimum processing size of semiconductor devices became smaller than the wavelength of light sources of exposure apparatuses. Even if image reduction projection is employed to increase the numerical aperture, resolution limit is exceeded. Therefore, there exists a problem that edge positions and shapes of the exposed pattern on the resist film are deformed, that is, the pattern formed in the mask cannot be accurately transferred onto the resist film.
If a mask pattern 101 as shown by the chain line in
A variety of technologies (for example, in the patent references cited below) are proposed to inhibit the shortening phenomenon due to this optical proximity effect. For example, an Optical Proximity Correction (OPC) method has been proposed. In the OPC method, a mask pattern is broadened more than a designed wiring pattern at a place where shortening occurs. Alternatively, dummy patterns are arranged around a place where shortening occurs, in order to inhibit the shortening.
For example, as shown in
In the method shown in
In the method shown in
Accordingly, the present invention is made in view of the above-mentioned problems, and aims at offering a semiconductor manufacturing method and an exposure mask that inhibit the shortening problem and bad connections and short circuits of wiring in lithography processes.
According to one aspect of the present invention, a semiconductor manufacturing method including a lithography process having an exposure step for projecting an image of a mask pattern of a mask onto a photo resist layer using exposure light is provided. In the method, the mask pattern comprises: a first pattern having a light transparency characteristic, corresponding to a circuit pattern; and a second pattern having an inverted light transparency characteristic, arranged within and spaced apart from the first pattern.
According to another aspect of the present invention, a method for manufacturing a semiconductor device including a first region having close gate patterns and a second region having sparse gate patterns, including a lithography process having an exposure step for projecting an image of a mask pattern of a mask onto a photo resist layer of the semiconductor device using exposure light is provided. In the method, the mask pattern comprises: in a region corresponding to the first region, a first pattern being light shielding and corresponding to the gate electrode patterns, and a second pattern being light transparent and arranged within and spaced apart from the first pattern; and in a region corresponding to the second region, a third pattern being light shielding and corresponding to the gate electrode patterns; wherein a width of the first pattern is larger than a width of the third pattern.
According to another aspect of the present invention, a method for manufacturing a semiconductor device including a first region having close wiring patterns and a second region having sparse wiring patterns, including a lithography process having an exposure step for projecting an image of a mask pattern of a mask onto a photo resist layer of the semiconductor device using exposure light is provided. In the method, the mask pattern comprises: in a region corresponding to the first region, a first pattern being light transparent and corresponding to the wiring patterns, and a second pattern being light shielding and arranged within and separated from the first pattern; and in a region corresponding to the second region, a third pattern being light transparent and corresponding to the wiring patterns; wherein a width of the first pattern is larger than a width of the third pattern.
According to the present invention, the shortening phenomenon can be effectively inhibited.
Features and advantages of the present invention are set forth in the description that follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description.
In the following, embodiments of the present invention are described with reference to the accompanying drawings.
Referring to
In this case, the first pattern MP1 is transparent to light. The second pattern MP2 and the region outside of the first pattern MP1 have light shielding characteristics. Another mask pattern having an inverted transparent characteristic is also included in the present invention, but its explanation is omitted.
Referring to
On the other hand, when the second pattern MP2 is provided within the first pattern MP1, the light transmitted through the second mask region A2 is partially shielded by the second pattern MP2. The second pattern MP2 is small enough so that no image of the second pattern MP2 can be projected on the resist layer, and therefore the light transmitted outside of the second pattern MP2 is diffracted and distributed over the whole region R2 on the resist layer. Therefore, the illumination distribution IL2 in the penumbra region R2 is even, and is lower than the illumination distribution IL1.
On the other hand, since the second pattern MP2 is not formed in the first mask region A1, the illumination on the region R1 is substantially the same as in the illumination distribution IL1.
Under this condition, when the intensity of the light source is increased, resultant illumination IL3 becomes larger proportionally. Then the shortening portion where the illumination distribution IL3 is lower than TH becomes smaller. That is, the shortening amount S2 is smaller than S1.
In this manner, the present invention can suppress the shortening effectively. Although
A mask pattern according to a first embodiment of the present invention is explained below.
Referring to
The auxiliary patterns 12 are formed within the wiring patterns 11, and configured so as to shield ultraviolet light. Each of the wiring patterns 11 has first regions 11-1 at the longitudinal ends 11a thereof and a second region 11-2 between the first regions. The auxiliary patterns 12 are formed in the second regions 11-2. The auxiliary patterns 12 are placed in parallel to the wiring patterns 11 and spaced apart from the sides of the wiring patterns 11. As shown in
The width W1 of each of the auxiliary patterns 12 is determined so as not to form an image on a resist film (not shown) that is an image-formation plane onto which the mask pattern 10 is transferred by exposure. By defining the auxiliary patterns 12 in this manner, ultraviolet light transmitting through the wiring patterns 11 is diffused to regions on the image-formation plane corresponding to the auxiliary patterns 12, and its intensity of illumination is lowered compared with a case where no auxiliary pattern 12 is provided.
On the other hand, there is no auxiliary pattern 12 in the first regions 11-1 at the ends of the wiring patterns 11. Therefore, the intensity of illumination is not lowered at regions on the image-formation plane corresponding to the first regions, and is the same as in a case where no auxiliary pattern 12 is provided, because the intensity of illumination is determined by the proximity effect in outer regions of the wiring patterns 11. Accordingly, by providing the auxiliary patterns 12, the intensity of illumination is relatively increased at the regions on the image-formation plane corresponding to the first regions 11-1 compared to the regions on the image-formation plane corresponding to the second region 11-2 due to the above explained principle. The amount of exposure (referred to as “exposure amount on light receiving face” herein) becomes equal over a larger area, resulting in inhibiting the shortening at the ends 11a of the wiring patterns.
The appropriate width W1 of the auxiliary patterns 12 is determined depending on projecting resolution of the exposure device. A reduced width W1 projected onto the image-forming plane is preferably in the range of 2%-20% of the wavelength of the light source. If the reduced width is larger than 20%, the auxiliary patterns 12 may form images. If the reduced width is smaller than 2%, the equality of the illumination is degraded. For example, if an excimer laser having a wavelength of 193 μm is used as a light source, a reduced width W1 of the auxiliary pattern 12 projected onto the image-forming plane is preferably in the range of 4 nm-40 nm, and more preferably in the range of 15 nm-40 nm.
The length of any portion of the mask pattern 10 means a reduced length projected onto the image-forming plane unless otherwise defined. If an exposure device has a reduction ratio of 4:1 for projecting, the length of any portion of the mask pattern is reduced to ¼ on the image-forming plane. In this specification, width direction lengths mean lengths in the shorter side direction of rectangles.
A distance L1 between the ends 12a of the auxiliary patterns 12 and the ends 11a of the wiring patterns 11 is appropriately selected depending on the wavelength of light source to be used for exposure, the configuration, and layout of the wiring patterns 11. For example, if an ArF excimer laser (wavelength: 193 nm) is used as a light source, and widths of the wiring patterns are 90 nm, then the distance L1 is preferably in the range of 50 nm-200 nm.
It is preferable that the auxiliary patterns 12 be placed substantially at the center of the widths of the wiring patterns 11, so as to prevent the images of wiring patterns 11 projected on the image-forming plane from decreasing in width.
The mask pattern 10 having the auxiliary patterns 12 within the wiring patterns 11 according to this embodiment can effectively inhibit the shortening problem, even if the wiring patterns 11 are arranged so closely that no hammer head can be provided. The mask patterns 10 according to this embodiment can still be utilized under conditions where the spaces between the wiring patterns 11 become shorter and the wavelength of exposure devices becomes shorter.
In the mask pattern 10 of the exposure mask according to this embodiment, the inside of the wiring patterns 11 is light transparent and the region outside of the wiring patterns 11 and the auxiliary patterns have shielding characteristics. However, a mask pattern having inverted light transparency can be used. That is, the inside of the wiring patterns 11 can have shielding characteristics and the region outside of the wiring patterns 11 and the auxiliary patterns 12 can be light transparent. In this case, the light transmitting through the auxiliary patterns 12 diffuses and illumination is increased at the middle portion rather than at the ends of the image-formed wiring patterns 11, resulting in equal illumination distribution over the wiring patterns 11. Therefore, by lowering the amount of light source power (brightness) multiplied by exposure time (referred to as “exposure amount of light source” herein), the shortening problem can be inhibited. Such mask patterns can be utilized in forming gate layers as gate electrodes of MOS transistors, for example, and are explained in more detail in a second embodiment below.
A wiring pattern was formed on a resist film applied on a silicon substrate using an exposure mask according to the first embodiment of the present invention.
Referring to
An exposure device used an ArF excimer laser (wavelength: 193 nm) as a light source and a reducing projection system having a reduction rate of ¼ (mask pattern size:image-formed pattern size=4:1). A 250 nm thickness positive type chemically amplified resist film was applied on a silicon substrate, exposed and developed to form an aperture of wiring pattern 16 in the resist film.
The exposure amount of the light source was selected so as to minimize the amount of shortening, which is explained below. For example, the exposure amount of the light source in a case where the width W3 of the auxiliary pattern is 15 nm, was increased by 25% compared to the no auxiliary pattern case.
As shown on the right side of
Comparing Sample
As shown in
Referring to
In the comparison sample, when plural wiring patterns are arranged in parallel, the wider the auxiliary pattern W4 is, the shorter the space between adjacent wiring patterns becomes. In the first example, when plural wiring patterns are arranged in parallel, even if the auxiliary pattern W3 becomes wider, the space between adjacent wiring patterns is constant. Therefore, the first embodiment is advantageous because it can prevent short circuits effectively, especially when the wiring pitch becomes shorter.
Simulation was performed for both the first example and the comparison sample under the condition that plural wiring patterns are closely arranged.
As shown at the left side of
On the other hand, as shown at the left side of
As shown on the right side of
On the other hand, as shown on the right side of
Accordingly, the mask pattern according to the first example can suppress the shortening problem while avoiding wiring pattern short circuits even when the wiring pattern pitch is decreased.
Next, mask patterns according to a first alternative example of the first embodiment are explained below.
With reference to
As shown in
As shown in
As shown in
The auxiliary patterns shown in
With reference to
Since that the width W5 is broader than the designed width W6 of the designed wiring pattern 53, illumination is further equalized at first regions 51-1 at the ends of the wiring pattern 51 and at a second region 51-2. Therefore, shortening is suppressed and illumination is increased at an image-forming plane of the wiring pattern 51, and the exposure amount of the light source can be decreased. The designed wiring patterns 53 are determined by considering wiring resistances and capacities between wirings in each wiring layer but without considering shortening.
It is preferred that a ratio W5/W6 of the width W5 and the width W6 be 1.02-1.20. It is preferred that a difference between the width W5 and the width W6 be substantially equal to a width of the auxiliary pattern 52.
With reference to
Since the wiring patterns 51 of the first mask portion 61 have the above mentioned second alternative example wiring patterns, illumination is increased at the image-forming plane of the wiring patterns 51, and is substantially the same as the illumination of the wiring patterns 63 at its image-forming plane. Therefore, it is possible to have substantially the same exposure amount of a light source for the first and second mask portions 61, 62, resulting in easy controlling of the exposure amount of the light source.
The first alternative example mask pattern, the second alternative example mask pattern and
A method for fabricating semiconductor devices according to a second embodiment of the present invention is now explained. A lithograph process in the semiconductor device fabrication method according to this embodiment uses an exposure mask having mask patterns according to the above mentioned first embodiment.
In the step shown by
In a step shown by
In the exposure process, ultraviolet light is irradiated from a light source 77 of an exposure device to the exposure mask 74 to make images of the mask patterns 74b at a surface of the resist film 73, resulting in latent images 73a. Ultraviolet light transmitting through the apertures 76-1 of the mask 76 is diffused, and illumination at the gate layer pattern region 73b (dark portion) becomes uniform.
In this example where the auxiliary pattern is transparent, the exposure amount of light source is preferably defined to be smaller than in a case where no auxiliary pattern is provided, and preferably defined so as to make the exposure amount on the light receiving face as small as possible but more than a minimum threshold value for exposing the resist layer at desired regions. By weakly and equally illuminating the gate layer regions 73b and highly illuminating the exposed portions 73a and photo-etching only the portions 73a, shortening of the gate layers can be suppressed.
On the other hand, in a case where the auxiliary patterns 12 are light shielding and are inside of the wiring patterns 11, the exposure amount of the light source is preferably defined to be larger than in a case where no auxiliary pattern is provided. By increasing the illumination on the image-formed wiring pattern regions equally, shortening of the gate layers can be suppressed.
Next, in a step shown by
The exposure mask 74 shown in
The projecting system of the exposure device of
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention. Prior art POC methods such as hammer head can be combined with the present invention.
The present application is based on
Japanese Priority Application No. 2004-196963 filed on Jul. 2, 2004 with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
Number | Date | Country | Kind |
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2004-196963 | Jul 2004 | JP | national |