The present invention relates to a semiconductor memory device and a method for producing the device.
Memory designs are continuously being introduced in the ongoing development of modern semiconductor memory technologies. These designs relate in particular to nonvolatile memories. In particular, the memory media to be provided in the respective memory cells or memory elements are selected and used with regard to their physical properties during phase transformations. Thus, by way of example, nonvolatile memories are known in which the memory medium undergoes a transition during a phase transformation from a low-resistance (if appropriate crystalline) state to a high-resistance (if appropriate amorphous) state. This design thus makes use of a material as a memory medium that has two stable phases, namely a high-resistance amorphous phase and a low-resistance crystalline phase. The material can be switched back and forth reversibly with regard to these two phases by electrical pulses. The corresponding changes in resistance during the phase transition between the amorphous phase and the crystalline phase are used for information storage. Although so-called chalcogenides have customarily been used heretofore for this purpose, in principle any material that permits a reversible changeover between a high-resistance and a low-resistance state is suitable as memory medium in these nonvolatile memories.
What is problematic about known semiconductor memory technologies based on a phase transformation memory effect is that a specific quantity of heat must be fed to the respective memory cell or to the respective memory element in order to initiate and carry out the phase transformation. In this case, the quantity of heat supplied has to be prevented from also influencing adjacent cells or elements and changing the information state thereof. This has been realized heretofore by complying with a specific minimum distance between adjacent memory cells or elements in a semiconductor memory device with a phase transformation memory effect. However, complying with such a minimum distance between two adjacent memory cells or memory elements goes against endeavors to provide a highest possible integration density for semiconductor memory devices.
An object of the present invention is to provide a semiconductor memory device based on a phase transformation memory effect material and also a method for producing the device by which semiconductor memory devices with a phase transformation memory effect can be realized with a particularly high integration density and nevertheless a high functional reliability.
The aforesaid and further objects are achieved individually and/or in combination, and it is not intended that the present invention be construed as requiring two or more of the objects to be combined unless expressly required by the claims attached hereto.
In accordance with the present invention, a semiconductor memory device includes at least one memory element with a phase transformation memory effect and a cavity arrangement with at least one cavity in spatial proximity to the respective memory element in such a way that the thermal coupling of the respective memory element to the surroundings of the memory element is formed in reduced fashion by reduction of the thermal conductivity between memory element and surroundings.
Consequently, a fundamental idea of the present invention is to provide a cavity arrangement with at least one cavity in the semiconductor substrate in which the memory element is formed. The respective cavity avoids providing a material which has a specific residual thermal conductivity. The cavity, whether evacuated or filled with gas, in any event always has a lower thermal conductivity than a material region formed in a corresponding manner, so that the thermal coupling between the memory cell and its surroundings, namely the semiconductor substrate or an adjacent element, is reduced.
A particularly advantageous embodiment of the semiconductor memory device according to the invention results when, for the memory element in the semiconductor substrate, a first or bottom access electrode device is provided, a second or top access electrode device is provided and also a memory medium is formed at least partly in between with a phase-dependent nonreactive resistance in a manner contact-connected to the access electrodes. At least one of the access electrode devices, preferably the first or bottom access electrode device, is provided and formed as an excitation electrode or heating electrode for locally heating the contact-connected memory medium and thus for initiating a corresponding phase transformation process or a corresponding phase transformation.
At least a part of the cavity arrangement, in particular at least one cavity, is provided in spatial proximity to the excitation electrode and/or in spatial proximity to the memory medium for the purpose of thermal insulation from the surroundings. As a result, in particular that element which carries the greatest part of the heat and is thus most likely to have a high temperature, namely that electrode which is designed for heating the memory medium and thus for exciting the phase transformation process, is thermally insulated from the surroundings by the cavity, so that a transfer of heat to the surroundings, and in particular to adjacent memory elements that are not selected, is at least reduced.
In another embodiment of the semiconductor memory device according to the invention, the excitation electrode in each case is assigned a cavity of the cavity arrangement, and the assigned cavity is directly adjoined to at least a part of the excitation electrode. In this embodiment, it is preferred for the assigned cavity to surround at least a part of the excitation electrode. This is because the thermal insulation from the surroundings and from adjacent memory elements is then particularly effective.
In yet another embodiment of the semiconductor memory device according to the invention, the excitation electrode is formed as a connecting region or plug region or as part thereof with respect to a source/drain region of a provided and assigned selection transistor, preferably a lateral selection transistor. This results in a particularly compact design of the semiconductor memory device according to the invention because, in the formation of the respective memory element, there is no need for an additional contact, terminal or plug between the source/drain region of the selection transistor and the respective first or bottom electrode.
In a further embodiment of the semiconductor memory device according to the invention, the excitation electrode is formed in a cutout or a trench structure or a trench, to be precise in the semiconductor substrate underlying the semiconductor memory device.
In another embodiment of the semiconductor memory device according to the invention, the memory medium is formed as a material region of the excitation electrode, preferably in an upper region of the trench structure. This embodiment is particularly space-saving because the memory medium with a phase transformation memory effect is also simultaneously formed in the connection region or plug region—serving as excitation electrode—toward the source/drain region of the selection transistor. This is realized in particular by filling an upper part of the respectively underlying trench structure.
A plurality of memory elements can be provided in the semiconductor memory device according to the invention. In this embodiment, it is advantageous to form a common memory region with a phase transformation memory effect for the plurality of memory elements. Alternatively, it is possible to form individual memory regions for the plurality of memory elements. It is preferable, however, if in each case two memory elements which are formed adjacent to one another in the semiconductor substrate jointly utilize a memory region.
In an embodient where a memory region is jointly utilized by a plurality of memory elements, the cavity arrangement, and in particular the respective cavity or the respective cavities, is at least partly formed laterally between the plurality of memory elements. In this embodiment, the respective cavity arrangement or the respective cavity is then jointly used by a plurality of memory cells. The joint utilization of cavity and memory medium may also be combined with one another in order to achieve a particularly compact configuration of the semiconductor memory device according to the invention.
Furthermore, it is advantageous and, moreover, increases the integration density of the semiconductor memory device according to the invention when a common further or second access electrode device is provided for a plurality of memory elements. In specific applications, however, it may also be advantageous for individual further or second access electrode devices to be formed or provided for the plurality of memory elements.
A method for producing a semiconductor memory device in accordance with the present invention and including at least one memory element with a phase transformation memory effect by providing a cavity arrangement with at least one cavity in spatial proximity to the respective memory element in such a way that the thermal coupling of the respective memory element to the surroundings of the memory element is formed in reduced fashion by reduction of the thermal conductivity between memory element and surroundings.
In a preferred embodiment of the method according to the invention, for the at least one memory element in the semiconductor substrate, a first or bottom access electrode device is provided, a second or top access electrode device is provided and a memory medium is formed at least partly in between with a phase-dependent nonreactive resistance in a manner contact-connected to the access electrode devices. At least one of the access electrode devices, preferably the first or bottom access electrode device, is provided and formed as an excitation electrode for locally heating the contact-connected memory medium and thus for initiating a corresponding phase transformation process or a corresponding phase transformation. At least a part of the cavity arrangement and in particular at least one cavity is provided in spatial proximity to the excitation electrode and/or the memory medium for the purpose of thermal insulation from the surroundings. In this embodiment, the excitation electrode is in each case assigned a cavity of the cavity arrangement, in such a way that the assigned cavity directly adjoins at least a part of the excitation electrode. In this embodiment, it is also preferred that the assigned cavity is formed in a manner surrounding at least a part of the excitation electrode.
In another embodiment of the method according to the invention, the excitation electrode is formed as a connecting region or plug region or as part thereof with respect to a source/drain region of a provided and assigned selection transistor, in particular a lateral selection transistor.
In accordance with a further embodiment of the method according to the invention, the excitation electrode is formed in a cutout or a trench structure in the semiconductor substrate.
The memory medium itself may be formed as a material region of the excitation electrode, in particular in an upper region of the respective trench structure.
It is particularly advantageous to provide a plurality (e.g., two) of memory elements, and the plurality of memory elements are formed with a common memory region. Alternatively, individual memory regions or memory media in each case can be formed for the plurality of memory elements. It is preferred that the cavity arrangement, and in particular the respective cavities, is at least partly formed laterally between the plurality of memory elements or memory cells. It is also preferred that a common further or second access electrode device is formed for the plurality of memory cells or memory elements. As an alternative, individual further or second access electrode devices are also conceivable for the plurality of memory elements or memory cells.
In a further embodiment of the method according to the invention, the cavity arrangement and the respective cavities are lined with a thin layer made of SiO2 or BPSG on the inside.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, particularly when taken in conjunction with the accompanying drawings wherein like reference numerals in the various figures are utilized to designate like components.
A series of designs, such as ferroelectric memories, magnetoresistive memories, and also phase transformation memories are being discussed for future nonvolatile memories.
In the case of phase transformation memories, the information is represented as a crystalline or amorphous state of a vitreous material. In this case, the phase transformation is effected by heating the material via a suitable electrical pulse. Chalcogenides GexSby—Tez, InSbTe, AgInSbTe and the like are used as preferred materials. The material utilized most often, Ge2Sb2Te5, requires, e.g., approximately 310° C. for crystallization and approximately 600° C. for melting and thus for converting the material from the crystalline phase to the amorphous phase.
One problem consists in the fact that even when heating the material to 600° C., an adjacent cell must not become so hot that it changes its state. This problem at the present time limits the scalability and integration density of phase transformation memories.
According to present-day estimations, the limit of the scalability and integration density of phase transformation memories occurs at minimum feature sizes of approximately 70 nm due to the influencing of an adjacent bit in the case of erasure. Conventional integration routes could still be taken in the case of the minimum feature sizes of 180 nm and 130 nm that are currently being discussed. Insulation materials having a much lower thermal conductivity than silicon dioxide, which has been used heretofore, are currently being discussed for the 70 nm generation and beyond.
Silicon dioxide has a thermal conductivity of 0.014 W/cm K. In comparison therewith, the preferred material class for phase transformation materials is 0.003-0.18 W/cm K. The preferred material composition at the present time, Ge2Sb2Te5, has a value of 0.0046 W/cm K, so that a large part of the heat is dissipated by the insulation material in this case. An improvement would result, for example, by using polyimide having a thermal conductivity of 0.0016 W/cm K. However, this cannot readily be integrated into a CMOS process sequence at the required point.
The invention solves this problem by separating the individual cells from one another via cavities. This has the effect that the thermal conductivity between the cells becomes minimal.
One feature of the invention resides in separating the individual cells from the surroundings and respectively from one another indirectly or directly via cavities, to be precise both structurally and by a suitable process implementation.
A number of embodiments of the invention are described below. In one embodiment, a suitable sacrificial layer is removed about the heating element. This has the effect that the heater or the excitation electrode is thermally insulated from the surroundings.
In another embodiment, the activated region is additionally insulated from the surroundings by concomitantly introducing it into the opening for the heating electrode. In a further embodiment, the heating elements are encapsulated in etching stop layers, and the insulation material is subsequently removed between the structures. In this embodiment, it is possible for the phase transformation material itself to be integrated into the cutout for the heating element.
In an additional embodiment, the sacrificial layer or the spacer can be applied and patterned lithographically such that they project significantly beyond the contact hole. Thus, prior to the application of the metallization, an opening may be etched as far as the sacrificial layer and the latter may be wet-chemically removed selectively with respect to the surroundings. This has the effect that the structure is insulated toward the bottom in the direct surroundings as well.
A further embodiment, in relation to all the previously described structures, inludes applying a further very thin layer (e.g., an SiO2 that is 5-10 nm thick) between the cavity and the heating electrode material or heating electrode material and chalcogenide by the known spacer technique. This has the effect, when etching the sacrificial layer and the heating electrode material, of preventing the latter from being attacked by the etching.
Further features for reducing the thermal coupling includes using an SOI substrate (heat flow via the silicon is prevented) and in introducing an additional thermal insulation between chalcogenide and top electrode, and in producing the contact only at the edge, e.g. by spacers or overlap, or at individual locations by contacts.
Embodiments of the invention are now described with reference to the figures, where structurally or functionally similar or identical elements or material regions are designated by the same reference symbols hereinafter without a detailed discussion of their properties being repeated upon every occurrence in the description or in the figures.
In the transition to the intermediate state of
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As an alternative, the cavities H1, H2 can be closed off by deposition and subsequent flowing of a BPSG layer. This alternative has the advantage that the inner walls of the cavities H1, H2 are then lined with BPSG.
In the transition to the state of
A layer 26 of a material with a phase transformation nature is then deposited, as is illustrated by the state of
In the transition to the state of
Another variation of the production method according to the invention proceeds from the structure illustrated in
In the transition to the intermediate state shown in
In the transition to the state of
The transition to the state of
Another variation of the production method according to the invention begins with an arrangement which corresponds to the arrangement of
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In the transition to the state of
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In the transition to the state of
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In the transition to the state of
The etching stop layer 27 is then opened between two cells, as is indicated by the cutout 42 in
In the transition to the state of FIGS. 25 to 27, then, firstly the insulation material of the region 22z is removed by etching selectively with respect to the etching stop layer through the opening hole 42, as a result of which a cavity H arises between the two bottom or first access electrode devices 14-1 and 14-2. Afterward, an insulation layer with poor edge coverage is then deposited in order to close off the opening hole 42 and consequently the cavity H by a plug 42p. The plug 42p is shown in
As an alternative, the cavities H1, H2 may be closed off by deposition and subsequent flowing of a BPSG layer. This variant has the advantage that the inner walls of the cavities H1, H2 are then lined with BPSG.
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In an alternative embodiment, proceeding from the intermediate state of
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All of the structures described previously can be formed with the material combinations listed below. The first semiconductor material substrate region 21 of the semiconductor substrate 20 may include p-type silicon, by way of example. The source/drain regions SD11, SD12, SD21, SD22 can then correspondingly include n+-type silicon. The conductivity types or conduction types can also be interchanged. The gates G1 and G2 can be fabricated from polysilicon, polycide, salicide or from a suitable material. Examples of appropriate insulation materials, in particular for the regions 22 and 23, are silicon dioxide, silicon oxynitride, BPSG or the like. Etching stop materials for the spacers 32f can be formed for example from silicon nitride, from aluminum oxide or the like. The material for the first or bottom access electrode devices 14, 14-1, 14-2, 14-1′, 14-2′, that is to say for the excitation electrode, which may also be referred to as a heating electrode, may appropriately be tantalum nitride, titanium silicon nitride, titanium nitride, titanium aluminum nitride, titanium silicon nitride, carbon, molybdenum, tungsten, titanium-tungsten and the like.
The material of the counterelectrode, that is to say of the second or top access electrode devices 18, may be aluminum, copper, tungsten, silicide or the like.
The plugs P1 and P2 can include tungsten, polysilicon, copper or aluminum. The metallizations for the interconnects W can include for example aluminum and copper. The thermal insulator 40 can include for example BPSG, polyimide or the like.
While the invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Number | Date | Country | Kind |
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102 55 117.0 | Nov 2002 | DE | national |
This application is a continuation of International Patent Application No. PCT/DE2003/003885, filed on Nov. 24, 2003, and titled “Semiconductor Memory Device and Method For Producing It,” and further claims priority under 35 USC § 119 to German Application No. DE 102 55 117.0, filed on Nov. 26, 2002, and titled “Semiconductor Memory Device and Method For Producing It.” The entire contents of each of the above-identified patent applications are hereby incorporated by reference.
Number | Date | Country | |
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Parent | PCT/DE03/03885 | Nov 2003 | US |
Child | 11137778 | May 2005 | US |