Semiconductor memory device and semiconductor integrated circuit system

Abstract

In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp by a bit-line precharge circuit and a source-line precharge circuit, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, by a bit-line write bias generation circuit, while the source line is grounded by a source-line write bias generation circuit. At the time of a reset operation, in contrast to the set operation, the bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp, for example. Thus, no negative potential generation circuits are necessary, and the time required for the data read operation is shortened.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a resistance change memory device included in a semiconductor memory device according to a first embodiment of the present invention, and also shows bias potentials thereto.

FIG. 2 shows bias potentials to a conventional resistance change memory device.

FIG. 3 shows the entire block structure of a semiconductor memory device according to the present invention.

FIG. 4 shows the structure of a sense amplifier and members around the sense amplifier in a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 shows the structure of a sense amplifier and members around the sense amplifier in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating the structure of the main part of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 7 shows the structure of a reference potential generation circuit included in the semiconductor integrated circuit according to the third embodiment of the present invention.

FIG. 8 shows a modified example of the reference potential generation circuit.

FIG. 9 shows the internal structure of a write/read circuit in the semiconductor integrated circuit according to the third embodiment of the present invention.

FIG. 10 shows various waveforms occurring when a reset command is issued in the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 11 shows various waveforms occurring when a set command is issued in the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 12 shows various waveforms occurring when data is read in the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 13 shows various waveforms occurring when a set command is issued in the semiconductor integrated circuit according to the third embodiment of the present invention.

FIG. 14 shows various waveforms occurring when a reset command is issued in the semiconductor integrated circuit according to the third embodiment of the present invention.

Claims

1. A semiconductor memory device, comprising: a resistance change memory device with a first node and a second node, for performing a set operation for data and a reset operation for the data by application of a forward bias voltage and a reverse bias voltage across the first and second nodes;a column selection line connected with the first node of the resistance change memory device;a row selection line connected with the second node of the resistance change memory device;a precharge circuit for precharging the first and second nodes of the resistance change memory device to a reference potential when the resistance change memory device is in standby mode;a bias applying circuit for applying a set high potential to one of the first and second nodes of the resistance change memory device and a set low potential to the other of the first and second nodes when the set operation for writing the data is performed, and applying the set low potential to the one node of the resistance change memory device and the set high potential to the other node when the reset operation for the written data is performed; anda read circuit for applying the reference potential to the first or second node of the resistance change memory device when a read operation for reading the data is preformed.

2. The semiconductor memory device of claim 1, wherein the read circuit applies, to the second or first node of the resistance change memory device, the set low potential or a potential which is higher than the reference potential by a potential required for the data read operation.

3. The semiconductor memory device of claim 1, wherein the reference potential is lower than the set high potential.

4. A semiconductor integrated circuit system including the semiconductor memory device of claim 1, the semiconductor integrated circuit system comprising: a system low-voltage source for supplying voltage to internal circuits, and a data input/output high-voltage source used for data input/output,wherein the reference potential used in the semiconductor memory device is power supply potential of the system low-voltage source,the set high potential used in the semiconductor memory device is power supply potential of the data input/output high-voltage source, andthe set low potential used in the semiconductor memory device is ground potential.

5. The semiconductor memory device of claim 1, comprising: a memory cell array including a number of said resistance change memory devices,wherein the bias applying circuit is divided into a first bias applying circuit for applying a bias voltage to the first node of each resistance change memory device and a second bias applying circuit for applying a bias voltage to the second node of each resistance change memory device, andthe first bias applying circuit is disposed at one side of the memory cell array, while the second bias applying circuit is disposed at the other side of the memory cell array.

6. The semiconductor memory device of claim 5, wherein the first and second bias applying circuits are controlled by a common bias-voltage-application control signal.

7. A semiconductor memory device, comprising: a resistance change memory device with a first node and a second node, for performing a set operation for data and a reset operation for the data by application of a forward bias voltage and a reverse bias voltage across the first and second nodes;a column selection line connected with the first node of the resistance change memory device;a row selection line connected with the second node of the resistance change memory device;a sense amplifier for amplifying a potential difference between a set reference potential and a potential produced by the value of resistance of the resistance change memory device;an amplification control circuit for making the sense amplifier constantly perform amplification operation when the data is written; anda write circuit for, at the time of the set operation for writing the data or the reset operation for the written data, starting the data set operation or the data reset operation in the resistance change memory device, and receiving an output signal from the sense amplifier to stop the data set operation or the data reset operation according to the received output signal.

8. The semiconductor memory device of claim 7, wherein a data-read sense amplifier, which is used when a read operation for reading the data is performed, is also used as the sense amplifier, and the semiconductor memory device further includes a set-operation reference potential generation circuit, a reset-operation reference potential generation circuit, and a data-read-operation reference potential generation circuit, which generate different reference potentials for the set operation for writing the data, the reset operation for the written data, and the data-read operation, each of the generated reference potentials being used as the set reference potential.

9. The semiconductor memory device of claim 8, wherein the write circuit stops the data set operation or the data reset operation according to an output signal from the data-read sense amplifier.

10. The semiconductor memory device of claim 8, comprising a read-data output circuit for externally outputting an output signal from the data-read sense amplifier, wherein the write circuit receives the output signal from the data-read sense amplifier through the read-data output circuit, andtiming at which the data-read sense amplifier and the read-data output circuit are started at the time of the set operation for writing the data and the reset operation for the written data is the same as timing at which the data-read sense amplifier and the read-data output circuit are started at the time of the data read operation.

11. The semiconductor memory device of claim 8, wherein the three reference potential generation circuits, i.e., the data-write set-operation reference potential generation circuit, the written-data reset-operation reference potential generation circuit, and the data-read-operation reference potential generation circuit, each have a current path, which is the same as a path of current flowing in the resistance change memory device where the data is written or read at the time of the set operation for writing the data, the reset operation for the written data, and the data read operation, have a plurality of resistance devices for voltage division in the current path, and are selected according to a set command, a reset command, and a read command, respectively.

12. The semiconductor memory device of claim 7, comprising a reference potential generation circuit for generating the set reference potential, wherein the reference potential generation circuit includes:a first P-channel transistor whose source is connected with a power source used for data writing;a second P-channel transistor whose source is connected with a power source used for data reading;a plurality of resistance devices for voltage division, all of which are connected with the first and second P-channel transistors; anda selection circuit for selecting either the first or second P-channel transistor.