Claims
- 1. A semiconductor memory device, comprising:a semiconductor substrate; a plurality of dielectric films stacked on a main surface of said semiconductor substrate; a memory cell area in which a field-effect transistor provided with a diffusion region and a conductive type of which is reverse to that of said semiconductor substrate, a gate electrode, a gate insulating film and, a capacitor are formed; and a peripheral circuit area and a first wiring formed in said peripheral circuit area, wherein: said capacitor circuit is formed in a concave portion which is bored through more than two dielectric films of said plurality of dielectric films in said memory cell area; a plurality of second wirings located over said stacked dielectric films in said peripheral circuit area and one of said second wirings is connected to said first wiring by a plurality of plugs, which plugs are connected by stacking thereof; and an upper face of said stacked dielectric films in extended from said peripheral circuit area to said memory cell area, and is in contact with the side face of a storage electrode of said capacitor.
- 2. A semiconductor memory device according to claim 1, wherein said capacitor includes said storage electrode, a capacitor dielectric film and a plate electrode, wherein said storage electrode is formed on an inner face of said concave portion.
- 3. A semiconductor memory device according to claim 2, wherein:some of said stacked dielectric films are provided between said capacitor and said semiconductor substrate; a first wiring layer located on one of said stacked dielectric films is separated from said capacitor; and a second wiring layer located on one of said stacked dielectric films is formed over said capacitor.
- 4. A semiconductor memory device according to claim 3, wherein said first wiring layer is selected from one of a polycrystalline silicon film containing high-concentration impurities; a stacked film of a polycrystalline silicon film and a silicide film; a stacked film of a tungsten film, a barrier metal film and a polycrystalline silicon film; and a stacked film of a tungsten film and a barrier metal film; a tungsten film; and a copper film.
- 5. A semiconductor memory device according to claim 2, wherein said capacitor dielectric film is selected from one of a stacked film of an oxide film and a nitride film; a stacked film of an oxide film and a tantalum pentoxide film; a stacked film of a nitride film and a tantalum pentoxide film; and a stacked film of an oxide film, a nitride film, and a tantalum pentoxide film; a BST film; and a PZT film.
- 6. A semiconductor memory device according to claim 2, wherein said plate electrode is comprised of a polycrystalline silicon film containing high-concentration impurities or a refractory metal film.
- 7. A semiconductor memory device according to claim 2, wherein said storage electrode is electrically connected to the diffusion region of said field effect MOS transistor formed in said memory cell area, via a conductor formed through some of said stacked dielectric films provided between said capacitor and said semiconductor substrate.
- 8. A semiconductor memory device according to claim 3, wherein said first wiring layer is electrically connected to said second wiring layer, via a conductor formed through some of said stacked dielectric films.
- 9. A semiconductor memory device according to claim 2, wherein an upper face of one of said stacked dielectric films is extended into said memory cell area and is in contact with the side or bottom of said capacitor, and the upper face is in contact with a lower face of a wiring layer formed in said peripheral circuit area.
- 10. A semiconductor memory device according to claim 9, wherein:the storage electrode of said capacitor is provided in said concave portion; and the capacitor dielectric film and the plate electrode are extended outside from the inner face of the storage electrode.
- 11. A semiconductor memory device according to claim 9, wherein:the storage electrode of said capacitor is formed on the inner face of said concave portion and protruded upward from the inner face of said concave portion; and the capacitor dielectric film and the plate electrode are extended outside the protruded portion of the storage electrode from the inside of said storage electrode.
- 12. A semiconductor memory device according to claim 9, wherein the second wiring layer is formed over said capacitor, via some of said stacked dielectric films.
Priority Claims (3)
Number |
Date |
Country |
Kind |
7-300960 |
Nov 1995 |
JP |
|
7-302460 |
Nov 1995 |
JP |
|
7-340368 |
Dec 1995 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of U.S. application Ser. No. 09/077,100, filed May 20, 1998; Now U.S. Pat. No. 6,617,205, which is a 371 of PCT/JP96/03343, filed Nov. 14, 1996.
US Referenced Citations (17)
Foreign Referenced Citations (18)
Number |
Date |
Country |
55-178894 |
Jun 1979 |
JP |
56-58253 |
May 1981 |
JP |
56-58254 |
May 1981 |
JP |
56-58255 |
May 1981 |
JP |
57-112066 |
Jul 1982 |
JP |
59-82761 |
May 1984 |
JP |
57-192478 |
Oct 1984 |
JP |
59-231351 |
Dec 1984 |
JP |
59-231851 |
Dec 1984 |
JP |
62-128168 |
Jun 1987 |
JP |
62-213273 |
Sep 1987 |
JP |
63-293967 |
Nov 1988 |
JP |
1-137666 |
May 1989 |
JP |
1-179449 |
Jul 1989 |
JP |
3-214670 |
Sep 1991 |
JP |
404357861 |
Dec 1992 |
JP |
5-291526 |
Nov 1993 |
JP |
5-167031 |
Jun 1995 |
JP |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09/077100 |
|
US |
Child |
10/206215 |
|
US |