SEMICONDUCTOR MEMORY DEVICE

Abstract

A memory cell has a heater element which generates heat by supplying electric current, a chalcogenide layer whose phase is changed by applying heat, and two transistors for driving the heater element. Bit lines extend in a predetermined direction and electrically connect with memory cells. Word lines extend at right angles to bit lines and electrically connect with memory cells. In a first cell row, memory cells are arranged at interval 2d along the bit lines. In a second row, memory cells are arranged such that the first cell row is shifted by distance d along the bit lines. First cell rows and second cell rows are alternately arranged at an interval e along the direction of word line so as to arrange the memory cells in a checker manner.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view illustrating a structure of a semiconductor memory device according to one example of the present invention. FIG. 1B is a sectional view along a 1B-1B line in FIG. 1A.

FIG. 2 is a figure schematically illustrating a layout of a memory cell contact in a semiconductor memory device according to one example of the present invention.

FIG. 3 is a block diagram illustrating a circuit structure of a semiconductor memory device according to an example of the present invention.

FIG. 4 is a figure illustrating an equivalent circuit in a unit cell.

FIG. 5 is a block diagram illustrating a structure of a word line driving circuit according to an example of the present invention.

FIG. 6 is a figure showing a list of logic levels of a signal output by a word line driving circuit according to an example of the present invention.

FIG. 7A is a plan view to explain a structure of a conventional phase-change memory (Related Art). FIG. 7B is a sectional view along a 7B-7B line in FIG. 7A.

Claims

1. A semiconductor memory device comprising: memory cells each having a heater element which generates heat by supplying an electric current and a variable resistor element whose phase is changed by heat;bit lines each extending in a predetermined direction and electrically connecting with the memory cells; andword lines each extending in a direction at right angles to the bit lines and electrically connecting with the memory cells;wherein the memory cells are arranged in a checker manner.

2. The semiconductor memory device according to claim 1, further comprising: first cell rows in which the memory cells are arranged at a predetermined interval 2d along the extending direction of the bit lines; andsecond cell rows in which the memory cells are arranged such that the first cell row is shifted by a distance d along the extending direction of the bit lines;wherein the first cell rows and the second cell rows are alternately arranged at a predetermined interval e along the extending direction of the word lines.

3. The semiconductor memory device according to claim 2, wherein the interval 2d is not less than the interval e.

4. The semiconductor memory device according to claim 2, wherein two or more word lines are arranged within the interval 2d.

5. The semiconductor memory device according to claim 2, wherein: the word lines comprise a first word line and a second word line;the first word line and second word line are arranged within the interval 2d; the memory cell disposed sandwiched between the first and second word lines is connected with the first and second word lines;writing into the memory cell is performed through both the first and second word lines; andreadout from the memory cell is performed through any one of the first and second word lines.

6. The semiconductor memory device according to claim 5, wherein: the memory cell further comprises a first switch element and a second switch element for switching power supply to the heater element;the first switch element comprises a first controlling terminal;the second switch element comprises a second controlling terminal;the first controlling terminal of the first switch element is connected with the first word line;the second controlling terminal of the second switch element is connected with the second word line; andthe power is supplied through the bit line.

7. The semiconductor memory device according to claim 5, further comprising a word line driver for driving the memory cells through the word lines; wherein the word line driver comprises a first decoder decoding one bit in a row address and column address to access the memory cell selectively and outputting a signal to select one of the first word lines and a second decoder decoding the row address and outputting a signal to select one of the second word lines when a writing signal is active.

8. The semiconductor memory device according to claim 6, further comprising a word line driver for driving the memory cells through the word lines; wherein the word line driver comprises a first decoder decoding one bit in a row address and column address to access the memory cell selectively and outputting a signal to select one of the first word lines and a second decoder decoding the row address and outputting a signal to select one of the second word lines when a writing signal is active.

9. The semiconductor memory device according to claim 7, wherein: when the row address is k which is 0 to 2n−1, n being an integer greater than 1, the numbers of the first word lines being 0 to 2n, respectively, the numbers of the second word lines being 0 to 2n−1, respectively,the first decoder outputs a selection signal to the first word line having any one of the numbers k and k+1 corresponding to 1 bit in the column address, andthe second decoder outputs a selection signal to the second word line having a number k.

10. The semiconductor memory device according to claim 8, wherein: when the row address is k which is 0 to 2n−1, n being an integer greater than 1, the numbers of the first word lines being 0 to 2n, respectively, the numbers of the second word lines being 0 to 2n−1, respectively,the first decoder outputs a selection signal to the first word line having any one of the numbers k and k+1 corresponding to 1 bit in the column address, andthe second decoder outputs a selection signal to the second word line having a number k.

11. A semiconductor memory device comprising: memory cells each having a heater element which generates heat by supplying an electric current and a variable resistor element whose phase is changed by heat;bit lines each extending in a predetermined direction and electrically connecting with the memory cells; andword lines each extending in a direction at right angles to the bit lines and electrically connecting with the memory cells;wherein the memory cells are arranged in a checker manner, said semiconductor memory device further comprising:first cell rows in which the memory cells are arranged at a predetermined interval 2d along the extending direction of the bit lines; andsecond cell rows in which the memory cells are arranged such that the first cell row is shifted by a distance d along the extending direction of the bit lines;wherein the first cell rows and the second cell rows are alternately arranged at a predetermined interval e along the extending direction of the word lines.

12. A semiconductor memory device comprising: memory cells each having a heater element which generates heat by supplying an electric current and a variable resistor element whose phase is changed by heat;bit lines each extending in a predetermined direction and electrically connecting with the memory cells; andword lines each extending in a direction at right angles to the bit lines and electrically connecting with the memory cells;wherein the memory cells are arranged in a checker manner,said semiconductor memory device further comprising:first cell rows in which the memory cells are arranged at a predetermined interval 2d along the extending direction of the bit lines; andsecond cell rows in which the memory cells are arranged such that the first cell row is shifted by a distance d along the extending direction of the bit lines;wherein the first cell rows and the second cell rows are alternately arranged at a predetermined interval e along the extending direction of the word lines, andwherein the interval 2d is not less than the interval e.