This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-092097, filed Mar. 29, 2006, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a capacitor.
2. Description of the Related Art
Higher integration of a semiconductor device has been accompanied by a progress in miniaturization of elements used for the semiconductor device. The miniaturization of the elements is achieved by reducing a minimum feature size of lithography.
However, current semiconductor devices are not enough to satisfy a demand for miniaturization. For example, as disclosed in Jpn. Pat. Appln, KOKAI Publication No. 2001-257320, in a semiconductor memory device such as a ferroelectric semiconductor memory device, a side face of a capacitor, which serves as an element device, is formed to be inclined. This structure is not suited to miniaturization since an effective area is smaller as compared with an amount of space occupied by the capacitor. A reason for forming such a structure is to prevent an etching problem that is formation of an etching byproduct on the side face of the capacitor when the side face of the capacitor is vertically etched. For example, if the etching byproduct is conductive, the structure allows preventing short-circuiting between upper and lower electrodes of the capacitor. Moreover, even if the side face of the capacitor can be etched to be vertical, its size is limited by the minimum feature size of lithography. Specifically, a capacitor area cannot be set smaller than L2, where L is a minimum feature size of lithography.
According to one aspect of the present invention, it is provided a semiconductor memory device comprising: a transistor including a gate electrode formed on a gate insulator on a semiconductor substrate and a plurality of sources/drains disposed in the semiconductor substrate to face each other holding the gate electrode therebetween; a ferroelectric capacitor formed above the transistor and including a lower electrode, a ferroelectric film, and an upper electrode; a first wiring line electrically connected to the lower electrode; and a second wiring line electrically connected to the upper electrode, wherein the ferroelectric capacitor is a staggered-electrode capacitor in which the upper electrode is shifted from the lower electrode and equivalently overlaps with parts of the plurality of lower electrodes.
According to another aspect of the present invention, it is provided a semiconductor memory device comprising: a plurality of transistors electrically connected in series, each transistor including a gate electrode formed on a gate insulator on a semiconductor substrate and a plurality of sources/drains disposed in the semiconductor substrate to face each other holding the gate electrode therebetween; a plurality of ferroelectric capacitors electrically connected to the transistors in parallel, each capacitor including a lower electrode, a ferroelectric film, and an upper electrode; a first wiring line connected to one end of the plurality of serially connected transistors; and a second wiring line connected to the other end of the plurality of serially connected transistors, wherein the ferroelectric capacitors are staggered-electrode capacitors in which the lower and upper electrodes are square, arranged to be shifted from and overlapped with each other, and equivalently shared with a plurality of ferroelectric capacitors, and a serial connection direction of the transistors is one of diagonal directions of the square lower and upper electrodes.
The embodiments of the present invention will be described with reference to the accompanying drawings. Throughout the drawings, corresponding portions are denoted by corresponding reference numerals. Each of the following embodiments is illustrated as one example, and therefore the present invention can be variously modified and implemented without departing from the spirits of the present invention.
As described above, by forming the staggered-electrode capacitor SC in which the upper and lower electrodes UE(46) and LE(42) of the ferroelectric capacitor 40 are arranged to be shifted, it can be provided a ferroelectric memory device 100 including the capacitor having an effective size smaller than the minimum feature size of lithography. As indicated by circle marks in the example of
To access only one desired capacitor of the semiconductor memory device 100 of the embodiment, each one upper electrode UE and one lower electrode LE must be selected. However, when they are selected by using a conventional planar type transistor, all capacitors connected to one word line are simultaneously selected. In other words, the plurality of capacitors sharing electrodes and connected to one word line substantially become one capacitor, thereby disabling achievement of the high density.
One of the methods of selecting only one capacitor is a method to use cross point transistors. Specifically, a first cross point transistor XTL connected with the lower electrode LE(42) and a second cross point transistor XTU connected with the upper electrode UE(46) are used. Where the cross point transistor XT includes two vertical type transistors VT1, VT2 connected serially, and respective word lines (gate electrodes) WL1, WL2 are arranged to be orthogonal to each other. In the cross point transistor XT, only when both transistors are turned ON the capacitor electrode connected thereto is selected. For details on the vertical transistors constituting the cross point transistor, refer to J. M. Hergenrother et al., “The vertical replacement-gate (VRG) MOSFET”, Solid-State Electronics 46, pp. 937-950, 2002.
A first wiring line M1 is disposed on the first interlevel insulator 18 formed to cover the transistor 10 on the semiconductor substrate 5. The first wiring line M1 serves as a common plate line.
The first cross point transistor XTL is disposed on the first wiring line M1. The first cross point transistor XTL includes serially connected first and second vertical transistors VT1 and VT2. The first vertical transistor VT1 is disposed to connect with the first wiring line M1, and includes a first source/drain 20, a first channel region 26, and a second source/drain 28. A first gate electrode WL1 is disposed on a first gate insulator 24-1 formed around the first channel region 26. The first gate electrode WL1 interconnects a plurality of first gate electrodes arranged in a horizontal direction to serve as a first word line.
The second vertical transistor VT2 is disposed on the first vertical transistor VT1. The second vertical transistor VT2 similarly includes the second source/drain 28, a second channel region 34, a third source/drain 36, a second gate insulator 32-1, and a second gate electrode WL2. The second gate electrode WL2 is disposed in a direction orthogonal to the first gate electrode WL1, and arranged to extend in a direction vertical to the paper surface. The second gate electrode WL2 serves as a second word line. The second source/drain 28 is shared with the first and second vertical transistors VT1 and VT2. The third source/drain 36 also serves as a contact plug to connect with the lower electrode 42 of the staggered-electrode capacitor SC formed thereon.
The staggered-electrode capacitor SC is disposed on the first cross point transistor XTL. The staggered-electrode capacitor SC includes a lower electrode 42, a ferroelectric film 44, and an upper electrode 46. It is presumed here that each of the lower and upper electrodes 42 and 46 is patterned in a square having its one side length set equal to a minimum feature size L of lithography. The lower electrode 42 is connected with the third source/drain 36 of the first cross point transistor XTL. The upper electrode 46 is formed to be shifted by nearly L/2 not only in the horizontal direction but also in the cross direction to the paper surface. One ferroelectric capacitor 40 is formed in each of overlapped parts of the lower and upper electrodes 42 and 46.
The second cross point transistor XTU is disposed on the staggered-electrode capacitor SC. The second cross point transistor XTU includes two serially connected vertical transistors VT3 and VT4. The vertical transistors VT3 and VT4 are similar to the vertical transistors VT1 and VT2, and thus description thereof will be omitted. A fourth source/drain 50 of the second cross point transistor XTU is connected with the upper electrode 46 of the staggered-electrode capacitor SC. Accordingly, the first and second cross point transistors XTL and XTU are arranged in positions shifted from each other by nearly L/2 in the horizontal and the cross directions of the paper surface.
A second wiring line M2 is disposed on the second cross point transistor XTU. The second wiring line M2 is connected with a sixth source/drain 66 to serve as a bit line. In this case, the first and second wiring lines M1 and M2 do not need to be formed in a line, but they can be formed in a plane. The wiring lines M1, M2 and the gate electrodes (word lines) WL1, WL2, WL3, and WL4 are connected with a third wiring line M3 through respective contact plugs VPx.
Among the four capacitors C1 to C4 on the lower electrode LE3, for example, the capacitor C1 is connected with the first cross point transistor XTL3 through the lower electrode LE3, and with the second cross point transistor XTU1 through the upper electrode UE1. Similarly, the capacitor C2 is connected with the second cross point transistor XTU2 through the upper electrode UE4, the capacitor C3 is connected with the second cross point transistor XTU3 through the upper electrode UE3, and the capacitor C4 is connected with the second cross point transistor XTU4 through the upper electrode UE4. Accordingly, for example, if the first cross point transistors XTL3 and the second cross point transistors XTU2 are selected, the capacitor C2 alone can be selected, and other capacitors are not selected.
Next, an example of a method of manufacturing the semiconductor memory device 100 shown in
(1) Referring to
(2) Next, the first cross point transistor XTL is formed on the first wiring line M1. First, a first semiconductor layer 20 is deposited on an entire surface to cover the first wiring line M1. For the first semiconductor layer 20, for example, n-type silicon doped with a high concentration of phosphorus (P) or arsenic (As) can be used, and it can be formed by CVD. The first semiconductor layer 20 is patterned by lithography and etching to form a first source/drain 20 connected with the first wiring line M1.
(3) A second interlevel insulator 22 is deposited on an entire surface to cover the first source/drain 20, and a surface of the second interlevel insulator 22 is planarized by, e.g., chemical mechanical polishing (CMP). In the planarization, the second interlevel insulator 22 is left thin on the first source/drain 20 to prevent exposure of the first source/drain 20. For the second interlevel insulator 22, for example, a SiO2 film formed by plasma CVD can be used.
(4) A conductive material which becomes a gate electrode is deposited on an entire surface of the second interlevel insulator 22, and patterned to form a first gate electrode WL1. For the conductive material, for example, aluminum, tungsten, or silicon doped with a high concentration of phosphorus or arsenic can be used. During the patterning, an opening is additionally formed nearly in a center position on the first source/drain 20 to pierce through the first gate electrode WL1. The opening is formed within the first gate electrode WL1 width to prevent cutting it.
(5) A third interlevel insulator 24 is deposited to cover the first gate electrode WL1 and to fill the opening, and a surface of the third interlevel insulator 24 is planarized by, e.g., CMP. In the planarization, the third interlevel insulator 24 is left thin on the first gate electrode WL1 to prevent exposure of the first gate electrode WL1. Then, a second opening which reaches the first source/drain 20 is formed in the opening by, e.g., reactive ion etching (RIE). In the etching, a third interlevel insulator 24-1 is left thin on the side face of the first gate electrode WL1. This third interlevel insulator 24-1 becomes a gate insulator of the first vertical transistor VT1.
(6) A second semiconductor layer 26 is formed to fill the second opening by, e.g., CVD. The second semiconductor layer 26 formed on the third interlevel insulator 24 is removed by, e.g., CMP. The second semiconductor layer 26 has conductivity different from that of the first semiconductor layer 20 and is p-type silicon doped with boron B, for example. In this way, a first channel region 26 of the first vertical transistor VT1 is formed.
(7) A third semiconductor layer 28 is formed on an entire surface to cover the third interlevel insulator 24 and the first channel region 26. For the third semiconductor layer 28, as in the case of the first semiconductor layer 20, for example, n-type silicon doped with a high concentration of phosphorus (P) or arsenic (As) can be used. The third semiconductor layer 28 is patterned to form a second source/drain 28 on the first channel region 26. Accordingly, the first vertical transistor VT1 of the structure shown in
(8) Referring to
Subsequently, a sixth interlevel insulator 38 is formed to cover the third source/drain 36, and the sixth interlevel insulator 38 is planarized by, e.g., CMP, using the third source/drain 36 as a stopper.
Accordingly, the first cross point transistor XTL that includes the first and second vertical transistors VT1, VT2 is formed.
(9) Next, the staggered-electrode capacitor SC is formed on the first cross point transistor XTL.
A lower electrode material 42 of a ferroelectric capacitor is deposited on an entire surface to cover the sixth interlevel insulator 38 and the third source/drain 36. For the lower electrode material, for example, titanium/aluminum nitride (TiAlN), strontium/ruthenium oxide (SrRuO3), or platinum (Pt) can be used. The lower electrode material 42 is patterned to form a lower electrode 42 (LE) to be connected with the third source/drain 36. A space between the lower electrodes 42 can be planarized by an interlevel insulator 43 such as a SiO2 film, if necessary.
(10) A ferroelectric film 44 and an upper electrode material 46 are sequentially deposited on the lower electrode 42. For the ferroelectric film 44, a metal oxide having a perovskite structure such as lead/zirconium titanate (PZT) or strontium/bismuth tantalite (SBT) can be used. For the upper electrode material 46, the same material as that of the lower electrode 42 can be used.
The upper electrode material 46 is patterned to form an upper electrode 46. As shown in
Then, a seventh interlevel insulator 48 is formed on an entire surface, and planarized by, e.g., CMP, to form the staggered-electrode capacitor SC shown in
(11) Referring to
The third vertical transistor VT3 includes a fourth source/drain 50 connected with the upper electrode 46 of the staggered-electrode capacitor SC, a third channel region 56, a fifth source/drain 58, and a third gate electrode WL3. The fourth vertical transistor VT4 includes the fifth source/drain 58, a fourth channel region 64, a sixth source/drain 66, and a fourth gate electrode WL4. The fifth source/drain 58 is shared with the third and fourth vertical transistors VT3, VT4. The sixth source/drain 66 also serves as a contact plug connected with a second wiring line M2 to be formed thereon. The third and fourth gate electrodes WL3 and WL4 are disposed in directions orthogonal to each other.
(12) The second wiring line M2 connected with the sixth source/drain 66 is formed on the second cross point transistor XTU. Since the second wiring line M2 serves as a common bit line, patterning it into a line pattern is not always necessary, and thus it can be formed in a plane pattern. An interlevel insulator 70 is deposited to cover the second wiring line M2, and planarized by, e.g., CMP. Contact plugs VPx each reaching one of the gate electrodes WL1 to WL4 or the wiring lines M1, M2 are formed in a plurality of interlevel insulators. Further, a third wiring line M3 to be connected with each contact plug VPx is formed on the interlevel insulator 70.
Thus, it can be formed the staggered-electrode capacitor SC which includes the cross point transistors XTL, XTU according to the embodiment shown in
In the case of the staggered-electrode capacitor of the embodiment, the four capacitors share one electrode. Accordingly, as a voltage is applied to the capacitors connected with the same electrode of the selected capacitor, it needs to pay attention to prevent inversely polarizing a ferroelectric film if the present invention is used in a ferroelectric memory device.
According to the embodiment, the staggered-electrode capacitor is formed by shifting the upper electrode from the lower electrode in the ferroelectric capacitor. By forming capacitors in the staggered-electrode capacitors, it can be formed a capacitor array having an effective size smaller than a size defined by a minimum feature size of lithography.
Hence, a semiconductor memory device that allows a higher packing density of capacitors can be provided.
(Modification 1)
The first embodiment is directed to the case of arranging the cross point transistors XTs above and below the capacitor as shown in
In
According to the Modification, a staggered-electrode capacitor SC that includes a lower electrode 42, a ferroelectric film 44, and an upper electrode 46 is formed on a first interlevel insulator 18. After the staggered-electrode capacitor SC is planarized by an interlevel insulator 48, a contact plug 80 to be connected with a center of the lower electrode 42 is disposed in the interlevel insulator 48 and the ferroelectric film 44. A first cross point transistor XTL connected with the lower electrode 42 is formed on the contact plug 80. The first cross point transistor XTL includes first and second vertical transistors VT1 and VT2. A first wiring line M1 (plate line) connected with a third source/drain 66a of the second vertical transistor VT2 is disposed on the first cross point transistor XTL. As in the case of the first embodiment, a second cross point transistor XTU that includes third and fourth vertical transistors VT3 and VT4 is formed on the upper electrode 46. A second wiring line M2 (bit line) connected with a sixth source/drain 66b of the fourth vertical transistor VT4 is disposed on the second cross point transistor XTU.
The first and third vertical transistors VT1 and VT3 are formed in the same first transistor layers 50, 56 and 58, and similarly the second and fourth vertical transistors VT2 and VT4 are formed in the same second transistor layers 58, 64 and 66. As shown in
A case in which no contact plug for connection to the upper electrode 46 is formed is shown. It should be understood, however, that contact plugs could be formed.
(Modification 2)
A semiconductor memory device 120 of Modification 2 of the first embodiment employs a structure in which a staggered-electrode capacitor SC is formed on first and second cross point transistors XTL, XTU, as shown in
In the semiconductor memory device 120 of the Modification, a process of forming the staggered-electrode capacitor SC on the first and second cross point transistors XTL, XTU is almost similar to that of the first embodiment. However, major differences are; (1) disposing first and second wiring lines M1, M2 on a first interlevel insulator 18, and (2) forming a contact plug 82 connecting the second cross point transistor XTU with an upper electrode 46 and piercing through a ferroelectric film 44 after forming the ferroelectric film 44 on a lower electrode 42.
A semiconductor memory device 200 according to a second embodiment of the present invention has a chain type memory cell comprising a staggered-electrode capacitor SC. An example of the semiconductor memory cell 200 of the embodiment will be described by referring to
In the chain type memory cell, a capacitor 40 and a MOS transistor 10 are electrically connected in parallel. For the capacitor 40, for example, a ferroelectric capacitor can be used. According to the embodiment, as shown in
The semiconductor memory device 200 that includes the staggered-electrode capacitor SC of the embodiment can be manufactured by a conventional manufacturing method. An example of the manufacturing method will be briefly described by referring to
A gate insulator 12 and a gate electrode material 14 are formed on a semiconductor substrate 5, e.g., a silicon substrate, and patterned into a gate electrode 14 by lithography and etching. Using the gate electrode 14 as a mask, for example, arsenic (As) is ion-implanted to the semiconductor substrate 5 to form a source/drain 16. Accordingly, the MOS transistor 10 is formed. The MOS transistor 10 is covered with a first interlevel insulator 18 to be planarized. A first contact plug 84 that reaches one source/drain 16a of the MOS transistor 10a is formed in the first interlevel insulator 18.
A lower electrode 42 of a staggered-electrode capacitor SC is formed on the first contact plug 84. As shown in
As described above, by forming the capacitor electrodes 42, 46 oblique to the chain direction of the memory cell by 45°, the first and second contact plugs 84, 86 can be arranged in the diagonal direction of the capacitor electrodes 42, 46. Thus, an area for forming the second contact plug 86 can be effectively increased by 21/2, and a margin for forming the second contact plug 86 can be increased.
Furthermore, according to the embodiment, by forming the staggered-electrode capacitor in which the upper electrode of the ferroelectric capacitor is formed by being shifted from the lower electrode, it can be formed a capacitor array having an effective size smaller than the minimum feature size of lithography. Thus, a semiconductor memory device that enables to achieve a higher packing density of a capacitor can be provided.
A semiconductor memory device according to a third embodiment of the present invention includes a ferroelectric capacitor having a hexagonal lower electrode and is a capacitor on bit line (COB) type semiconductor memory device. This structure enables to achieve a higher packing density of the semiconductor memory device. When hexagons are closely packed, each center thereof is shifted by a ½ pitch in both horizontal and longitudinal directions. The embodiment provides a structure suited to an operation in a 2 transistor-2 capacitor (2T-2C) mode. However, the device can also be operated in a 1 transistor-1 capacitor (1T-1T) mode.
The semiconductor memory device 300 of the embodiment includes a MOS transistor Tr(10), a ferroelectric capacitor C(40), a word line WL, a bit line BL, and a plate line PL. The ferroelectric capacitor 40 of the embodiment has a lower electrode 42 formed into a hexagonal planar shape, and is arranged to be closely packed. The MOS transistor 10 is formed on a semiconductor substrate 5. A gate electrode 14 of the MOS transistor 10 serves as a word line WL by interconnecting gate electrodes of a plurality of MOS transistors 10 arrayed in a longitudinal direction of
Next, an operation of the ferroelectric memory device 300 of the embodiment will be described.
A) 2T-2C Operation
Consideration will be given to a 2T-2C memory cell constituted of two transistors Tr[1], Tr[2] and two ferroelectric capacitors C[1], C[2], indicated by hatched lines in
Each of the ferroelectric capacitors C[1], C[2] has capacitance-voltage characteristics shown in
A case of writing from a state of nothing written in the ferroelectric capacitor (point 0 in
First, the word lines WL[1], WL[2] are set “High”, other word lines WLs are set “Low”, and all plate lines PLs other than the plate line PL[1] are set to floating.
1) When the BL[1] is set to 0 V, the BL[2] is set to 1.8 V, and the PL[1] is set to 0 V, a potential difference −1.8 V is applied to the C[2], and the C[2] is polarized in a negative direction (point A in
2) When the PL[1] is set to 1.8 V while the BL[1], BL[2] are kept at potentials as they are, a potential difference +1.8 V is applied to the C[1], and the C[1] is polarized in a positive direction (point C). At this potential, as a potential difference of the C[2] is 0 V, the C[2] holds polarization of the negative direction (point B).
3) In this state, all the potentials are set to 0 V (BL[1]=BL[2]=PL[1]=WL[1]=WL[2]=0 V). In other words, when power is turned OFF, the C[1] and the C[2] are written in opposite directions, i.e., the C[1] is written in the positive direction (point D) and the C[2] is written in the negative direction (point B).
Next, a case of reading will be described. For initial setting, as in the case of the writing, the WL[1], WL[2] are set “High”, the other WLs are set “Low”, and all the PLs other than the PL[1] are set to floating.
1) When the BL[1] and BL[2] are set to 0 V, and the PL[1] is set to 1.8 V, as a potential difference of the C[1] is +1.8 V, the C[1] is changed from the point D to the point C, but its positive polarized state is not changed. As a potential difference of the C[2] is +1.8 V, the C[2] is changed from the point B to the point C, and its polarized state is changed from negative to positive. As a result, a plenty of charges are discharged from the C[2]. This is detected by a sense amplifier (S/A) connected to the BL[1] and BL[2]. Thus, destructive reading is carried out.
2) Next, to restore the destroyed data, the BL[1] and BL[2] are returned to original states by a flip flop in the S/A, i.e., the BL[1] is returned to 0 V, and the BL[2] is returned to 1.8 V, and the PL[1] is returned to 0 V. Thus, as a potential difference of the C[2] becomes −1.8 V, the C[2] is changed from the point C to the point A to return to the initial polarized state of the negative direction. As a potential difference of the C[1] is 0 V, the C[1] returns to the point D, but the polarized state is not changed from positive. In other words, rewriting is carried out.
In both of the writing and reading cases, the WL[1] and WL[2] operate in the same manner. In other words, they can be made common, and its example will be described later in Modification 3.
B) 1T-1C Operation
When the ferroelectric semiconductor device shown in
In the case of the 1T-1C operation, consideration is given to a memory cell constituted of a transistor Tr[1] and a ferroelectric capacitor C[1] indicated by hatched lines in
To read data, in place of comparing the ferroelectric capacitors C[1] and C[2] with each other in the 2T-2C mode, the ferroelectric capacitor C[1] and a dummy capacitor DC[2] connected to the bit line BL[2] are compared. In this case, all the transistors connected to the bit line BL[2] must be turned OFF. Amount of charges discharged from the ferroelectric capacitor C[1] and the dummy capacitor DC[2] are detected by the sensor amplifier (S/A) to read the data.
As described above, according to the embodiment, the lower electrode of the ferroelectric capacitor is formed to be hexagonal and arranged to be closely packed, and the staggered-electrode capacitor is formed by shifting the upper electrode from the lower electrode, whereby the capacitor array having an effective size smaller than the minimum feature size of lithography can be formed. Hence, it can be provided a semiconductor memory device capable of achieving a higher packing density of the capacitors.
Various modifications and changes can be made to the embodiment. Some examples will be described below.
(Modification 3)
The semiconductor memory device of the Modification allows the 2T-2C operation. However, even if a 1T-1C operation is being carried out, transistors Tr[1] and Tr[2] connected to a pair of bit lines BL[1] and BL[2] are simultaneously turned ON, thereby enabling the 1T-1C operation.
(Modification 4)
As described above, according to the present invention, the staggered-electrode capacitor is formed by shifting the upper electrode from the lower electrode of the ferroelectric capacitor, whereby the capacitor array having an effective size smaller than a minimum feature size of lithography can be formed. Thus, it can be provided a semiconductor memory device capable of achieving a higher packing density of the capacitor.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Number | Date | Country | Kind |
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2006-092097 | Mar 2006 | JP | national |