Patent Application
20200152554
This Utility patent application claims priority to German Patent Application No. 10 2018 128 109.9, filed Nov. 9, 2018, which is incorporated herein by reference.
The present disclosure relates to a clip, a semiconductor package, and a method for fabricating a semiconductor package.
A typical semiconductor package may include various components such as a leadframe, a semiconductor die, a clip, a heatsink, different types of bonds, and an encapsulant. Very often these and other components are coupled together using solder or a similar viscous substance. The soldering process may be performed by application of a specific solder material in the form of, for example, a solder paste to one or more functional interfaces of the components to be connected, and performing soldering, in particular by a reflow process and subsequent cooling and thereby transforming the solder material into a solid and connecting the components together.
The accompanying drawings are included to provide a further understanding of aspects and are incorporated in and constitute a part of this specification. The drawings illustrate aspects and together with the description serve to explain principles of aspects. Other aspects and many of the intended advantages of aspects will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference signs may designate corresponding similar parts.
A first aspect of the present disclosure relates to a clip. The clip comprises a die attach portion comprising a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and comprising a curved transition from an inner wall of the at least one through-hole to the first main face.
It has turned out that in soldering processes as those described above, it may happen that voids are created in the solder material during the reflow process. If such voids would remain in the finished solder layer, they could have a potentially harmful influence on the mechanical and electrical performance of the chip-to-clip or chip-to-leadframe connection. Therefore efforts should be made to remove these voids during the reflow process. As will be shown in more detail later, the through-hole formed in the die attach portion, fulfils the function of an escape channel for voids. Moreover it can be shown that the curved edge allows the voids to more easily and more smoothly move into the through-hole and along an outer contour of the clip. In contrast thereto, sharp edges would act as barriers for the voids due to capillary forces. The curved edge serves to reduce such capillary forces.
According to an embodiment of the clip of the first aspect, the cross section of the curved transition comprises a circular arc segment comprising a non-zero radius R. According to further embodiment thereof the non-zero radius R is in a range from 0.05 mm to 0.5 mm, more specifically from 0.1 mm to 0.4 mm, more specifically from 0.2 mm to 0.3 mm. Alternatively, the cross section of the curved transition may follow any other first or higher order continuously differentiable shape such as a parabola or a spline curve or a chamfer with variable chamfer angle.
According to an embodiment of the clip of the first aspect, the curved edge is formed by an etching process. For example, by etching an originally sharp edge can be transformed into a curved edge. The etching parameters can be selected such that a desired radius R of the curved transition will be obtained. Alternatively, the curved edge may be manufactured by a punching or a coining process.
According to an embodiment of the clip of the first aspect, at least one through-hole comprises the form of at least one elongated slot. According to a further embodiment thereof the at least one through-hole comprises the form of two parallel elongated slots. Also other forms of one or more slots are possible as, for example, non-parallel slots, one or more crossed forms, one or more circles, one or more S-like forms or other curved forms.
According to an embodiment of the clip of the first aspect, the clip comprises a base body comprising Cu, a Cu alloy, or a compound material comprising Cu and at last one further metal. According to a further embodiment thereof, a layer is disposed on a main face of the base body, wherein the layer is comprised of another metallic material than the material of the base body. According to a further embodiment thereof the material of the layer comprises Ni or Ag or respective alloys thereof.
According to an embodiment of the clip of the first aspect, the clip comprises a composite material stack, combining conductive and non-conductive materials.
According to an embodiment of the clip of the first aspect, the clip comprises a thickness in a range from 100 μm to 2 mm. The thickness of the clip is defined as the distance between the two main surfaces of the clip.
According to an embodiment of the clip of the first aspect, a minimum lateral dimension of the through-hole is in the order of the thickness of the clip. For example, in case of a slot the minimum lateral dimension corresponds to the width of the slot which can be in the order of the thickness of the clip or greater.
A second aspect of the present disclosure relates to a clip comprising a die attach portion comprising a first main face, a second main face opposite to the first main face, side faces extending between the first and second main faces, and a curved transition from a side face to the first main face.
According to further embodiments of the clip of the second aspect, the clip and in particular the curved transition may be formed according to any one of the embodiments as described above in connection with a clip of the first aspect.
A third aspect of the present disclosure relates to a semiconductor package. The semiconductor package comprises a die pad, a semiconductor die comprising a first main face and a second main face opposite to the first main face, the semiconductor die being attached with its first main face to the die pad by means of a first solder layer, and a clip comprising a die attach portion comprising a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and comprising a curved transition from an inner wall of the at least one through-hole to the first main face, or a clip comprising a die attach portion comprising a first main face, a second main face opposite to the first main face, side faces extending between the first and second main faces, and a curved transition from a side face to the first main face, wherein the clip is attached with the first main face of the die attach portion to the semiconductor die by means of a second solder layer, and an encapsulation layer component the semiconductor die and the die attach portion of the clip.
According to further embodiments of the semiconductor package of the third aspect, the clip may be formed according to any one of the embodiments as described above in connection with a clip of the first or second aspects.
According to a further embodiment of the semiconductor package of the third aspect, in case of a clip having a through-hole, at least one through-hole is at least partly filled with material of the second solder layer. According to an embodiment thereof, the through-hole is only partly filled with the solder material. Furthermore it may be that it is filled with the solder material in such a way that due to capillary forces the filling level is higher at the inner wall of the through-hole than in the center. As a result the surface of the filled in solder material may comprise a parabolic form in a lateral cross-section.
A forth aspect of the present disclosure relates to a method for fabricating a semiconductor package. The method comprises providing a die pad, providing a semiconductor die comprising a first main face and a second main face opposite to the first main face, attaching the semiconductor die with its first main face to the die pad by means of a first solder layer, providing a clip comprising a die attach portion comprising a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and comprising a curved transition from an inner wall of the through-hole to the first main face or a clip comprising a die attach portion comprising a first main face, a second main face opposite to the first main face, side faces extending between the first and second main faces, and a curved transition from a side face to the first main face, attaching the clip with the first main face of the die attach portion to the semiconductor die by means of a second solder layer, and encapsulating the semiconductor die and the die attach portion of the clip with an encapsulation layer.
According to an embodiment of the method of the forth aspect, attaching the clip to the semiconductor die comprises applying a solder material on one or more of the first main face of the die attach portion of the clip and the first main face of the semiconductor die, and performing a solder process so that the solder material is transformed into the second solder layer. According to a further embodiment thereof, applying the solder material comprises dispensing the solder material.
According to an embodiment of the method of the forth aspect the solder material comprises a solder paste containing a flux material. Alternatively, the solder material may also comprise a flux-free solder paste. In general, it should be mentioned at this point that the method according to the third aspect can in principle be carried out with every kinds of solder materials.
According to an embodiment of the method of the third aspect providing the clip comprises fabricating the at least one through-hole by etching.
In the following detailed description, reference is made to the accompanying drawings, in which are shown by way of illustration specific aspects in which the disclosure may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, etc., may be used with reference to the orientation of the figures being described. Since components of described devices may be positioned in a number of different orientations, the directional terminology may be used for purposes of illustration and is in no way limiting. Other aspects may be utilized and structural or logical changes may be made without departing from the concept of the present disclosure. Hence, the following detailed description is not to be taken in a limiting sense, and the concept of the present disclosure is defined by the appended claims.
In addition, while a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application, unless specifically noted otherwise or unless technically restricted. Furthermore, to the extent that the terms “include”, “have”, “with” or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprise”. The terms “coupled” and “connected”, along with derivatives thereof may be used. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other; intervening elements or layers may be provided between the “bonded”, “attached”, or “connected” elements. Also, the term “exemplary” is merely meant as an example, rather than the best or optimal.
The examples of a semiconductor package and a method for fabricating a semiconductor package may use various types of semiconductor dies or circuits incorporated in the semiconductor dies, among them power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, analogue integrated circuits, power integrated circuits, chips with integrated passives, etc. The examples may also use semiconductor dies comprising MOS transistor structures or vertical transistor structures like, for example, IGBT (Insulated Gate Bipolar Transistor) structures or, in general, transistor structures in which at least one electrical contact pad is arranged on a first main face of the semiconductor die and at least one other electrical contact pad is arranged on a second main face of the semiconductor die opposite to the first main face of the semiconductor die. Moreover, the examples of insulation materials may, for example, be used for providing insulation layers in various types of enclosures and insulation for electrical circuits and components, and/or for providing insulation layers in various types of semi-conductor dies or circuits incorporated in semiconductor dies, including the above mentioned semiconductor dies and circuits.
The semiconductor die(s) of the semiconductor package can be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, GaN, or from any other semiconductor material, and, furthermore, may contain one or more of inorganic and organic materials that are not semiconductors, such as for example insulators, plastics or metals.
The semiconductor die(s) considered herein may be thin, in particular thinner than 100 μm, 50 μm, 20 μm, or 10 μm. In order to allow handling or manipulation of the semiconductor die, e.g. handling/manipulation required for packaging, or semiconductor device assembly, the semiconductor chip may form part of a composite chip. A composite chip may comprise the semiconductor chip and a reinforcing chip secured to the semiconductor chip. The reinforcing chip adds stability and/or strength to the composite chip to make it manageable.
The semiconductor die(s) may have contact pads (or electrodes) which allow electrical contact to be made with the integrated circuits included in the semiconductor chip(s). The electrodes may be arranged all at only one main face(s) of the semiconductor chip(s) or at both main faces of the semiconductor chip(s). They may include one or more electrode metal layers which are applied to the semiconductor material of the semiconductor chip(s). The electrode metal layers may be manufactured with any desired geometric shape and any desired material composition. For example, they may comprise or be made of a material selected of the group of Cu, Ni, NiSn, Au, Ag, Pt, Pd, an alloy of one or more of these metals, an electrically conducting organic material, or an electrically conducting semiconductor material.
The semiconductor package may comprise an encapsulation material forming an encapsulation body which encapsulates the clip and the semiconductor die. The encapsulation material may be electrically insulating. The encapsulation material may comprise or be made of any appropriate ceramic, plastic or polymer material such as, e.g., a duroplastic, thermoplastic or thermosetting material or laminate (prepreg), and may e.g. contain filler materials. Various techniques may be employed to encapsulate the semiconductor chip(s) with the encapsulation material, for example compression molding, injection molding, powder molding, liquid molding or lamination. Heat and/or pressure may be used to apply the encapsulation material.
In several examples layers or layer stacks are applied to one another or materials are applied or deposited onto layers. It should be appreciated that any such terms as “applied” or “deposited” are meant to cover literally all kinds and techniques of applying layers onto each other. In particular, they are meant to cover techniques in which layers are applied at once as a whole like, for example, laminating techniques as well as techniques in which layers are deposited in a sequential manner like, for example, sputtering, plating, molding, CVD, etc.
The first main face 1C of the clip 10 is the one onto which a semiconductor die has to be attached by means of a solder material and a reflow process turning the solder material into a solder layer. During the reflow process undesirable voids can be formed which are schematically represented as spheres of different size in
As further indicated by the wide arrows, the voids flow upwards through the solder material and pass out of the solder material into the interior of the reflow oven. The reflow process can be carried out at normal pressure in the reflow oven, hence a vacuum is not required. However, it is also possible to arrange for an at least reduced pressure or even a (moderate) vacuum inside the reflow oven which would then further assist in the extraction of the voids.
The solder material can in principle be any conventional solder material. In particular, the solder material can be a paste-based solder or a wire based solder. Besides that, the solder material may be based on or contain one or more of the following elements or compounds: Pb, Sn, Ag, PbSn, SnAg. The solder material can also be Pb free. Besides the above, the solder material may or may not contain a flux or any other similar auxiliary agent.
As shown in
It should be mentioned that the first aspect of the present disclosure is not necessarily restricted to a clip, but could also be realized in other types of contact elements like, for example, a leadframe, a lead of a leadframe, a heatsink (e.g. exposed heatsink soldered on top of a clip) or a die pad.
The curved transition 11E may be configured in the same way as the curved transition 1B of the clip 10 as shown in
It should further be mentioned that the two embodiments of clips 10 and 20 as shown in
Accordingly the clip 10 comprises a die attach portion 1 comprising a first main face and a second main face opposite to the first main face, and two slots 1A extending between the first and second main faces and comprising a curved transition from an inner wall to the first main face. The clip 10 is attached with the first main face of the die attach portion 1 to the semiconductor die 20 by means of a second solder layer 15.
The semiconductor package 100 further comprises an encapsulation 40 encapsulating the semiconductor die 20 and the die attach portion 1 of the clip 10. The encapsulation 40 may comprise any one of the materials as were listed above, in particular a resin like, for example, an epoxy resin.
It should be noted that the semiconductor package could also be configured such that it comprises a clip 20 as was shown in
The method 200 of
The method of
The first and second solder layers 15 and 25 can be equal, similar or different, i.e. they can be based on equal, similar, or different elements or compounds.
Attaching the semiconductor die to the die pad can be performed by applying, in particular dispensing, a first solder material, in particular a first solder paste, to one or both of the semiconductor die and the die pad and thereafter disposing the semiconductor die onto the die pad with the first solder material between them. Thereafter a second solder material, in particular a second solder paste, can be applied, in particular dispensed, to one or both of the semiconductor die and the clip and thereafter the clip is disposed onto the semiconductor die with the second solder material between them. Thereafter the resulting stack is placed in a reflow oven in which a reflow process is carried out followed by a cooling step. As a result, the first and second solder materials are transformed into first and second solder layers and the semiconductor die is permanently attached to the die pad and the clip is attached to the semiconductor die. It is also possible that another solder process than a reflow process is carried out.
Although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based at least in part upon a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations and is limited only by the concept of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2018 128 109.9 | Nov 2018 | DE | national |
