Patent Application
20230197585
The instant application relates to semiconductor devices, and in particular relates to methods of forming semiconductor packages and corresponding semiconductor package configurations.
High-voltage semiconductor devices such as MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), diodes, etc., are commonly packaged in a molded semiconductor package that includes several leads protruding out an encapsulant body. These types of semiconductor packages are commonly used in high power applications such as automotive, power transmission, HVAC, etc. Product performance requirements for high voltage applications, such as low electrical resistance, low parasitic inductance, low parasitic capacitive coupling, etc. demand innovative solutions. In particular, conventional interconnect techniques for electrically connecting semiconductor dies to one another and/or to package leads are ill-equipped to meet modern performance requirements with a small package footprint. For instance, although the electrical resistance of bond wires can be favorably improved by increasing the diameter of the wires, this creates practical challenges in the assembly process and increases the size of the package.
Thus, there is a need for an improved low parasitic package for semiconductor devices.
A method of forming a packaged semiconductor device is disclosed. According to an embodiment, the method comprises providing a lead frame comprising a die pad and a plurality of leads, providing a first semiconductor die that comprises a first load terminal disposed on a main surface of the first semiconductor die, providing a second semiconductor die that comprises a plurality of I/O terminals disposed on a main surface of the second semiconductor die, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies each face away from the die pad, forming an encapsulant body of electrically insulating mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals from the second semiconductor die to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.
Separately or in combination, the encapsulant body is formed to expose interior surface portions of the leads at the upper surface of the encapsulant body, wherein the conductive tracks are formed to contact the interior surface portions of the leads from the first group of the leads, and wherein the metal pad is formed to contact the interior surface portion of the second lead.
Separately or in combination, the encapsulant body is formed to comprise a depression in the upper surface of the encapsulant body, and the exposed interior surface portions of the leads protrude out from a first sidewall of the depression.
Separately or in combination, the method further comprises forming vertical interconnect elements on the I/O terminals of the second semiconductor die before forming the encapsulant body, wherein the encapsulant body is formed to expose upper ends of the vertical interconnect elements that are disposed on the I/O terminals at the upper surface of the encapsulant body, and wherein the conductive tracks are formed to contact the exposed upper ends of the vertical interconnect elements that are disposed on the I/O terminals.
Separately or in combination, forming either one of the plurality of conductive tracks and the metal pad comprises any one or more of laser assisted metal deposition, inkjet metal printing, electroplating, and electroless plating.
Separately or in combination, the method further comprises forming vertical interconnect elements on the first load terminal of the first semiconductor die before forming encapsulant body, and wherein the encapsulant body is formed to expose upper ends of the vertical interconnect elements on the first load terminal at the upper surface of the encapsulant body.
Separately or in combination, the metal pad is formed on the upper surface of the encapsulant body so as to contact the exposed upper ends of the vertical interconnect elements on the first load terminal.
Separately or in combination, the method further comprises forming an opening in the upper surface of the encapsulant body that exposes the first load terminal of the first semiconductor die, and wherein forming the opening comprises using the exposed upper ends of the vertical interconnect elements on the first load terminal to identify a location of the first load terminal underneath the encapsulant body.
Separately or in combination, the method further comprises forming a ribbon on the first load terminal of the first semiconductor die before forming encapsulant body, wherein the encapsulant body is formed to expose apex points of the ribbon at the upper surface of the encapsulant body, and wherein the metal pad is formed on the exposed apex points of the ribbon
Separately or in combination, the method further comprises forming a solder mask over the conductive tracks.
Separately or in combination, the method further comprises forming a layer of electrically insulating and thermally conductive material that covers the metal pad.
Separately or in combination, the encapsulant body is formed to directly expose the first load terminal and the I/O terminals at the first surface of the encapsulant body.
Separately or in combination, the first semiconductor die is a power transistor die that comprises a gate terminal disposed on the main surface of the first semiconductor die, the second semiconductor die is a logic die, and the method further comprises forming a second conductive track on the upper surface of the encapsulant body that electrically connects one of the I/O terminals from the second semiconductor die to the gate terminal of the first semiconductor die.
Separately or in combination, the first semiconductor die comprises a second load terminal that is disposed on a rear surface of the first semiconductor die, wherein the second load terminal of the first semiconductor die faces and electrically connects with the die pad.
According to another embodiment, the method comprises providing a lead frame comprising a die pad and a plurality of leads, providing a first semiconductor die that comprises a first load terminal and a plurality of I/O terminals disposed on a main surface of the first semiconductor die, providing a second semiconductor die that comprises a first load terminal and a gate terminal disposed on a main surface of the second semiconductor die, mounting the first semiconductor die directly on the lead frame such that the main surface of the first semiconductor die faces away from the lead frame, mounting the second semiconductor die on the first semiconductor die such that the main surface of the second semiconductor die faces away from the lead frame, forming an encapsulant body of electrically insulating mold compound that encapsulates the first and second semiconductor dies, forming a plurality of first conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals from the first semiconductor die to a first group of the leads, forming a second conductive track on the upper surface of the encapsulant body that electrically connects one of the I/O terminals from the first semiconductor die to the gate terminal of the second semiconductor die, forming a first metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal of the first semiconductor die to a second lead, and forming a second metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal of the second semiconductor die to a third lead.
Separately or in combination, the first semiconductor die comprises a power transistor device block and a logic block monolithically integrated in the first semiconductor die, wherein the second transistor die comprises a power transistor device, wherein the power transistor device block of the first semiconductor die and the power transistor device of the second semiconductor die form a half-bridge circuit, and wherein the logic block of the first semiconductor die forms a driver circuit that is configured to control a switching operation of the half-bridge circuit.
Separately or in combination, the method further comprises providing a third semiconductor die that comprises a first load terminal and a plurality of I/O terminals disposed on a main surface of the third semiconductor die, providing a fourth semiconductor die that comprises a first load terminal and a gate terminal disposed on a main surface of the fourth semiconductor die, mounting the third semiconductor die directly on the lead frame such that the main surface of the third semiconductor die faces away from the lead frame, and mounting the fourth semiconductor die on the third semiconductor die such that the main surface of the fourth semiconductor die faces away from the lead frame, wherein the third semiconductor die comprises a power transistor device block and a logic block monolithically integrated in the third semiconductor die, wherein the fourth transistor die comprises a power transistor device, wherein the power transistor device block of the third semiconductor die and the power transistor device of the fourth semiconductor die form a second half-bridge circuit, and wherein the logic block of the third semiconductor die forms a driver circuit that is configured to control a switching operation of the second half-bridge circuit.
A packaged semiconductor device is disclosed. According to an embodiment, the packaged semiconductor device comprises a lead frame comprising a die pad and a plurality of leads, a first semiconductor die that comprises a first load terminal disposed on a main surface of the first semiconductor die that faces away from the die pad, a second semiconductor die that comprises a plurality of I/O terminals disposed on a main surface of the second semiconductor die that faces away from the die pad, an encapsulant body of electrically insulating mold compound that encapsulates the first and second semiconductor dies, a plurality of conductive tracks that are formed on an upper surface of the encapsulant body and electrically connect at least some of the I/O terminals from the second semiconductor die to a first group the leads, and a metal pad formed on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.
Separately or in combination, interior surface portions of the leads are exposed at the upper surface of the encapsulant body, and wherein the metal pad and the conductive tracks contact the exposed interior surface portions of the leads.
Separately or in combination, the encapsulant body comprises a depression in the upper surface of the encapsulant body, and wherein the exposed interior surface portions of the leads protrude out from a first outer sidewall of the depression.
Separately or in combination, the depression is spaced apart from an outer edge side of the encapsulant body by a thicker portion of the of the encapsulant body, and wherein upper surfaces of the leads are covered by encapsulant material in the thicker portion.
Separately or in combination, the depression comprises a second sidewall that is opposite from the first sidewall and a bottom surface, and wherein the metal pad completely fills a region between the first and second sidewalls of the depression.
Separately or in combination, the first semiconductor die is a power transistor die that comprises a gate terminal disposed on the main surface of the first semiconductor die, the second semiconductor die is a logic die, and wherein the semiconductor package further comprises a second plurality of conductive tracks on the upper surface of the encapsulant body that electrically connect at least one of the I/O terminals from the second semiconductor die to the gate terminal of the second semiconductor die.
Separately or in combination, the first semiconductor die is mounted on top of the second semiconductor die, and wherein the second semiconductor die is mounted directly on the die pad.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
Various embodiments of a method of forming a packaged semiconductor device and a corresponding packaged semiconductor device are described herein. The packaged semiconductor device is formed by mounting first and second semiconductor dies on a die pad. The I/O terminals from the second semiconductor die are electrically connected to package leads by conductive tracks that are formed in an upper surface of the encapsulant body. A load terminal from the second semiconductor die is connected to one or more of the package leads by a metal pad that is also formed in an upper surface of the encapsulant body. The conductive tracks provide high density ad high performance electrical interconnect. Meanwhile, the metal pad provides a low electrical resistance connection, which may be a power connection such as a source or drain connection to a power transistor die. Advantageously, the conductive tracks and the metal pad can be formed by metal structuring techniques at minimal expense. According to one embodiment, the encapsulant body of the package is formed to comprise a depression that exposes interior surface portions of the leads, wherein thicker parts of the encapsulant body outside of the depression cover and retain the package leads. The conductive tracks and/or the metal pad can be directly formed and structured within the depression. A protective structure such as a solder resist layer and/or layer of thermal interface material may be arranged in the depression over the conductive tracks and/or the metal pad.
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A first semiconductor die 104 and a second semiconductor die 106 are provided and are mounted on the die pad 100. The first and second semiconductor dies 104, 106 may be singulated from a semiconductor wafer (not shown), e.g. by sawing, prior to being mounting on the metal lead frame. In general, the semiconductor wafer and therefore the resulting semiconductor die may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, but are not limited to, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), etc.
Generally speaking, each of the first and second semiconductor dies 104, 106 may have any device configuration. Examples of these device configurations include discrete device configurations, e.g., diodes, transistor, thyristors, etc., and integrated device configurations, e.g., logic devices, application specific integrated circuits (ASICs), ASSPs (application specific standard products), controllers, etc. At least one of the first and second semiconductor dies 104, 106 may be vertical devices, meaning that the device is configured to conduct current in a direction perpendicular to the main and rear surfaces of the respective semiconductor die. At least one of the first and second semiconductor dies 104, 106 may be a lateral device, meaning that the device is configured to conduct current in a direction parallel to a main surface of the respective semiconductor die.
The first and second semiconductor dies 104, 106 are each mounted on the die pad 100. In the mounted position, the main surfaces of the first and second semiconductor dies 104, 106 face away from the die pad 100 and the rear surfaces of the first and second semiconductor dies 104, 106 face the die pad 100. An adhesive such solder, sinter, glue, etc., may be provided between the rear surfaces of the first and second semiconductor dies 104, 106 and the die pad 100 to effectuate the mounting. In the case of a vertical device, the adhesive may form a conductive connection between the rear surfaces of the first and second semiconductor dies 104, 106 and the die pad 100.
According to an embodiment, the first semiconductor die 104 comprises a power semiconductor device. Examples of power semiconductor devices include power MISFETs (Metal Insulator Semiconductor Field Effect Transistors) power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), HEMTs (High Electron Mobility Transistors), power bipolar transistors or power diodes such as, e.g., PIN diodes or Schottky diodes, etc. In one particular embodiment, the first semiconductor die 104 comprises a vertical power transistor, e.g., MOSFET IGBT, etc., that is rated to block voltages on the order of 100 V (volts), 600 V, 1200 V or more.
According to an embodiment, the second semiconductor die 106 comprises a logic device, Examples of logic device includes CMOS (complimentary metal oxide semiconductor) based ASIC (application specific integrated circuit) devices and ASSPs (application specific standard products). In one particular embodiment, the second semiconductor die 106 comprises a driver circuit that is configured to control a switching operation the first semiconductor die 104, e.g., in the case that the first semiconductor die 104 comprises a power transistor.
The first semiconductor die 104 comprises a first load terminal 108 disposed on the main surface of the first semiconductor die 104. The first load terminal 108 may be a voltage blocking terminal of the device, e.g., source, drain, emitter, collector, etc. The first semiconductor die 104 comprises a second load terminal (not shown), which corresponds to an opposite voltage blocking terminal of the device, e.g., source, drain, emitter, collector, etc., from the first load terminal. In the case of a vertical device configuration (as shown), the second load terminal may be disposed on a rear surface of the first semiconductor die 104, and may face and electrically connect with the die pad 100, e.g., by a conductive adhesive such as solder or sinter. In this case, the die pad 100 is configured to provide a power supply voltage to the first semiconductor die 104. In the case of a lateral device configuration, the second load terminal of the first semiconductor die 104 may be disposed on the main surface of the first semiconductor die 104. The first semiconductor die 104 may further comprise one or more gate terminals 110 disposed on the main surface of the first semiconductor die 104, e.g., in the case of a transistor device. In a commonly known manner, the gate terminal 110 may control a conductive connection between the first load terminal 108 and the second load terminal of the first semiconductor die 104.
The second semiconductor die 106 comprises a plurality of I/O (input/output) terminals 112 disposed on a main surface of the second semiconductor die 106. The I/O terminals 112 refer to the terminals that receive or provide signals that modulate during operation, such as digital logic signals. In the case that the second semiconductor die 106 is a logic die, the I/O terminals 112 can comprise an input terminal that receives an input signal for switching a semiconductor die, and an output terminal that is configured to provide a switching signal, e.g., a PWM (pulse width modulation) to the gate terminal 110 of the second semiconductor die 106. The second semiconductor die 106 may additionally comprise sensors, e.g., temperature sensors, short circuit sensors, etc., configured to monitor the operation of the first semiconductor die 108 and to protect the first semiconductor die 108 in the event of a hazardous condition. The second semiconductor die 106 may additionally comprise power supply terminals 114 that are disposed on the main surface of the second semiconductor die 106. The power supply terminals 114 receive a fixed voltage such as a positive voltage and a reference potential. Thus, in the case that the die pad 100 is configured to provide a power supply voltage to the first semiconductor die 104, the second semiconductor die 106 can be powered independently via the power supply terminals 114. In yet another embodiment, the second semiconductor die 106 may comprise a power semiconductor device, e.g., a power transistor, and a logic portion comprising driver circuitry monolithically integrated therein. In that case, the power semiconductor device of the second semiconductor die 106 may comprise a rear surface terminal that is electrically connected to the die pad 100 in a similar manner as described above.
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Generally speaking, the encapsulant body 118 can comprise any electrically insulating material that is suitable for semiconductor packaging. Examples of these materials include mold compound, epoxy, thermosetting plastic, polymer, resin, fiber and glass woven fiber materials, etc. According to an embodiment, the encapsulant body 118 comprises a laser-activatable mold compound. A laser-activatable mold compound refers to a mold compound that includes metal ions, e.g., Cu, Ni, Ag, etc. These metal ions are activated by a focused laser beam applied to the mold compound, which creates an active metal at the surface of the mold compound for a subsequent plating process, such as electroless plating or electroplating technique. In addition to the additive metal ions, a laser-activatable mold compound includes a polymer material as a base material. Examples of these polymers include thermoset polymers having a resin base, ABS (acrylonitrile butadiene styrene), PC/ABS (polycarbonate/acrylonitrile butadiene styrene), PC (polycarbonate), PA/PPA (polyimide/polyphthalamide), PBT (polybutylene terephthalate), COP (cyclic olefin polymer), PPE (polyphenyl ether), LCP (liquid-crystal polymer), PEI (polyethylenimine or polyaziridine), PEEK (polyether ether ketone), PPS (polyphenylene sulfide), etc.
The encapsulant body 118 is formed such that upper ends of the of the vertical interconnect elements 116 are exposed at an upper surface 120 of the encapsulant body 118 that is opposite from the die pad 100. Additionally, the encapsulant body 118 is formed such that interior surface portions 122 of the leads 102 are exposed at the upper surface 120 of the encapsulant body 118. The interior surface portions 122 of the leads 102 refer to those surfaces of the leads 102 which extend to an inner end of the leads 102 which faces the die pad 100, and may include an upper surface of the leads 102 that extends away from the die pad 100, and a side surface of the leads 102 that faces the die pad 100. This arrangement provides the benefit of making the later metal pad 134 and/or conductive traces 130 easily connected to the respective dies and the leads, and after the later step of applying protective structure 140 on top of the encapsulant body 124, the metal pad 108 and the conductive traces 130 are hidden and protected within the final semiconductor package.
According to the depicted embodiment, the encapsulant body 118 is formed to comprise a depression 124 in the upper surface 120 of the encapsulant body 118. The depression 124 comprises first and second sidewalls 126, 128 that are opposite from one another and a bottom surface 128 that extends between the first and second sidewalls 126, 128. The exposed interior surface portions 122 of the leads 102 may protrude out from one or both of the first and second sidewalls 126, 128.
The depression 124 can be formed in a variety of different ways. According to one technique, the encapsulant body 118 is initially formed to have a substantially cubic shape and/or a substantially planar upper surface 120, and the depression 124 is formed by subsequently removing the encapsulant material from the upper surface 120 of the encapsulant body 118, e.g., by polishing, grinding, etching, etc. According to another technique, the depression 124 may be formed by appropriately configuring a mold tool cavity which forms the encapsulant body 118 to form the depression 124 as a molded feature. In either case, forming the depression 124 in the upper surface 120 of the encapsulant body 118 allows for the upper ends of the vertical interconnect elements 116 and/or the interior surface portions 122 of the leads 102 to be exposed from the upper surface 120 of the encapsulant body 118. Meanwhile, the encapsulant body 118 comprises thicker portions 129 that are arranged between the sidewalls 126 and the outer edge sides of the encapsulant body 118. The leads 102 are anchored to the encapsulant body 118 by the thicker portions 129 and are electrically isolated from one another by the thicker portions 129. This embodiment makes it is possible to make leaded package, instead of leadless package.
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Additionally, a metal pad 134 is formed on the upper surface 120 of the encapsulant body 118. The metal pad 134 may be formed to directly contact the exposed interior surface portions 122 of the leads 102 and to directly contact the upper ends of the vertical interconnect elements 116. The metal pad 134 electrically connects the first load terminal 108 of the first semiconductor die 104 to a second group 136 of the leads 102, which comprises a number of leads that are not part of the first group of the leads 102. That is, the metal pad 134 forms a separate electrically conductive path between at least one of the leads 102 and the first load terminal 108 of the first semiconductor die 104. The metal pad 134 can therefore replace the need for other types of interconnect elements, such as bond wires, ribbons, clips, etc.
Due to its size, the metal pad 134 provides a low resistance connection between the first load terminal 108 of the first semiconductor die 104 and the leads 102. For instance, as shown, the metal pad 134 can be formed to occupy a large surface area, such as an area that covers substantially all of the first semiconductor die 104 and/or an area completely fills a region between the first and second sidewalls 126, 128 of the depression 124. As a result, the interconnection has a large current carrying capacity. Moreover, the arrangement of the metal pad 134 in the depression 124 allows for the metal pad 134 make contact with multiple ones of the leads 102 from the second group 136, thus distributing a load current amongst multiple leads 102 and reducing electrical resistance. Moreover, the large size of the metal pad 134 allows the metal pad 134 to be used separately as an electrical contact structure and/or a cooling structure that may be mated with an external heat sink. Furthermore, having this large-size metal pad 134 eliminates the need of a clip which is commonly used in power semiconductor package, which is expensive and difficult to assemble.
According to an embodiment, the conductive tracks 130 and/or the metal pad 134 are formed by a laser direct structuring technique. According to this technique, the encapsulant body 118 comprises a laser-activatable mold compound and a laser is applied to the upper surface 120 of the encapsulant body 118 at selected regions corresponding to the desired location of the conductive tracks 130 and/or metal pad 134, as the case may be. The applied laser energy creates laser activated regions in the encapsulant body 118, which forms complexes in the encapsulant body 118 that act as a nuclei for a metal plating process. Subsequently, a metal plating process is performed so as to selectively deposit metal in the laser activated regions without forming metal in adjacent locations of the encapsulant body 118 that do not comprise the complexes. This metal plating process may comprise an electroplating process, an electroless plating process, or both. In either case, the device is submerged in a chemical bath that contains metal ions (e.g., Cu+ ions, Ni+ ions, Ag+ ions, etc.) that react with the organic metal complexes in the laser activated regions, thereby forming the conductive tracks 130 and/or metal pad 134, as the case may be.
According to another embodiment, the conductive tracks 130 and/or the metal pad 134 are formed by a laser assisted metal deposition technique. According to this technique, a metal powder is applied to the upper surface 120 of the encapsulant body 118 at selected regions corresponding to the desired location of the conductive tracks 130 and/or metal pad 134, as the case may be. Subsequently, a laser beam is used to fuse the metal power together into a metal track and/or the metal pad 134 at the focal point of the laser beam.
According to another embodiment, the conductive tracks 130 and/or the metal pad 134 are formed by an ink jet metal printing process. According to this technique, a viscous ink comprising a liquid solvent and a conductive metal, e.g., Ag, Cu, etc., is applied by a printer head in the desired location and subsequently dried.
More generally, forming the conductive tracks 130 and the metal pad 134 can comprise any one or more of: a laser direct structuring technique, a laser assisted metal deposition technique, an electroplating technique, and an electroless plating technique. The conductive tracks 130 may be formed by the same technique as the metal pad 134 or a different technique as the metal pad 134. In the case that a laser direct structuring technique is not used to form either of the conductive tracks 130 and the metal pad 134, the encapsulant body 118 does not have to comprise a laser-activatable mold compound.
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As shown, the second semiconductor die 146 may be mounted directly on the first load terminal 108 of the first semiconductor die 144. Thus, the second load terminal (not shown) of the second semiconductor die 146 may face and electrically connect with the first load terminal 108 of the first semiconductor die 144. A conductive adhesive, e.g., solder, sinter, etc. may be used to effectuate this connection.
According to an embodiment, the stacked arrangement of the first semiconductor die 144 and the second semiconductor die 146 is arranged to form a half-bridge circuit. A half-bridge circuit refers to one type of circuit topology that is used in a power conversion circuit, such as a DC to DC converter, DC to AC converter, etc. A half-bridge circuit comprises a high-side switch connected in series with a low-side switch. One load terminal of the high-side switch (e.g., the drain) is connected to a first DC voltage (e.g., a positive potential), one load terminal of the low-side switch (e.g., the source) is connected to a second DC voltage (e.g., negative potential or ground), and the remaining two load terminals (e.g., the source of the high-side switch and the drain of the low-side switch) are connected together to form the output of the half-bridge circuit. The control terminals of the high-side and low-side switch (e.g., the gate terminals) can be switched according to a power control scheme (e.g., pulse width modulation) to produce a desired voltage and frequency at the output of the half-bridge circuit.
The second semiconductor die 146 may provide the high-side switch of the half-bridge circuit, the power transistor incorporated into the power transistor device block of the first semiconductor die 144 may provide the low-side switch of the half-bridge circuit, and the logic circuit incorporated into the logic block of the second semiconductor die 146 may provide the driver circuit of the half-bridge circuit.
As shown, the packaged semiconductor may additionally comprise a third semiconductor die 148 mounted on the die pad 100 and a fourth semiconductor die 150 mounted on top of the third semiconductor die 148. The third and fourth semiconductor dies 148, 150 may have the same configuration as the first and second semiconductor dies 144, 146 that are mounted in a stacked arrangement on the same the die pad 100. Thus, third semiconductor die 148 may comprise power transistor device block and a logic block monolithically integrated in third semiconductor die 148, and the fourth semiconductor die 150 may be configured as a discrete vertical transistor. Moreover, the stacked arrangement of the third semiconductor die 148 and the fourth semiconductor die 150 may be arranged to form a second half-bridge circuit. Thus, a full-bridge circuit may be realized. More generally, the stacking concept may be used to provide different types of multi-phase circuits, e.g., three phase circuits.
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The term “electrically connected” as used herein describes a permanent low-ohmic, i.e., low-resistance, connection between electrically connected elements, for example a wire connection between the concerned elements. Two elements may electrically connected by to one another by direct physical contact between the elements or by an electrically conductive intermediary, such as a wire, solder, contact pad, etc., provided between the elements.
Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second,” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
