This Utility patent application claims priority to German Patent Application No. 10 2017 212 457.1, filed Jul. 20, 2017, which is incorporated herein by reference.
This disclosure relates in general to a semiconductor package comprising a Ni plating and to a method for fabricating such a semiconductor package.
Semiconductor packages may comprise outer contacts that are covered by one or more metal layers. Such metal layers may e.g. be used to improve the electrical characteristics of the semiconductor package, to be able to connect the outer contacts to pads on a customer board, or to improve the durability of the outer contacts. Ni is an example for such a metal that is used to cover outer contacts. Fabrication of such metal layers may comprise several steps, may require expensive machinery, may comprise the use of costly catalysts and may be time consuming. Improved fabrication methods may help to overcome these problems and may also yield semiconductor packages with improved electrical and/or mechanical characteristics.
For these and other reasons, there is a need for improved semiconductor packages and for improved methods of fabricating semiconductor packages.
Various aspects pertain to a method for fabricating a semiconductor package, wherein the method comprises providing a substrate, at least partially encapsulating the substrate in an encapsulation body, depositing by electroplating a first Ni layer on a first surface of the substrate and depositing by electroless Ni plating a second Ni layer on the first Ni layer.
Various aspects pertain to a method for fabricating a semiconductor package, wherein the method comprises providing a substrate, wherein the substrate comprises on a first surface a first Ni layer, at least partially encapsulating the substrate and the first Ni layer in an encapsulation body and depositing by electroless Ni plating a second Ni layer on the first Ni layer.
Various aspects pertain to a semiconductor package, wherein the semiconductor package comprises an encapsulation body, a substrate, the substrate being exposed from the encapsulation body on a first main face and at least one side face of the encapsulation body, a first Ni layer arranged on the substrate at the first main face of the encapsulation body and a second Ni layer arranged on the first Ni layer and on the substrate at the at least one side face of the encapsulation body.
The accompanying drawings illustrate examples and together with the description serve to explain principles of the disclosure. Other examples and many of the intended advantages of the disclosure will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
h show side views of a semiconductor package in various stages of production according to an exemplary method of fabrication.
In the following detailed description, reference is made to the accompanying drawings. It may be evident, however, to one skilled in the art that one or more aspects of the disclosure may be practiced with a lesser degree of the specific details. In other instances, known structures and elements are shown in schematic form in order to facilitate describing one or more aspects of the disclosure. In this regard, directional terminology, such as “top”, “bottom”, “left”, “right”, “upper”, “lower” etc., is used with reference to the orientation of the Figure(s) being described. Because components of the disclosure can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In addition, while a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application, unless specifically noted otherwise or unless technically restricted. Furthermore, to the extent that the terms “include”, “have”, “with” or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprise”. The terms “coupled” and “connected”, along with derivatives thereof may be used. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other; intervening elements or layers may be provided between the “bonded”, “attached”, or “connected” elements. Also, the term “exemplary” is merely meant as an example, rather than the best or optimal. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
The semiconductor chip(s) described further below may be of different types, may be manufactured by different technologies and may include for example integrated electrical, electro-optical or electro-mechanical circuits and/or passives, logic integrated circuits, control circuits, microprocessors, memory devices, etc.
The semiconductor packages described below may include one or more semiconductor chips. By way of example, one or more semiconductor power chips may be included. Further, one or more logic integrated circuits may be included in the devices. The logic integrated circuits may be configured to control the integrated circuits of other semiconductor chips, for example the integrated circuits of power semiconductor chips. The logic integrated circuits may be implemented in logic chips.
The semiconductor chip(s) may be bonded to a carrier. The carrier may be a (permanent) device carrier used for packaging. The carrier may comprise or consist of any sort of material as, for example, metallic material, copper or copper alloy or iron/nickel alloy. The carrier can be connected mechanically and electrically with one or more contact elements of the semiconductor chip(s).
The semiconductor chip(s) may be covered with an encapsulation material in order to be embedded in an encapsulant (artificial wafer). The encapsulation material may be electrically insulating. The encapsulation material may comprise or be made of any appropriate plastic or polymer material such as, e.g., a duroplastic, thermoplastic or thermosetting material or laminate (prepreg), and may e.g. contain filler materials. Various techniques may be employed to encapsulate the semiconductor chip(s) with the encapsulation material, for example compression molding, injection molding, powder molding, liquid molding or lamination. Heat and/or pressure may be used to apply the encapsulation material.
In several examples layers or layer stacks are applied to one another or materials are applied or deposited onto layers. It should be appreciated that any such terms as “applied” or “deposited” are meant to cover literally all kinds and techniques of applying layers onto each other. In particular, they are meant to cover techniques in which layers are applied at once as a whole like, for example, laminating techniques as well as techniques in which layers are deposited in a sequential manner like, for example, sputtering, plating, molding, CVD, etc.
The semiconductor packages described below may be different types of packages and may for example be leadless semiconductor packages. A “leadless” semiconductor package may be a package, wherein outer contacts do not “stick out” of an encapsulation body of the package. Examples of such leadless packages are QFN (quad-flat no-leads), DFN (dual-flat no-leads) and TSNP (thin small non-leaded package). The semiconductor packages described below may be configured to be mounted to a customer board by surface mount technology (SMT). The semiconductor packages described below may comprise outer contacts that are exposed on a first main face of the semiconductor package and on at least one side face of the package. In particular, an exposed part of the outer contact one the first main face and on the at least one side face may be one contiguous exposed surface of the outer contact.
The semiconductor packages described below may comprise a substrate. The substrate may comprise the carrier and one or more outer contacts of the semiconductor package. The substrate may comprise a leadframe, wherein the carrier and the one or more outer contacts are parts of the leadframe. The substrate may comprise or consist of a metal or metal alloy like, e.g., Cu or Fe.
The semiconductor packages described below may comprise a first Ni layer arranged on the outer contact(s), in particular on an exposed surface of the outer contacts. The first Ni layer may be deposited on the outer contact(s). For example, a Ni electroplating process may be used to deposit the first Ni layer. Ni electroplating may comprise immersing the semiconductor package into an electrolyte solution and using the outer contact(s) as a cathode. According to an example, the semiconductor package is still part of an artificial wafer during the Ni electroplating process. In other words, the artificial wafer is immersed into the electrolyte solution as a whole. According to an example, the first Ni layer forms solely on the first main face of the semiconductor package, but not on the side faces.
According to an example, the semiconductor packages described below do not comprise a first Ni layer but a first metal layer comprising another metal like, e.g., Pd, that may act as a catalyst for the electroless Ni plating of the second Ni layer. For example, the first metal layer may be a first Pd layer.
According to an example, the first Ni layer is free of any phosphorus or boron. The first Ni layer may be a pure Ni layer except for small quantities of inevitable impurities stemming from the fabrication process.
The semiconductor packages described below may comprise a second Ni layer arranged on the first Ni layer. For example, an electroless Ni plating process may be used to deposit the second Ni layer on the first Ni layer. Electroless Ni plating is an autocatalytic reaction that does not require an electric current. Electroless Ni plating may comprise adding an additive like phosphorus (P) to the Ni. For example, the second Ni layer may comprise P at an amount of less than, about, or more than 5%, 8%, 10%, or 12% of the second Ni layer.
The second Ni layer may be deposited directly on top of the first Ni layer. Because the first Ni layer may act as a “seed layer” it may not be necessary to pre-treat the semiconductor package with, e.g., Pd prior to the electroless Ni plating process. In particular, it may not be necessary to provide a Pd layer onto which the second Ni layer can be deposited by electroless Ni plating. Therefore, the semiconductor packages described below may be free of any Pd layers. In particular, the semiconductor packages described below may be free of any Pd between the first Ni layer and the second Ni layer.
First outer contact surfaces 104A, 106A of the outer contacts 104, 106 may be exposed from the encapsulation body 102 at a first main face 100A of the semiconductor package 10 and outer contact side faces 104C, 106D may be exposed from the encapsulation body 102 at respective side faces 100C, 100D of the semiconductor package 10. Because of the exposed outer contact side faces 104C, 106D, the outer contacts 104, 106 may be termed side assist pads (SAPs). A second main face 100B of the semiconductor package 10 may be free of any outer contacts. The respective outer contact surfaces and side faces 104A, 104C and 106A, 106D may each form a contiguous outer contact surface of the respective outer contacts 104 and 106.
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The first Ni layer 110 may be arranged directly on the outer contacts 104, 106 and the second Ni layer 120 may be arranged directly on the first Ni layer 110 and directly on the outer contacts 104, 106 as described below.
The semiconductor package 100 may comprise one or more further layers arranged on the second Ni layer 120, for example a protection layer. The one or more further layers may e.g. comprise an Au layer, an Ag layer, a Pd layer, or a Sn layer.
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At the first main face 100A of the semiconductor package 100 the second Ni layer 120 may be arranged directly on the first Ni layer 110 and at the side faces 100C, 100D of the semiconductor package 100 the second Ni layer 120 may be arranged directly on the respective outer contacts 104, 106.
The first Ni layer 110 may have been deposited by a Ni electroplating process and the second Ni layer 120 may have been deposited by an electroless Ni plating process. The first Ni layer 110 may be free of P and the second Ni layer 120 may comprise P as described further above.
The first Ni layer 110 may have a thickness measured along the direction of the arrow A in
According to an example of a semiconductor package 100, a combined thickness of the first and second Ni layers 110, 120 measured along the arrow A is about or more than 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, or 10 μm.
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According to an example, the outer contact surfaces 104A, 106A are completely covered by the first Ni layer 110. According to another example, the outer contact surfaces 104A, 106A are only partially covered by the first Ni layer 110. For example, about or more than 10%, 20%, 30%, 40%, 50%, or 60% of the outer contact surfaces 104A, 106A are covered by the first Ni layer 110.
Prior to the formation (e.g. by deposition) of the first Ni layer 110 a chemical deflash process (e.g. to remove any mold bleed out) and/or a cleaning process (e.g. cleaning by use of a waterjet) may be performed in order to prepare the outer contact surfaces 104A, 106A for the formation of the first Ni layer 110.
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The presence of the first Ni layer 110 may significantly extend the time span that the singulated device 211 can be dipped into an etching bath without damaging the outer contacts 104, 106. For example, the time span may be extended by a factor of about 3.8.
After removal of the burrs 213, the outer contact side faces 104C, 106D may essentially comprise a surface roughness that is much smaller than the size of the burrs 213. This small surface roughness may be beneficial for the forming the second Ni layer 120 (see below) because the small surface roughness may improve the bonding between the outer contact side faces 104C, 106D and the second Ni layer 120.
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The semiconductor package 300 may further comprise a semiconductor chip that is electrically and/or mechanically coupled to the outer contacts 104, 106. The semiconductor package 300 may further comprise a further metal layer arranged on the second Ni layer 120.
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According to an example, the semiconductor package 400 comprises the further metal layer 215 described with respect to
The outer contacts 104, 106 and 501 may comprise exposed outer contact side faces on the side faces of the semiconductor package 500 as shown in
According to an example, the first Ni layer is deposited while the semiconductor package is part of an artificial wafer and the second Ni layer is deposited after singulation of the semiconductor package from the artificial wafer.
According to an example, the first Ni layer is formed while the semiconductor package is part of an artificial wafer and the second Ni layer is deposited after singulation of the semiconductor package from the artificial wafer.
While the disclosure has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure.
Number | Date | Country | Kind |
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10 2017 212 457.1 | Jul 2017 | DE | national |