Patent Application
20240047555
The present invention relates to semiconductor devices and, more particularly, to embodiments of a semiconductor structure including a field effect transistor (FET) and to embodiments of a method of forming the semiconductor structure.
Radio frequency (RF) integrated circuit (RFIC) chips could benefit from the inclusion of at least some FETs (e.g., at least some fin-type FETs (FINFETs)) with reduced effective gate lengths. However, conventional lithographic patterning techniques for defining gate critical dimension (CD) are limited. Furthermore, scaling the gate CD can result in a gate contact landing area that is too small. Additionally, in replacement metal gate (RMG) processing scaling the gate CD can result in a gate opening that is too small to fill with a RMG without the formation of voids or defects.
Disclosed herein are embodiments of a structure. The structure can include a gate structure. The gate structure can include a gate dielectric layer and a gate conductor layer. Additionally, the gate structure can have a first portion and a second portion. The first portion can be on a semiconductor body. The second portion can be on the first portion and can have an edge region that extends laterally beyond the first portion. The structure can further include a gate sidewall spacer. The gate sidewall spacer can have a first section, which is positioned laterally adjacent to the first portion of the gate structure between the edge region of the second portion of the gate structure and the semiconductor body, and a second section, which is positioned laterally adjacent to the first section and to the second portion of the gate structure. The gate sidewall spacer can be physically separated from the gate conductor layer by the gate dielectric layer.
Some embodiments of a structure disclosed herein can more specifically include a substrate and a field effect transistor (FET), such as a fin-type FET (FINFET), on the substrate. The FINFET can include a semiconductor fin. The FINFET can further include a gate structure. The gate structure can include a gate dielectric layer and a gate conductor layer. The gate structure can further have a first portion and a second portion. The first portion can be on the top surface and opposing sides of the semiconductor fin and the second portion can be on the first portion and can have an edge region that extends laterally beyond the first portion. The FINFET can further include a gate sidewall spacer with a first section and a second section. The first section of the gate sidewall spacer can be positioned laterally adjacent to the first portion of the gate structure between the edge region of the second portion of the gate structure and the semiconductor fin. The second section of the gate sidewall spacer can be positioned laterally adjacent to the first section and to the second portion of the gate structure. The gate sidewall spacer can be physically separated from the gate conductor layer by the gate dielectric layer. Optionally, the embodiment of the structure can further include an additional FINFET on the substrate and the additional FINFET can include an additional gate structure with a longer effective gate length than the gate structure.
Also disclosed herein are method embodiments for forming the disclosed structure embodiments. The method embodiments can include providing a substrate and forming, on the substrate, a structure. The structure can include a gate structure. The gate structure can include a gate dielectric layer and a gate conductor layer. Additionally, the gate structure can have a first portion and a second portion. The first portion can be on a semiconductor body. The second portion can be on the first portion and can have an edge region that extends laterally beyond the first portion. The structure can further include a gate sidewall spacer. The gate sidewall spacer can have a first section, which is positioned laterally adjacent to the first portion of the gate structure between the edge region of the second portion of the gate structure and the semiconductor body, and a second section, which is positioned laterally adjacent to the first section and to the second portion of the gate structure. The gate sidewall spacer can be physically separated from the gate conductor layer by the gate dielectric layer.
The present invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
As mentioned above, radio frequency (RF) integrated circuit (RFIC) chips could benefit from the inclusion of at least some FETs (e.g., at least some fin-type FETs (FINFETs) with reduced effective gate lengths. However, conventional lithographic patterning techniques for defining gate critical dimension (CD) are limited. Furthermore, scaling the gate CD can result in a gate contact landing area that is too small. Additionally, replacement metal gate (RMG) processing scaling the gate CD can result in a gate opening that is too small to fill with a RMG without the formation of voids or defects.
In view of the foregoing, disclosed herein are embodiments of a semiconductor structure including a substrate and, on the substrate, a FET (e.g., a FINFET) having a scaled effective gate length. Specifically, the FET can include a gate structure (e.g., an RMG structure) with a relatively short gate length proximal to a channel region, but a relatively large gate length distal to the channel region (e.g., for a relatively large surface area for contact landing). In some embodiments, the gate structure can include a first portion, which is within a narrow region of a gate opening proximal to the channel region, and a second portion, which is within a wider region of the same gate opening on the narrow region and distal to the channel region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. In other embodiments, the gate structure can include a first portion, which includes a relatively thick and short gate dielectric layer proximal to the channel region, and a second portion, which is on the first portion distal to the channel region, and which fills a gate opening. In this case, the second portion can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. In some embodiments, the semiconductor structure can further include, on the same substrate, an additional FET with a corresponding additional gate structure that does not have a scaled effective gate length. In each of the embodiments, gate sidewall spacers are on opposing sides of the gate structure (e.g., to isolate the gate structure from adjacent source/drain regions, respectively) and each gate structure has a first section and a second section with the first section positioned laterally adjacent to the first portion of the gate structure and the second section positioned laterally adjacent to the first section and to the second portion of the gate structure. The FET (e.g., the FINFET) as described above can exhibit improved performance because the disclosed gate structure configuration with the reduced effective gate length has the added benefit of lowering overlap capacitance and, thereby limiting performance degradation due to overlap capacitance. Also disclosed herein are method embodiments of forming the semiconductor structure including forming the FET, as described above, with a scaled effective gate length and, optionally, concurrently forming the additional FET without the scaled effective gate length.
Referring to
As mentioned above, the semiconductor structure 100.1, 100.2 can further include one or more FETs and, more particularly, at least one FET 1.1A, 1.2A with a scaled effective gate length. Optionally, as illustrated, the semiconductor structure 100.1, 100.2 can further include at least one additional FET 1.2A, 1.2B without a scaled effective gate length.
In any case, the FET 1.1A, 1.2A (and, if included, the additional FET 1.1B, 1.2B) can include a semiconductor body 110. The FET 1.1A, 1.2A (and, if included, the additional FET 1.1B, 1.2B) can further include a channel region 123 within the semiconductor body 110. The FET 1.1A, 1.2A (and, if included, the additional FET 1.1B, 1.2B) can further include source/drain regions 122 (e.g., doped semiconductor regions of the semiconductor body 110, doped epitaxial semiconductor regions filling trenches within the semiconductor body 110, or any other suitable type of source/rain regions). The FET 1.1A, 1.2A (and, if included, the additional FET 1.1B, 1.2B) can further include a channel region 123 within the semiconductor body 110 positioned laterally between the source/drain regions 122 and a gate structure (as discussed in greater detail below) on the semiconductor body 110 adjacent to the channel region 123. The channel region 123 can have a first type conductivity at a relatively low conductivity level. Alternatively, the channel region 123 can be an intrinsic region. The source/drain regions 122 can have a second type conductivity different from the first type conductivity at a relatively high conductivity level. Optionally, each FET can also include a source/drain extension region 121 on one or both sides of the channel region 123 extending to the adjacent source/drain region 122. The source/drain extension region(s) 121 can have the second type conductivity at a relatively low conductivity level.
The FET 1.1A, 1.2A can be an N-type FET (NFET) or a P-type FET (PFET). If included in the semiconductor structure 100.1, 100.2, the FET 1.1B, 1.2B can have the same type conductivity as the FET 1.1A, 1.2A or can have a different type conductivity. In other words, FETs 1.1A, 1.2A and 1.1B, 1.2B could both be NFETs, could both be PFETs, or can be a combination of N and PFETs. That is, the FET 1.1A, 1.2A could be an NFET and the FET 1.2A, 1.2B could be a PFET or vice versa. Those skilled in the art will recognize that, in any given FET within the structure, the first type conductivity and the second type conductivity mentioned above with regard to the channel and source/drain regions will vary depending upon whether the FET is an NFET or a PFET. Specifically, for an NFET, the first type conductivity of the channel region is P-type conductivity and the second type conductivity of the source/drain regions (and if applicable the source/drain extension region(s)) is N-type conductivity; whereas, for a PFET, the first type conductivity of the channel region is N-type conductivity and the second type conductivity of the source/drain regions (and if applicable the source/drain extension region(s)) is P-type conductivity. See the detailed discussion below regarding the material-specific dopants that can be implanted, diffused, or otherwise integrated into a semiconductor material in order to achieve either P-type conductivity or N-type conductivity.
The FET 1.1A, 1.2A can have a gate structure 126.1A, 126.2A with gate sidewall spacers 115A and a scaled effective gate length (L1). The optional additional FET 1.1B, 1.2B can have an additional gate structure 126.1B, 126.2B with gate sidewall spacers 115B but without a scaled effective gate length (i.e., with an effective gate length (L2) that is greater than L1).
It should be understood that the FET(s) in the disclosed semiconductor structure can be any type of FET, for example, planar FET(s), fin-type FET(s) (FINFET(s)), etc., with any type of gate structure. However, for purposes of illustration and, particularly, to illustrate the unique physical configuration of the gate structure with the scaled effective gate length (L1), the FET(s) of the semiconductor structure 100.1 of
Each FINFET can include one or more semiconductor bodies 110 specifically in the form of semiconductor fins. For purposes of this disclosure, a “semiconductor fin” refers to a relatively thin, elongated, semiconductor body. Ideally, a semiconductor fin will have a three-dimensional rectangular shape with a uniform width from the bottom of the semiconductor fin proximal to the substrate to the top of the semiconductor fin distal from the substrate. However, those skilled in the art will recognize that semiconductor fins are typically formed using a selective anisotropic etch process and, as a result of this process, the sidewalls of the semiconductor fins may not be exactly vertical (i.e., perpendicular to the bottom surface of the substrate) and the fin width may be somewhat non-uniform (e.g., wider proximal to the substrate). Optionally, each FINFET can include multiple parallel semiconductor fins. As illustrated, in the VV, XX, YY cross-sections, each FINFET is illustrated as having two semiconductor fins 110. However, it should be understood that each FINFET could include any number of one or more semiconductor fins. Furthermore, the number of semiconductor fins in the FINFETs could be the same (as illustrated) or different. In a bulk semiconductor structure, as illustrated, the semiconductor fin(s) 110 can be patterned and etched in the upper portion of the substrate 101 such that they extend essentially vertically from the substrate. In this case, an insulator layer 105 (e.g., a silicon dioxide layer) can be on the substrate 101 laterally surrounding the lower portion of each semiconductor fin and extending between the fins to form an isolation region. It should be noted that each semiconductor fin can be a discretely patterned semiconductor fin, as illustrated. However, again, the figures are not intended to be limiting. Alternatively, during processing relatively long semiconductor fins could be formed and shallow trench isolation regions (STI) regions (not shown) can segment the long semiconductor fins into multiple shorter semiconductor fins.
The RMG structure of the FINFETs can include at least a gate dielectric layer 124 and a gate conductor layer 125 on the gate dielectric layer 124. The gate dielectric layer 124 can include a high-K gate dielectric layer; and a gate conductor layer 125 can include one or more work function (WF) metal or metal alloy layers on the high-K gate dielectric layer and, optionally, a conductive fill material on the WF metal or metal alloy layer(s). Those skilled in the art will recognize that a high-K gate dielectric layer refers to a layer of dielectric material with a dielectric constant that is greater than the dielectric constant of silicon dioxide (i.e., greater than 3.9). Illustrative high-K dielectric materials include, but are not limited to, hafnium (HO-based dielectrics (e.g., hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium aluminum oxide, etc.) or other suitable high-k dielectrics (e.g., aluminum oxide, tantalum oxide, zirconium oxide, etc.). The WF metal or metal alloy layer(s) can be selected to achieve the optimal WF depending upon the conductivity type of the FET (i.e., optimal NFET WF for an NFET or optimal PFET WF for a PFET). Those skilled in the art will further recognize that the optimal WF for a gate conductor of an NFET will be, for example, between 3.9 eV and about 4.2 eV. Metals (and metal alloys) that have a work function within this range include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys thereof, such as, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. Those skilled in the art will further recognize that the optimal WF for a gate conductor of PFET will be, for example, between about 4.9 eV and about 5.2 eV. Metals (and metal alloys) that have a work function within this range include, but are not limited to, ruthenium, palladium, platinum, cobalt, and nickel, as well as metal oxides (aluminum carbon oxide, aluminum titanium carbon oxide, etc.) and metal nitrides (e.g., titanium nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, tantalum aluminum nitride, etc.). Alternatively, the WF metal or metal alloy layer(s) can be metal or metal alloy materials that are selected due to suitability for use in either NFETs or PFETs. The optional conductive fill material layer can be, for example, doped polysilicon or any suitable metal or metal alloy fill material including, but not limited to, tungsten, a tungsten alloy (e.g., tungsten silicide or titanium tungsten), cobalt, or aluminum.
In any case, those skilled in the art will recognize that, for a single-fin FINFET, the gate structure will be adjacent to the top surface and opposing sides of the single semiconductor fin. For a multi-fin FINFET, the gate structure will traverse all semiconductor fins and will be adjacent to the top and opposing sides of each semiconductor fin. Additionally, isolation of the FINFETs from the substrate 101 below and from each other is achieved through the insulator layer 105, which is below the gate structures, and further through one or more additional dielectric layers 107 (e.g., including one or more layers of dielectric material, interlayer dielectric (ILD) material) laterally surrounding the FINFETs. The ILD material can include, for example, one or more layers of silicon dioxide, silicon nitride, a doped silicon glass (e.g., phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG)), or any other suitable ILD material.
In the FET 1.1A, 1.2A, the gate structure 126.1A, 126.2A can include a first portion 261 and a second portion 262. The first portion 261 can be proximal to and, particularly, on and immediately adjacent to the top surface and opposing sides (see
In the optional additional FET 1.1B, 1.2B, instead of including two portions with different lengths, the gate structure 126.1B, 126.2B can have an approximately uniform length. That is, the gate structure 126.1B, 126.2B can have a length (L2) proximal to and, particularly, on and immediately adjacent to the top surface and opposing sides of the semiconductor fin(s) 110 at the channel region 123 therein. Furthermore, the gate structure 126.1B, 126.2B can have a length (L4) distal to the fin (e.g., at the top surface of the gate structure) and L4 can be approximately equal to L2. In this case, opposing sidewalls of the gate structure can be essentially planar and planar gate sidewall spacers 115B positioned laterally adjacent thereto. However, those skilled in the art will recognize that, due to processing variations (e.g., during gate stack patterning), the sidewalls of the gate structure 126.1B, 126.2B may not be perfectly parallel/vertical. Thus, although L2 and L4 are described as being approximately equal, it should be understood that L2 may vary somewhat (e.g., be longer or shorter) as compared to L4. Optionally, L2 and L4 of the gate structure 126.1B, 126.2B may also be approximately equal to the length L3 of the gate structure 126.1A, 126.2A (e.g., L1<L2˜L3˜L4).
In some embodiments, the difference between the effective gate lengths L1 and L2 of the gate structures 126.1A, 126.2A and 126.1B, 126.2B, respectively, could, for example, range from 4-10 nm or more or less. For example, in some embodiments, L2 could be 60 nm and L1 could be in the range of 50-56 nm. In other embodiments, L2 could be lower than 25 nm and L1 could be 1, 2, 3 or more nm less. It should be understood that these examples are not intended to be limiting.
Referring specifically to the gate structure 126.1A of the FINFET 1.1A of the semiconductor structure 100.1 of
Referring specifically to the gate structure 126.2A of the FINFET 1.2A of the semiconductor structure 100.2 of
It should be noted that the gate sidewall spacers (e.g., 115A and 115B) can be made of the same sidewall spacer material. This sidewall spacer material can be, for example, silicon nitride, silicon carbon nitride, silicon boron carbon nitride or any other suitable dielectric gate sidewall spacer material that will remain essentially intact during RMG processing (described in greater detail below with regard to the method embodiments) and that will provide the necessary isolation between the gate structure and the adjacent source/drain regions 122. Furthermore, in the gate sidewall spacers 115A, the first section 151 may include only this sidewall spacer material. That is, the sidewall spacer material may completely fill the cavity between the outer edge of the second portion 262 and the adjacent semiconductor fin 110. Alternatively, the first section 151 may include some sidewall spacer material and an airgap. That is, the sidewall spacer material may, during processing, pinch off prior to completely filling the cavity between the outer edge of the second portion 262 and the adjacent semiconductor fin 110, thus, forming an airgap (not shown).
Therefore, the semiconductor structure 100.1, 100.2 described above and illustrated in the figures includes one or more FETs including at least one FET 1.1A, 1.2A (e.g., at least one FINFET) with a scaled effective gate length and, optionally, at least one additional FET 1.2A, 1.2B (e.g., at least one additional FINFET) without a scaled effective gate length. It should further be noted that, although not illustrated, the semiconductor structure 100.1, 100.2 could optionally include multiple FETs (e.g., multiple FINFETs) where two or more of the FETs have different scaled effective gate lengths. In any case, any FET with a scaled effective gate length (e.g., FET 1.1A, 1.2A) could be employed, for example, in radio frequency (RF) device or any other device that could benefit from having a gate length that is less than that achievable by conventional processing techniques, whereas any FET without such a scaled effective gate length (e.g., FET 1.1B, 1.2B) could be incorporated into a logic device or other type of device where such a small effective gate length is not deemed critical.
Referring to the flow diagram of
The method can include providing a substrate (see process 302). For formation of a bulk semiconductor structure (as illustrated), a bulk semiconductor substrate can be provided at process 302. This bulk semiconductor substrate can include, for example, a bulk monocrystalline silicon substrate or a bulk substrate of some other suitable monocrystalline semiconductor material. Alternatively, for a semiconductor-on-insulator structure, a semiconductor-on-insulator (e.g., a silicon-on-insulator (SOI) substrate) can be provided at process 302.
The method can further include forming at least one semiconductor body for at least one field effect transistor (FET) on the substrate (see process 302 and
For purposes of illustration,
If the semiconductor fins 110 are patterned into the upper portion of a bulk semiconductor substrate, as illustrated, an insulator layer 105 (e.g., a silicon dioxide layer) can further be formed on the semiconductor substrate 101 over the semiconductor fins 110 and then recessed such that the insulator layer 105 laterally surrounds the lower portions of the semiconductor fins and extends laterally between adjacent semiconductor fins 110 (see
Sacrificial gate stack(s) for any FET(s) to be formed on the semiconductor substrate 101 can then be formed (see process 304 and
A mask 155 can then be formed over DR-B to protect the sacrificial gate structure therein (see process 306 and
Exposed vertical surfaces of the first material layer 111 of the gate stack in DR-A can be selectively laterally etched to undercut the second material layer 112 (see process 308 and
It should be noted that, due to the protection of the mask 155 over DR-B during process 308, the length (L2) of the first material layer 111 and the length (L4) of the second material layer 112 of any sacrificial gate stack in DR-B will remain the same (i.e., L2˜L4). Furthermore, depending upon patterning at process 304, L2 and L4 can also be approximately equal to L3 discussed above.
The mask 155 over DR-B can then be selectively removed and conventional FET processing (e.g., conventional FINFET processing) can be performed in order to complete the semiconductor structure 100.1 of
Following formation of the gate sidewall spacers, conventional source/drain processing can be performed (see process 312). Exemplary FINFET source/drain processing can include but is not limited to formation of source/drain extension regions 121 by dopant implantation (see
Following formation of source/drain regions 122, one or more additional dielectric layers 107 (e.g., including one or more layers of dielectric material, interlayer dielectric (ILD) material) can be deposited over the partially completed structure (see process 314 and
In order to form the semiconductor structure 100.1 of
Alternatively, in order to form the semiconductor structure 100.2 of
Additional processing can further be performed in order to complete the semiconductor structure (see process 342). This additional processing can include, but is not limited to, middle of the line (MOL) process to form contacts (not shown) to the source/drain regions and the gate structure of each FET as well as back end of the line (BEOL) processing. Such processing is well known in the art and, thus, the details thereof have been omitted from the specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments.
In the structures and method described above, a semiconductor material refers to a material whose conducting properties can be altered by doping with an impurity. Semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material and, more particularly, a semiconductor material that is not doped with an impurity for the purposes of increasing conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with an impurity for the purposes of increasing conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same base material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity) and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a Group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopant(s) in a given semiconductor region. Furthermore, when a semiconductor region or layer is described as being at a higher conductivity level than another semiconductor region or layer, it is more conductive (less resistive) than the other semiconductor region or layer; whereas, when a semiconductor region or layer is described as being at a lower conductivity level than another semiconductor region or layer, it is less conductive (more resistive) than that other semiconductor region or layer.
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises”, “comprising”, “includes”, and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching”, “in direct contact”, “abutting”, “directly adjacent to”, “immediately adjacent to”, etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
